Memory management method and storage device

Abstract

The present application provides a memory management method and a memory device. The method comprises: obtaining first count information corresponding to a target logical unit, wherein the first count information reflects a number of times that target data belonging to the target logical unit is updated within a first time range; obtaining second count information corresponding to the target logical unit, wherein the second count information reflects a number of times that the target data is updated within a second time range, wherein the second time range is different from the first time range; determining a hotness evaluation value corresponding to the target logical unit according to the first count information and the second count information; and determining whether the target data is hot data according to the hotness evaluation value. Thus, the operation efficiency and the operation stability of the memory device can be improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method and a storage device. Background Technology

[0002] In recent years, flash memory (flash storage modules) has gained increasing market share in the mainstream storage market due to its high stability, high read / write speeds, and low power consumption, and is widely used in various storage devices. However, due to its inherent physical characteristics, flash memory requires the entire physical block to be erased before a write operation can be performed. Therefore, garbage collection (GC) mechanisms are crucial for fully utilizing each storage unit of flash memory.

[0003] In practice, some types of storage devices use a simple counting mechanism to treat recently accessed data as hot data and store it centrally in specific blocks. This aims to increase the probability of most data in these blocks becoming invalid, thereby improving overall garbage collection efficiency by performing garbage collection on these blocks. Furthermore, the classification and management of hot and cold data can also be applied to other memory management programs, such as improving data retrieval speed by centrally storing hot data.

[0004] Therefore, improving the accuracy of thermal data identification to enhance system operating efficiency is a pressing issue that needs to be addressed. Summary of the Invention

[0005] The present invention provides a memory management method and a storage device that can improve the above-mentioned problems and improve the accuracy of identifying hot data, thereby improving the operating efficiency of the storage device.

[0006] Embodiments of the present invention provide a memory management method for a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of entity management units, and the memory management method includes: obtaining first counting information corresponding to a target logical unit, wherein the first counting information reflects the number of times target data belonging to the target logical unit is updated within a first time range; obtaining second counting information corresponding to the target logical unit, wherein the second counting information reflects the number of times the target data is updated within a second time range, wherein the second time range is different from the first time range; determining a heat evaluation value corresponding to the target logical unit based on the first counting information and the second counting information; and determining whether the target data is hot data based on the heat evaluation value.

[0007] Embodiments of the present invention further provide a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of entity management units, and the memory controller is used to: obtain first count information corresponding to a target logical unit, wherein the first count information reflects the number of times target data belonging to the target logical unit is updated within a first time range; obtain second count information corresponding to the target logical unit, wherein the second count information reflects the number of times the target data is updated within a second time range, wherein the second time range is different from the first time range; determine a heat assessment value corresponding to the target logical unit based on the first count information and the second count information; and determine whether the target data is hot data based on the heat assessment value.

[0008] Based on the above, after obtaining the first and second count information corresponding to the target logic unit, the heat assessment value corresponding to the target logic unit can be determined according to the first and second count information. Specifically, the first count information reflects the number of times the target data belonging to the target logic unit is updated within a first time range, and the second count information reflects the number of times the target data is updated within a second time range, where the second time range differs from the first time range. Subsequently, based on the heat assessment value, it can be determined whether the target data is hot data.

[0009] In other words, the memory management method and storage device proposed in this invention can effectively improve the accuracy of identifying hot data by monitoring and analyzing data update behavior within multiple predefined time ranges, thereby improving the operating efficiency and operational stability of the storage device. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram illustrating the operation of determining the heat assessment value corresponding to the target logic unit according to an embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram illustrating the operation of determining the heat assessment value corresponding to the target logic unit according to an embodiment of the present invention;

[0015] Figure 6This is a schematic diagram illustrating the categorized storage of cold / hot data from the host system according to an embodiment of the present invention;

[0016] Figure 7 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0019] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 via connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0020] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0021] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), or other similar device or combination of these devices. In one embodiment, memory controller 123 may include flash memory controller.

[0022] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0023] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0027] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(B). Each physical unit includes multiple storage units for non-volatile storage of data.

[0028] In one embodiment, an entity unit may include an entity programming unit. In one embodiment, an entity programming unit is also referred to as an entity programming unit. In one embodiment, an entity programming unit may be considered as an entity page.

[0029] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0030] In one embodiment, a physical programming unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on a physical programming unit to write data to that physical programming unit, multiple memory cells in that physical programming unit can be synchronously programmed to store the corresponding data. For example, when programming a physical programming unit, a write voltage can be applied to that physical programming unit to change the threshold voltage of at least some of the memory cells in that physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell.

[0031] In one embodiment, an entity erasure unit may include multiple entity programmatic units. In another embodiment, an entity erasure unit may be considered as an entity block.

[0032] In one embodiment, multiple programmed units in a physical erase unit can be erased simultaneously. For example, when an erase operation is performed on a physical erase unit, an erase voltage can be applied to multiple programmed units in this physical erase unit to change the threshold voltage of at least some of the memory cells in these programmed units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased.

[0033] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1) to 301(A) and 301(A+1) to 301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1) to 301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1) to 301(B) in the idle area 32 do not store any data (e.g., valid data).

[0034] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0035] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0036] In one embodiment, the memory control circuit 23 may be configured with a plurality of logic units 302(1) to 302(C) to map physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0037] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0038] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information in this management table (i.e., the logic-to-physical mapping table).

[0039] In one embodiment, the memory control circuit 23 may manage or access (i.e., access) the memory module 122 based on multiple entity management units. Each entity management unit may include one or more entity erase units. In one embodiment, an entity management unit is also referred to as a virtual block.

[0040] In one embodiment, each entity management unit may span multiple entity spaces within the memory module 122. For example, each entity space may refer to a memory die, a chip-enabled (CE) region, or a plane within the memory module 122. For example, multiple entity erase units (or multiple entity programming units) within a single entity management unit may be distributed across the aforementioned multiple entity spaces. Subsequently, the memory control circuitry 23 may synchronously (or sequentially) access the multiple entity erase units (or multiple entity programming units) within the single entity management unit.

[0041] In one embodiment, the memory control circuit 23 can acquire counting information (also called first counting information) corresponding to a certain logic unit (also called a target logic unit). For example, the target logic unit may be... Figure 3 The first counting information may reflect the number of times the data belonging to the target logic unit (also referred to as the target data) is updated within a certain time range (also referred to as the first time range). For example, assuming that the target data is updated 10 times within the first time range, the first counting information may include the value "10". However, the actual value included in the first counting information may be adjusted according to practical needs, and the present invention does not limit it.

[0042] In one embodiment, the update of the target data may be requested by the host system 11 (e.g., the host system 11 issues a write command to instruct the target data to be updated). In another embodiment, the update of the target data may also be actively performed by the memory control circuit 23 during the period when the memory control circuit 23 performs internal management or migration of data in the memory module 112.

[0043] In one embodiment, it is assumed that the target data was originally stored at a certain entity address (also referred to as a first sub-entity unit) of the memory module 112. For example, the first sub-entity unit may include one or more entity programmable units. The first sub-entity unit is mapped to the target logic unit. By updating the target data, the memory control circuit 23 can store the new data belonging to the target logic unit (i.e., the new target data) at another entity address (also referred to as a second sub-entity unit) of the memory module 112. For example, the second sub-entity unit may also include one or more entity programmable units. At the same time, in response to the update of the target data, the memory control circuit 23 can map the second sub-entity unit to the target logic unit (i.e., establish a mapping relationship between the second sub-entity unit and the target logic unit) and can remove the mapping relationship between the first sub-entity unit and the target logic unit. Therefore, after updating the target data, the data originally stored in the first sub-entity unit (i.e., the old target data) can be marked as invalid (i.e., the old target data becomes invalid data), while the data newly stored in the second sub-entity unit (i.e., the new target data) can be marked as valid (i.e., the new target data belongs to valid data).

[0044] In one embodiment, the memory control circuit 23 may acquire another counting information (also referred to as second counting information) corresponding to the target logic unit. The second counting information may reflect the number of times the data belonging to the target logic unit (i.e., the target data) is updated within another time range (also referred to as the second time range). For example, assuming the target data is updated 15 times within the second time range, the second counting information may include the value "15". However, the actual value included in the second counting information may be adjusted according to practical needs, and this invention is not limited thereto.

[0045] In one embodiment, the memory control circuit 23 can determine a heat assessment value corresponding to the target logic unit based on the first counting information and the second counting information. This heat assessment value can reflect the change (or trend) in the frequency and / or number of times the data belonging to the target logic unit (i.e., the target data) has been updated over multiple time ranges (at least including the aforementioned first and second time ranges). Then, the memory control circuit 23 can determine whether the target data is hot data based on this heat assessment value.

[0046] Figure 4This is a schematic diagram illustrating the operation of determining the heat assessment value corresponding to the target logic unit according to an embodiment of the present invention. Please refer to... Figure 4 Assume that the first time range includes time range 41, and the second time range includes time range 42. Time range 41 is between time point T(0) and T(1). Time range 42 is between time point T(1) and T(2).

[0047] In one embodiment, the memory control circuit 23 can automatically define time ranges 41 and 42. In particular, assuming that the current system time of the storage device 12 is at time point T(s), the time points in time range 41 are significantly further away from the current system time (i.e., time point T(s)) compared to the time points in time range 42. For example, the current system time of the storage device 12 can be managed and / or updated by the firmware of the memory control circuit 23.

[0048] In one embodiment, the memory control circuit 23 can monitor the number of times data 40 (i.e., target data) belonging to the target logic unit is updated within a time range 41 to obtain counting information 401 (i.e., first counting information). On the other hand, the memory control circuit 23 can monitor the number of times data 40 is updated within a time range 42 to obtain counting information 402 (i.e., second counting information).

[0049] After obtaining the counting information 401 and 402, the memory control circuit 23 can determine the heat evaluation value 411 corresponding to the target logic unit (or data 40) based on the counting information 401 and 402. For example, the memory control circuit 23 can input the counting information 401 and 402 into a computational model or a specific algorithm, and obtain the heat evaluation value 411 based on the output of this computational model or specific algorithm. For example, the heat evaluation value 411 can reflect the change (or trend) of the frequency and / or number of times the target logic unit (or data 40) is updated within the time range 41 and 42. After obtaining the heat evaluation value 411, the memory control circuit 23 can determine whether the data 40 is hot data (or cold data) based on the heat evaluation value 411.

[0050] Generally speaking, hot data refers to data that has been accessed by host system 11 relatively frequently over a period of time. Conversely, cold data refers to data that has been accessed by host system 11 relatively infrequently over a period of time.

[0051] Traditionally, memory controllers often directly count the frequency or number of times data belonging to a specific logical unit is accessed within a past time frame (e.g., 24 hours, 48 ​​hours, or 72 hours), and define data with a frequency or number exceeding a threshold as hot data. Then, a classification management mechanism for cold / hot data can be applied to manage the data in an attempt to improve the overall data access performance of the storage device.

[0052] However, in practice, this simple statistical mechanism may encounter a problem: even if the host system's long-term data access pattern is fixed (i.e., conforms to a specific trend), if the host system temporarily changes its data access pattern for some reason, frequently used data that was previously considered "hot" data may be immediately misclassified as infrequently used "cold" data, and vice versa. In this case, when the host system subsequently reverts to its original data access pattern, it may need to go through a period of low access performance to reclassify the cold / hot data before it can return to its long-term access performance.

[0053] However, the memory management method and storage device proposed in this invention can effectively improve the above-mentioned problems. In particular, the memory management method and storage device proposed in this invention can accurately identify cold / hot data in a long-term and stable manner based on the changing trends of data access statistically across multiple time ranges, thereby improving the operating efficiency of the storage device.

[0054] In one embodiment, the memory control circuit 23 can obtain difference information based on the first count information and the second count information. This difference information reflects the difference between the first count information and the second count information. Then, the memory control circuit 23 can determine the heat assessment value corresponding to the target logic unit based on this difference information.

[0055] by Figure 4 For example, assuming that count information 401 contains the value "10" and count information 402 contains the value "15", the memory control circuit 23 can obtain the corresponding difference information based on the count information 401 and 402. For example, this difference information can contain the value "5" (15-10=5). Then, the memory control circuit 23 can obtain the heat evaluation value 411 based on this difference information.

[0056] In one embodiment, the memory control circuit 23 can obtain accumulated information based on the first count information and the second count information. This accumulated information reflects the sum of the first count information and the second count information. For example, this accumulated value can be obtained by summing the first count information and the second count information. Then, the memory control circuit 23 can determine the heat assessment value corresponding to the target logic unit based on this accumulated information.

[0057] Similarly Figure 4 For example, assuming that count information 401 contains the value "10" and count information 402 contains the value "15", the memory control circuit 23 can obtain the corresponding accumulated information based on the count information 401 and 402. For example, this accumulated information can contain the value "25" (10+15=25). Then, the memory control circuit 23 can obtain the heat evaluation value 411 based on this accumulated information.

[0058] In one embodiment, the memory control circuit 23 may also consider the aforementioned difference information and accumulation information simultaneously to obtain the heat evaluation value. For example, the memory control circuit 23 may obtain the heat evaluation value according to the following formulas (1) to (4).

[0059] AC=V(1)+V(2)+V(3) (1)

[0060] V(1)=K1×C(t) (2)

[0061] V(2)=K2×(C(0)+C(1)…+C(t)) (3)

[0062] V(3)=K3×(C(t)-C(t-1)) (4)

[0063] In formulas (1) to (4), K1 is the proportional coefficient, K2 is the integral coefficient, and K3 is the differential coefficient. K1, K2, and K3 can be set according to practical needs. C(t-1) represents the first counting information, C(t) represents the second counting information, and "C(0)+C(1)…+C(t)" represents the sum of multiple counting information including the first and second counting information, and AC represents the heat evaluation value. In addition, V(1) represents the proportional evaluation value, V(2) represents the integral evaluation value, and V(3) represents the differential evaluation value.

[0064] According to formulas (1) to (4), the proportional evaluation value (i.e., V(1)), the integral evaluation value (i.e., V(2)), and the differential evaluation value (i.e., V(3)) can be obtained simultaneously or sequentially. Then, by summing the proportional evaluation value, the integral evaluation value, and the differential evaluation value, the heat evaluation value corresponding to the target logic unit (i.e., AC = V(1) + V(2) + V(3)) can be obtained.

[0065] In one embodiment, if Figure 4 Substituting the count information 401 and 402 obtained in the embodiment into the above formulas (1) to (4), the following formula (5) can be obtained:

[0066] AC=K1×C(1)+K2×(C(0)+C(1))+K2×(C(1)-C(0)) (5)

[0067] In formula (5), C(1) represents count information 402 (i.e., the second count information), C(0) represents count information 401 (i.e., the first count information), and AC represents the heat assessment value 411.

[0068] In other words, according to formulas (1) to (4), the past elapsed time can be divided into multiple time ranges, and the counting information corresponding to these time ranges can be integrated based on the three concepts of proportion, integral, and differential to gradually influence the final heat assessment value. Compared with the traditional method of only considering the short-term data access patterns of the host system to evaluate the cold / hot data, the automatic generation and adjustment mechanism for the heat assessment value of the target logical unit proposed in this embodiment of the invention will gradually update the heat assessment value of the target logical unit every time a new time range is elapsed. Thus, in addition to introducing the latest access pattern of the host system to the target logical unit, it can also avoid misjudgment or over-decision of cold / hot data in the short term due to temporary changes in the access pattern of the host system. It should be noted that the above formulas (1) to (4) can also be adjusted according to practical needs, and this invention does not limit them.

[0069] Figure 5 This is a schematic diagram illustrating the operation of determining the heat assessment value corresponding to the target logic unit according to an embodiment of the present invention. Please refer to... Figure 5 , continuing Figure 4 In one embodiment, after a period of time, it is assumed that the current system time is at a new time point T(s).

[0070] exist Figure 5 In this embodiment, the memory control circuit 23 may further define a new time range 51 between time points T(2) and T(3). Compared to the time points in time range 51, the time points in time range 41 or 42 are significantly further away from the current system time (i.e., time point T(s)).

[0071] In one embodiment, the memory control circuit 23 continuously monitors the number of times data 40 (i.e., target data) belonging to the target logic unit is updated within a time range 51 to obtain counting information 501. Then, the memory control circuit 23 can determine a heat assessment value 511 corresponding to the target logic unit (or data 40) based on the counting information 401, 402, and 501. For example, the memory control circuit 23 can input the counting information 401, 402, and 501 into a computational model or a specific algorithm, and obtain the heat assessment value 511 based on the output of this computational model or specific algorithm. After obtaining the heat assessment value 511, the memory control circuit 23 can determine whether data 40 is hot data (or cold data) based on the heat assessment value 511.

[0072] In one embodiment, if Figure 5 Substituting the count information 401, 402, and 501 obtained in the embodiments into the above formulas (1) to (4), the following formula (6) can be obtained:

[0073] AC=K1×C(2)+K2×(C(0)+C(1)+C(2))+K2×(C(2)-C(1)) (6)

[0074] In formula (6), C(2) represents count information 501 (i.e., the new second count information), C(1) represents count information 402 (i.e., the new first count information), C(0) represents count information 401 (also known as historical count information), and AC represents the heat assessment value 511.

[0075] In one embodiment, the memory control circuit 23 can obtain historical count information corresponding to the target logic unit (e.g., Figure 5 The counting information 401 in the memory is then used. The memory control circuit 23 can then adjust the heat assessment value corresponding to the target logic unit based on this historical counting information. Specifically, refer to the above formula (6), and formula (6) can also be adjusted according to practical needs. In addition, the total number of historical counting information can be gradually increased after a longer time range.

[0076] In one embodiment, after determining the heat assessment value corresponding to the target data, the memory control circuit 23 can compare this heat assessment value with a threshold value (also called a heat threshold value) to obtain a comparison result. This heat threshold value can be set according to practical needs or dynamically adjusted. This comparison result reflects the relative numerical relationship between the heat assessment value and the heat threshold value. For example, this comparison result may show that the heat assessment value is greater than, less than, or equal to the heat threshold value. Then, the memory control circuit 23 can determine whether the target data is hot data based on this comparison result.

[0077] In one embodiment, if the aforementioned comparison result shows that the heat assessment value is greater than the heat threshold value, the memory control circuit 23 can determine that the target data is hot data based on this comparison result. However, if the aforementioned comparison result shows that the heat assessment value is not greater than (e.g., less than or equal to) the heat threshold value, the memory control circuit 23 can determine that the target data is not hot data based on this comparison result.

[0078] In one embodiment, if the target data is determined to be hot data, the target data may be written (i.e. stored) to a certain type of entity management unit (also referred to as a first type of entity management unit) in the memory module 112. However, if the target data is determined to be non-hot data (i.e., cold data), the target data may be written to another type of entity management unit (also referred to as a second type of entity management unit) in the memory module 112.

[0079] In one embodiment, the first type of entity management unit can be considered as an entity management unit dedicated to storing hot data, while the second type of entity management unit can be considered as an entity management unit dedicated to storing cold data (or both hot and cold data can be stored). However, it should be noted that any entity management unit in the memory module 112 can only belong to either the first type of entity management unit or the second type of entity management unit at any given time.

[0080] Figure 6 This is a schematic diagram illustrating the categorized storage of cold / hot data from the host system according to an embodiment of the present invention. Please refer to... Figure 6 In one embodiment, the memory control circuit 23 may obtain a write instruction 61 corresponding to the target logic unit from the host system 11. The write instruction 61 is used to update the target data. For example, the write instruction 61 may instruct the old data belonging to the target logic unit (i.e., the old target data) to be updated with new data 62 (i.e., the new target data).

[0081] Upon receiving write instruction 61, memory control circuit 23 determines whether the target data (i.e., data 62) is hot data. If data 62 is determined to be hot data, memory control circuit 23 instructs memory module 122 to write data 62 to entity management unit 610. Entity management unit 610 belongs to the first type of entity management unit. However, if data 62 is determined not to be hot data (i.e., data 62 belongs to cold data), memory control circuit 23 instructs memory module 122 to write data 62 to entity management unit 620. Entity management unit 620 belongs to the second type of entity management unit. Similarly, more hot data from host system 11 can be centrally stored in entity management unit 610 (i.e., the first type of entity management unit), while more cold data from host system 11 can be centrally stored in entity management unit 620 (i.e., the second type of entity management unit). Subsequently, memory control circuit 23 can apply management strategies for hot data to entity management unit 610 and management strategies for cold data to entity management unit 620. This can effectively improve the access and / or management efficiency of the memory module 122.

[0082] In one embodiment, the memory control circuit 23 can count the number of times or frequency that the identified thermal data is updated within a first time range. Then, the memory control circuit 23 can adjust the length of a second time range based on this number or frequency. For example, if the number of times or frequency that the thermal data is updated within the first time range is not greater than (e.g., less than or equal to) a preset value, the memory control circuit 23 can set the length of the second time range to be the same as the length of the first time range. However, if the number of times or frequency that the thermal data is updated within the first time range is greater than this preset value, the memory control circuit 23 can set the length of the second time range to be shorter than the length of the first time range. For example, this preset value can be 0 or other values; the present invention is not limited thereto.

[0083] In one embodiment, the memory control circuit 23 can obtain historical heat assessment values ​​corresponding to the target logic cell. Then, the memory control circuit 23 can adjust the currently obtained heat assessment value based on the historical heat assessment values. Figure 4 and Figure 5For example, after obtaining the heat assessment value 411, the memory control circuit 23 can temporarily store the heat assessment value 411. Later, after obtaining the heat assessment value 511, the memory control circuit 23 can fine-tune the heat assessment value 511 based on the heat assessment value 411. For example, the memory control circuit 23 can determine whether the difference between the heat assessment value 511 and the heat assessment value 411 is greater than a difference threshold. If this difference is greater than the difference threshold, the memory control circuit 23 can adjust (e.g., increase or decrease) the heat assessment value 511 so that the difference between the adjusted heat assessment value 511 and the heat assessment value 411 is not greater than this difference threshold (i.e., by adjusting the heat assessment value 511, the difference between the heat assessment value 511 and the heat assessment value 411 is reduced). This avoids excessively significant numerical changes in the heat assessment value for the same target logic unit (or the same target data) within a short period, thus preventing misjudgment or over-decision. Furthermore, if the difference between the heat assessment value 511 and the heat assessment value 411 is not greater than this difference threshold, the memory control circuit 23 may not adjust the heat assessment value 511.

[0084] In one embodiment, the memory control circuit 23 can adjust the influence of the counting information (also known as target counting information) corresponding to a certain time range (also known as target time range) on the heat assessment value based on the time difference (also known as time distance) between a certain time range (also known as target time range) and the current system time. For example, this time difference (or time distance) can be negatively correlated with the influence of the target counting information on the heat assessment value.

[0085] by Figure 4 For example, compared to time range 42, the time difference (or time distance) between time range 41 and system time (e.g., time point T(s)) is larger. Therefore, compared to counting information 402, memory control circuit 23 can reduce the influence of counting information 401 on heat assessment value 411. Conversely, compared to time range 41, the time difference (or time distance) between time range 42 and system time (e.g., time point T(s)) is smaller. Therefore, compared to counting information 401, memory control circuit 23 can increase the influence of counting information 402 on heat assessment value 411.

[0086] Or, with Figure 5For example, compared to time ranges 42 and 51, the time difference (or time distance) between time range 41 and system time (e.g., time point T(s)) is larger. Therefore, compared to counting information 402 and 501, memory control circuit 23 can reduce the influence of counting information 401 on the heat assessment value 511. Conversely, compared to time ranges 41 and 42, the time difference (or time distance) between time range 51 and system time (e.g., time point T(s)) is smaller. Therefore, compared to counting information 401 and 402, memory control circuit 23 can increase the influence of counting information 501 on the heat assessment value 511.

[0087] In one embodiment, the memory control circuit 23 can configure different weight parameters for the historical counting information, the first counting information, and the second counting information. The configured weight parameters can be used to influence the influence of different types of counting information on the final obtained heat assessment value. For example, the memory control circuit 23 can sequentially configure weight parameters W(1), W(2), and W(3) to the historical counting information, the first counting information, and the second counting information. Among them, W(1) is less than W(2), and W(2) is less than W(3).

[0088] By using these specially configured weight parameters (e.g., W(1), W(2), and W(3)), the influence of historical count information that is furthest from the current system time on the final heat assessment value can be minimized, while the second count information that is closest to the current system time has the greatest influence on the final heat assessment value. Therefore, the heat assessment value can be gradually updated based on the changes (or trends) of different types of count information evaluated for different time ranges. This also avoids excessively significant numerical changes in the heat assessment value for the same target logical unit (or the same target data) within a short period, thus preventing misjudgments or over-decision.

[0089] In one embodiment, the memory control circuit 23 can monitor the response time (or average response time) of the storage device 12 (or memory module 122) corresponding to a write operation. For example, this write operation may be performed according to a write instruction from the host system 11, or it may be an autonomous data management or data migration of the memory module 122 initiated autonomously by the memory control circuit 23.

[0090] Furthermore, the response time (or average response time) is negatively correlated with the performance (or average performance) of the storage device 12 (or memory module 122) for write operations. That is, the higher the performance (or average performance) of the storage device 12 (or memory module 122) for write operations, the shorter the response time (or average response time) will be.

[0091] In one embodiment, the memory control circuit 23 can adjust the heat assessment value based on this response time (or average response time). For example, the adjusted heat assessment value can be negatively correlated with this response time (or average response time). That is, if the monitored response time (or average response time) of the storage device 12 (or memory module 122) corresponding to a write operation increases, the memory control circuit 23 can reduce the currently determined heat assessment value corresponding to the target data. This avoids adding additional computational burden to the storage device 12 when the data access efficiency of the storage device 12 decreases.

[0092] In one embodiment, the memory control circuit 23 can monitor the usage status of a plurality of logic units (also referred to as candidate logic units). For example, these candidate logic units may include Figure 3 At least some or all of the logic units 302(1) to 302(C) in the memory. Then, the memory control circuit 23 can determine (e.g., select) the target logic unit from these candidate logic units based on this usage state.

[0093] In one embodiment, if the aforementioned usage status reflects that the number of times or frequency of use of a certain logic unit (also referred to as the first candidate logic unit) among a plurality of candidate logic units in past write operations is higher than a preset value, the memory control circuit 23 may determine this first candidate logic unit as the target logic unit. However, if the aforementioned usage status reflects that the number of times or frequency of use of another logic unit (also referred to as the second candidate logic unit) among a plurality of candidate logic units in past write operations is not higher than the preset value, the memory control circuit 23 may not determine this first candidate logic unit as the target logic unit. This preset value can be set according to practical needs.

[0094] In one embodiment, the usage status of a certain logic unit can reflect the number of times data has been written to this logic unit within a past period (also known as the number of writes). In one embodiment, the memory control circuit 23 can determine at least one logic unit among the candidate logic units whose number of writes is greater than a threshold value as the target logic unit.

[0095] In one embodiment, the memory control circuit 23 can count the total number of times data has been written to multiple candidate logic units over a period of time. In another embodiment, the memory control circuit 23 can determine at least one logic unit among the candidate logic units whose percentage of writes in the total number of writes is higher than a percentage threshold as the target logic unit.

[0096] In one embodiment, the usage status of a logic unit can reflect the frequency percentage of data written to that logic unit over a past period (also known as the write frequency percentage). For example, the memory control circuit 23 can divide the frequency of data written to a logic unit over a past period (i.e., the write frequency) by the maximum frequency (or average frequency) of data written to that logic unit in the past to obtain the write frequency percentage of that logic unit. In one embodiment, the memory control circuit 23 can determine at least one logic unit among the candidate logic units whose write frequency percentage is greater than a frequency percentage threshold as the target logic unit.

[0097] In one embodiment, the memory control circuit 23 calculates the heat assessment value only for at least one logic unit selected as the target logic unit. That is, if a logic unit is not selected as the target logic unit, the memory control circuit 23 may not calculate its heat assessment value for that logic unit. This reduces the consumption of system computing and / or storage resources.

[0098] In one embodiment, the memory control circuit 23 may further adjust the popularity assessment value based on the number of times the target data has been accessed within at least one past time range. For example, this at least one time range may include the aforementioned first time range, second time range, and / or historical time range. For example, the adjusted popularity assessment value may be positively correlated with the number of times the target data has been accessed within the first time range, second time range, and / or historical time range.

[0099] In one embodiment, the memory control circuit 23 can adjust the heat threshold based on the first count information. For example, the first count information may be positively correlated with the adjusted heat threshold. That is, the higher the number of times the target data is updated within the first time range, the larger the determined heat threshold may be. This reduces the probability that target data that should not be considered hot data may be misclassified as hot data due to intensive updates or accesses to the target data that may only occur within a very short period of time.

[0100] In one embodiment, the memory control circuit 23 can obtain multiple heat assessment values ​​corresponding to the updated target data within a first time range. Each target data corresponds to one heat assessment value. On the other hand, the memory control circuit 23 can also obtain multiple write amplification parameters corresponding to these target data. Each target data also corresponds to one write amplification parameter. For example, the write amplification parameter corresponding to a certain target data can reflect the amplification factor of the amount of data written to store this target data. For example, if the write amplification parameter corresponding to a certain target data is "2.5", it means that the amplification factor of the amount of data written to store this target data is "2.5".

[0101] In one embodiment, the memory control circuit 23 can determine the smallest of the aforementioned plurality of write amplification parameters as the target write amplification parameter. After determining the target write amplification parameter, the memory control circuit 23 can determine the target data (also referred to as the first target data) corresponding to this target write amplification parameter from the aforementioned plurality of target data. Then, the memory control circuit 23 can set the heat assessment value (also referred to as the first heat assessment value) corresponding to the first target data as the heat threshold. Thus, by considering the write amplification parameters of multiple target data to set the heat threshold, the screening strategy for hot data can be further set to increase the probability of identifying data with potentially high write amplification factors as hot data. This can improve the write amplification problem for newly written data in the future.

[0102] In one embodiment, if a target data is determined to be hot data, the memory control circuit 23 can temporarily store this target data in the memory of the storage device 12. For example, this memory can be independent of the memory module 122. For example, this memory can be located in the memory controller 123. For example, this memory can include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), or other types of volatile memory. This can further improve the efficiency of updating or accessing this target data in a short time.

[0103] In one embodiment, if a target data is determined to be hot data, after storing the target data in the first type of entity management unit, the memory control circuit 23 can also simultaneously temporarily store the target data in the memory of the storage device 12. For example, after storing the target data in the first type of entity management unit, the memory control circuit 23 can keep the target data in the memory of the storage device 12 for a short period of time to facilitate repeated access. This further improves the efficiency of updating or accessing the target data in a short time.

[0104] On the other hand, if a target data is not hot data, the memory control circuit 23 can immediately discard or delete the target data from memory after storing it in the first type of entity management unit.

[0105] In one embodiment, the memory control circuit 23 can directly use the memory of the storage device 12 as a first-type entity management unit. Therefore, in one embodiment, after determining that a certain target data belongs to hot data, the memory control circuit 23 can directly store this target data in the memory of the storage device 12 without writing this target data to the memory module 122. This reduces the accelerated wear and tear on the memory module 122 caused by frequent updates of hot data.

[0106] In one embodiment, the first type of entity management unit may include an entity management unit operating based on SLC mode. In another embodiment, the second type of entity management unit may include an entity management unit not operating based on SLC mode. For example, the second type of entity management unit may include an entity management unit operating based on MLC, TLC, or QLC mode.

[0107] In one embodiment, the memory control circuit 23 can classify the entity management units according to the spatial distance between each entity management unit in the memory module 122 and the memory controller 123. This spatial distance is affected by the actual location of the memory controller 123 in the storage device 12 and the actual location of each entity management unit in the memory module 122.

[0108] In one embodiment, the classified entity management units may exhibit the following characteristic: the spatial distance between the first type of entity management unit and the memory controller 123 (also referred to as the first spatial distance) is smaller than the spatial distance between the second type of entity management unit and the memory controller 123 (also referred to as the second spatial distance).

[0109] In one embodiment, the memory control circuit 23 can identify at least one entity management unit whose spatial distance from the memory controller 123 is less than a spatial distance threshold as a first type of entity management unit. This improves the efficiency of subsequent access to target data from the first type of entity management unit. Alternatively, the memory control circuit 23 can identify at least one entity management unit whose spatial distance from the memory controller 123 is greater than this spatial distance threshold as a second type of entity management unit.

[0110] In one embodiment, the memory control circuit 23 can monitor the usage of multiple physical management units (also referred to as candidate physical management units) in the memory module 122. For example, the usage of a particular physical management unit may reflect or be positively correlated with the wear and tear of that physical management unit. For example, the memory control circuit 23 can determine the usage (or wear and tear) of a particular physical management unit based on its total erase / write cycles (PE cycles), total read cycles, and / or bit error rate. For example, the total erase / write cycles, total read cycles, and / or bit error rate of a particular physical management unit may be positively correlated with its usage (or wear and tear).

[0111] In one embodiment, the memory control circuit 23 can determine a first type of entity management unit from among these candidate entity management units based on their usage level. For example, the memory control circuit 23 can determine at least one entity management unit among these candidate entity management units whose usage level is below a usage level threshold as the first type of entity management unit. Thus, in the management strategy of cold / hot data classification storage, the overall wear and tear of the memory module 122 can be balanced, avoiding the rapid deterioration of the first type of entity management unit into bad blocks due to frequent reading, writing, and erasing of hot data.

[0112] In one embodiment, the memory control circuit 23 can divide the system into multiple logic management intervals. These logic management intervals correspond to multiple heat assessment value ranges. The memory control circuit 23 can group a target logic unit into one of these logic management intervals based on the heat assessment value corresponding to that target logic unit. For example, suppose the multiple logic management intervals include logic management intervals A to C. Logic management interval A covers heat assessment values ​​"1 to 3", logic management interval B covers heat assessment values ​​"4 to 6", and logic management interval C covers heat assessment values ​​"7 to 9". Suppose the heat assessment value corresponding to the target logic unit is "5", then the memory control circuit 23 can group this target logic unit into logic management interval B, which corresponds to the heat assessment value range of "4 to 6". It should be noted that the total number and division method of the multiple logic management intervals can be adjusted according to practical needs.

[0113] In one embodiment, each of the aforementioned logical management intervals can be bound to or matched with at least one first-type entity management unit that conforms to a specific lifecycle rule. Specifically, the heat assessment value range corresponding to a logical management interval can be positively correlated with the remaining lifespan of the bound or matched first-type entity management unit. For example, assuming a logical management interval has a relatively high heat assessment value range, the remaining lifespan of the first-type entity management unit bound to or matched with this logical management interval can be relatively long. Conversely, if a logical management interval has a relatively low heat assessment value range, the remaining lifespan of the first-type entity management unit bound to or matched with this logical management interval can be relatively short. Subsequently, when a target data is determined to be hot data, this target data can be written to the first-type entity management unit bound to or matched with the corresponding heat assessment value range. Thus, entity management units currently in different lifecycles can be precisely managed according to their possible usage frequency, thereby extending the overall lifespan of the memory module 122 and improving the operational stability of the storage device 12.

[0114] Figure 7This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 7 In step S701, first count information corresponding to the target logic unit is obtained, wherein the first count information reflects the number of times the target data belonging to the target logic unit is updated within a first time range. In step S702, second count information corresponding to the target logic unit is obtained, wherein the second count information reflects the number of times the target data is updated within a second time range, wherein the second time range is different from the first time range. In step S703, a heat assessment value corresponding to the target logic unit is determined based on the first count information and the second count information. In step S704, whether the target data is hot data is determined based on the heat assessment value.

[0115] However, Figure 7 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 7 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 7 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0116] In summary, the memory management method and storage device proposed in this invention can accurately identify cold / hot data in a long-term and stable manner based on the statistical trends of data access changes over multiple time periods. Furthermore, the memory management method and storage device proposed in this invention can also perform precise management of different types of entity management units specifically used for storing cold / hot data, based on spatial location and / or lifecycle. This improves the overall operating efficiency and operational stability of the storage device.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For use in a storage device, wherein the storage device includes a memory module, and the memory management method includes: Obtain first counting information corresponding to the target logic unit, wherein the first counting information reflects the number of times the target data belonging to the target logic unit is updated within a first time range; Obtain second counting information corresponding to the target logic unit, wherein the second counting information reflects the number of times the target data is updated within a second time range, wherein the second time range is different from the first time range; The updating of the target data includes: The new data belonging to the target logic unit is stored in another physical address in the memory module, wherein the other physical address is different from the original physical address where the old target data is stored. Map the other entity address to the target logical unit; and Mark the old target data stored at the original entity address as invalid; Based on the first counting information and the second counting information, a heat assessment value corresponding to the target logic unit is determined; and Based on the heat assessment value, determine whether the target data is hot data.

2. The memory management method according to claim 1, wherein each time point in the first time range is further away from the current system time than each time point in the second time range.

3. The memory management method according to claim 1, wherein the step of determining the heat assessment value corresponding to the target logic unit based on the first counting information and the second counting information includes: Based on the first counting information and the second counting information, obtain the difference information and the accumulation information; as well as Based on the difference information and the accumulated information, the heat evaluation value corresponding to the target logic unit is determined.

4. The memory management method according to claim 1, wherein the step of determining whether the target data is the hot data based on the heat assessment value includes: The heat assessment value is compared with the critical value to obtain the comparison result; as well as Based on the comparison results, determine whether the target data is the thermal data. The memory management method further includes: The threshold value is adjusted based on the first counting information.

5. The memory management method according to claim 1, further comprising: Obtain a write instruction corresponding to the target logic unit, wherein the write instruction is used to update the target data; If it is determined that the target data belongs to the hot data, the first target data indicated by the write instruction is written to the first type of entity management unit among the multiple entity management units of the memory module; as well as If it is determined that the target data does not belong to the hot data, the first target data is written to the second type of entity management unit among the plurality of entity management units.

6. The memory management method according to claim 5, further comprising: Monitor the usage of multiple entity management units of the memory module; as well as Based on the degree of use, the first type of entity management unit is determined from the plurality of entity management units.

7. The memory management method according to claim 5, wherein the first type of entity management unit spans multiple entity spaces, and each entity space refers to a memory chip, a chip enable region, or a plane in the memory module.

8. The memory management method according to claim 5, further comprising: If it is determined that the target data belongs to the hot data, the target data is temporarily stored in the memory of the storage device.

9. The memory management method according to claim 1, further comprising: The length of the second time range is adjusted based on the number or frequency of times the thermal data is updated within the first time range.

10. The memory management method according to claim 1, further comprising: Obtain the historical heat assessment value corresponding to the target logic unit; as well as The popularity assessment value is adjusted based on the historical popularity assessment value.

11. The memory management method according to claim 1, further comprising: Monitor the response time corresponding to the write operation, wherein the response time is negatively correlated with the performance of the storage device for the write operation; as well as The heat assessment value is adjusted based on the response time.

12. The memory management method according to claim 1, further comprising: Monitor the usage status of multiple candidate logic units; as well as Based on the usage status, the target logic unit is determined from the plurality of candidate logic units.

13. The memory management method of claim 12, wherein the step of determining the target logic unit from the plurality of candidate logic units according to the usage state includes: If the usage status reflects that the first candidate logic unit among the plurality of candidate logic units has a higher number of uses or usage frequency in multiple write operations than a preset value, the first candidate logic unit is determined as the target logic unit.

14. The memory management method according to claim 1, further comprising: The popularity assessment value is adjusted based on the number of times the target data is accessed.

15. The memory management method according to claim 1, further comprising: Based on the time difference between the target time range and the system time, adjust the influence of the counting information corresponding to the target time range on the popularity assessment value.

16. A storage device, characterized in that, include: Connection interface, used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to: Obtain first counting information corresponding to the target logic unit, wherein the first counting information reflects the number of times the target data belonging to the target logic unit is updated within a first time range; Obtain second counting information corresponding to the target logic unit, wherein the second counting information reflects the number of times the target data is updated within a second time range, wherein the second time range is different from the first time range; The updating of the target data includes: The new data belonging to the target logic unit is stored in another physical address in the memory module, wherein the other physical address is different from the original physical address where the old target data is stored. Map the other entity address to the target logical unit; and Mark the old target data stored at the original entity address as invalid; Based on the first counting information and the second counting information, a heat assessment value corresponding to the target logic unit is determined; and Based on the heat assessment value, determine whether the target data is hot data.

17. The storage device of claim 16, wherein the operation of determining the heat assessment value corresponding to the target logic unit based on the first counting information and the second counting information comprises: Based on the first counting information and the second counting information, the difference information is obtained; as well as Based on the difference information, the heat evaluation value corresponding to the target logic unit is determined.

18. The storage device of claim 16, wherein the memory controller is further configured to: Obtain a write instruction corresponding to the target logic unit, wherein the write instruction is used to update the target data; If it is determined that the target data belongs to the hot data, the first target data indicated by the write instruction is written to the first type of entity management unit among the multiple entity management units of the memory module; and If it is determined that the target data does not belong to the hot data, the first target data is written to the second type of entity management unit among the plurality of entity management units.

19. The storage device of claim 16, wherein the memory controller is further configured to: Monitor the usage status of multiple candidate logic units; and Based on the usage status, the target logic unit is determined from the plurality of candidate logic units.

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