A memory system supporting dual-mode access of cache and RAM and an access method thereof

Abstract

The application discloses a storage system supporting Cache and RAM dual-mode access and an access method thereof. The storage system comprises a data storage array, which is divided into a plurality of structured storage sub-blocks; a storage mode register, which is used for storing a configuration value, the configuration value being used for dynamically configuring each storage sub-block to work in a Cache mode or a RAM mode, so that the data storage array works in a full Cache mode, a full RAM mode or a Cache and RAM coexistence mode; and storage access control logic, which is used for arbitrating a storage access request, mapping the storage access request to a corresponding storage sub-block for read / write access according to an access address and the configuration value, and activating a storage sub-block mapped by the storage access request and deactivating a storage sub-block not mapped by the storage access request. The application dynamically configures, simultaneously supports Cache and RAM mode access, can configure part or all of storage banks as Cache or RAM, simultaneously utilizes the advantages of the two storage modes, supports parallel access of a plurality of storage sub-blocks, is flexible and efficient in use, and reduces power consumption.

Description

Technical Field

[0001] This invention relates to the field of computer system microarchitecture, specifically a storage system and its access method that support dual-mode access of cache and RAM. Background Technology

[0002] Modern processors employ data caching technology to improve core memory access efficiency. The cache memory resides between the processor core and a large-capacity storage medium (such as RAM), utilizing temporal and spatial locality to cache frequently used data, thereby reducing processor core memory access latency. Taking a 32-bit physical memory space as an example, without considering address mapping, the cache memory access addresses are organized as follows.

[0003]

[0004] in: Offset: m bits, indicating the size of a cache line. byte; Set: n bits, representing the address used to index cache lines, totaling... One Cache Set; Tag: 32-(m+n) bits, the high-order bits of the physical address of the data, used to determine whether the access address hits the tag value of the cache line.

[0005] For a directly mapped cache structure, the number of cache sets is... Each group has only one cache line, and the data storage array size is [size missing]. bytes, tag array size is Bit; For a set-associative cache structure, assuming it is w-way set-associative and the data storage array size is... bytes, total There are 1 tag, and the tag array size is 1. ; For a fully associative cache structure, n is 0, meaning there is only one set. Assuming there are w paths, the data storage array size is... bytes, tag array size is .

[0006] In addition, each tag includes a valid bit, indicating whether there is valid data at that location. For caches that support data consistency protocols, each tag also includes a consistency status bit. When accessing the cache, the corresponding set must first be indexed based on the address, and then the validity of the tag in the set is checked. Simultaneously, the high-order bits of the accessed address are compared with the tag in the set to determine if the accessed data is cached in the cache. The cache storage space can be much larger than the cache's own capacity, which may lead to data overrun and subsequent eviction.

[0007] Generally, processors have a multi-level cache system. The first-level cache uses a Harvard architecture to separate instructions and data, while the second-level cache shares the same space. Smaller cache levels are closer to the core, resulting in shorter access latency but limited storage space; larger cache levels are farther from the core, leading to longer access latency but more storage space. Multiple cache levels work together to improve overall hit rate and reduce core data access latency. With advancements in storage technology, on-chip storage density has gradually increased, and read / write latency has gradually decreased, allowing modern processors to use larger-capacity on-chip memory to construct cache systems.

[0008] However, cache storage also has the following problems: Data inside the cache is adaptively loaded and evicted by the processor core during read and write operations. It can be prefetched through software interface or dedicated instructions, or the data can be actively flushed out. However, data in the cache cannot be directly indexed. When the accessed dataset is small, the cache storage space cannot be fully utilized, resulting in wasted resources. If the addressing space of multiple frequently used data blocks happens to map to the same region in the cache, it will cause data thrashing and reduce memory access performance.

[0009] In some scenarios, applications may want to use cache storage space as RAM. Frequently used programs or data can be directly accessed via the nearest index after loading, eliminating the need to maintain data loading and eviction during runtime, making it more convenient. The corresponding tag array can be powered off or clocked off to save energy. Furthermore, the cache space used as RAM can be read and written at high speed via the DMA interface, without requiring the interrupt core to move data, making data exchange more efficient. Summary of the Invention

[0010] To address the shortcomings of the prior art, this invention provides a storage system and its access method that support dual-mode access of Cache and RAM. The storage structure of this invention can be dynamically configured and supports access of both Cache and RAM modes simultaneously. As needed, some or all of the storage can be configured as Cache or RAM, thus utilizing the advantages of both storage modes for greater flexibility and efficiency.

[0011] To achieve the above technical objectives, the present invention adopts the following technical solution: a storage system supporting dual-mode access of Cache and RAM, comprising: The data storage array is divided into multiple structured storage sub-blocks; A storage mode register is used to store configuration values, which are used to dynamically configure each of the storage sub-blocks to work in cache mode or RAM mode, thereby enabling the data storage array to work in full cache mode, full RAM mode, or cache and RAM coexistence mode. Storage access control logic is used to arbitrate storage access requests. Based on the access address and the configuration value, the storage access request is mapped to the corresponding storage sub-block for read and write access. The storage sub-block mapped by the storage access request is activated, while the storage sub-block not mapped by the storage access request is not activated.

[0012] The storage capacity of the multiple storage sub-blocks is different.

[0013] The formula for calculating the storage capacity of the storage sub-block is as follows: (Formula 1); in, This is the total storage capacity of the data storage array. is the storage capacity of the i-th storage sub-block, and x is the total number of storage sub-blocks. It is the storage capacity of the x-th storage sub-block, where, x is a positive integer greater than or equal to 1; when hour, This indicates that there is only one such storage sub-block; when hour, and definition This indicates that there are two storage sub-blocks with the same storage capacity. when hour, and definition This indicates that there are 3 storage sub-blocks, and the first 2 storage sub-blocks have the same storage capacity, while the storage capacity of the 3rd storage sub-block is twice that of the 2nd. when When, define , indicating that there are x storage sub-blocks, and the storage capacity of the xth storage sub-block is twice that of the (x-1)th storage sub-block.

[0014] when At that time, it can be known that: ; ; ; And so on, ; therefore, (Formula 2); According to Formula 2, (Formula 3); According to formulas two and three, when When known, then ; When x and s are known, then That is, the size of the first storage sub-block is .

[0015] The bit width of the configuration value is The bit width is 3, where x is the number of storage sub-blocks. When x is 4, the configuration bit width is 3. When the configuration value is 000b, each of the storage sub-blocks operates in RAM mode, making the data storage array operate in full RAM mode; When the configuration values ​​are 001b, 010b, and 011b, a portion of the storage sub-blocks operate in RAM mode, and the remaining portion of the storage sub-blocks operate in Cache mode, so that the data storage array operates in a Cache and RAM coexistence mode. When the configuration value is 1XXb, each of the storage sub-blocks operates in cache mode, making the data storage array operate in full cache mode.

[0016] When the data storage array operates in a cache and RAM coexistence mode, access to the cache and RAM is independent of each other; And when the configuration values ​​are different: The access address organization of the storage sub-blocks operating in Cache mode is different, and the larger the storage capacity of the storage sub-block, the wider the Set segment used as the index and the shorter the Tag segment used for matching and searching in the corresponding access address. The spatial base address of the storage sub-block operating in RAM mode remains unchanged, and the corresponding end address increases when the configuration value increases.

[0017] Each of the storage sub-blocks is associated with a Tag array, which is used to store address tags and is activated when the storage sub-block is operating in Cache mode to support data matching and lookup. The logical structure of the Tag array is the same as that of the Cache structure.

[0018] An access method for a storage system that supports dual-mode access of cache and RAM includes the following steps: According to the configuration value of the storage mode register, the working mode of each storage sub-block is configured, wherein the working mode is Cache mode or RAM mode, thereby enabling the data storage array to work in full Cache mode, full RAM mode, or Cache and RAM coexistence mode, wherein the data storage array is divided into multiple structured storage sub-blocks; Arbitrate storage access requests and map the storage access request to the corresponding storage sub-block for read and write access based on the access address and the configuration value. The storage sub-block mapped by the storage access request is activated, while the storage sub-block not mapped by the storage access request is not activated.

[0019] Based on the working mode of the storage sub-block, the lookup index form of each storage sub-block is determined, wherein the lookup index form includes the storage sub-block number generated from the access address and the index value within the storage sub-block, as well as the request tag bit of the cache space, and the index value is used to access the tag array and the data storage array; When the storage sub-block is working in Cache mode, the corresponding Tag array and the data storage array work simultaneously. Each time it is accessed, the storage sub-block with the matching number is searched for index. When the storage sub-block is operating in RAM mode, the storage sub-block is accessed directly according to the number and the index value; The storage sub-blocks operating in Cache mode and the storage sub-blocks operating in RAM mode can be accessed in parallel.

[0020] When accessing the Tag array, if the Tag of a certain path in the corresponding Set segment matches the high segment of the access address, the cache is hit; otherwise, it is not hit. At the same time, it is checked whether the access address falls within the RAM space under the current configuration value. If it does, the RAM is hit; otherwise, it is not hit. For read operations: When accessing the storage sub-block configured in Cache mode, the data storage array can be accessed simultaneously with the Tag array, or the data storage array can be accessed after the Tag array is accessed. Specifically, when the data storage array and Tag array are accessed simultaneously, since no hit result is obtained, data in each path is accessed simultaneously based on the index value, and the hit path data is selected only after a hit result is obtained. When the data storage array is accessed after the Tag array is accessed, since the hit result is already known, only the hit path array is accessed. When accessing the storage sub-block configured in RAM mode, if a hit occurs, the data storage array can be directly accessed; For write operations: When accessing the storage sub-block configured in Cache mode, the data storage array can only access it after obtaining hit path information; When accessing the storage sub-block configured in RAM mode, if a hit occurs, direct access is possible.

[0021] In summary, the present invention has achieved the following technical effects: This invention discloses a storage structure and access method that simultaneously supports both cache and RAM modes. Users can dynamically divide the data storage array into cache or RAM space through a mode configuration register. For a storage array configured as a cache, various organizational structures are supported, such as direct mapping, set-associative, and fully associative. The corresponding tag array is activated to support data matching and lookup. For a storage array configured as RAM, the corresponding tag array can be powered off or its clock can be turned off to save energy. The core can directly access RAM based on address space mapping, and the external DMA engine can also perform data transfer when the core is not accessing RAM to improve data exchange efficiency. The storage array can be configured as full cache, full RAM, or a coexistence of cache and RAM. When configured as a coexistence of cache and RAM, the two spaces are independent of each other. The cache storage array only caches data in the lower-level RAM and the cacheable space of the storage medium, and does not cache data in the same-level or higher-level RAM. The RAM array can be accessed in parallel with the cache array, but the two will not hit at the same time. This invention dynamically divides the same storage space into Cache, RAM, or a coexistence of both through different access logics and configuration values, exhibiting completely different storage characteristics, making full use of storage space, and achieving high resource utilization. Cache storage arrays and RAM storage arrays can be accessed in parallel, improving the overall throughput of the storage system. Only the requested storage sub-block is activated during each access, and the corresponding tag array configured as RAM can have its clock turned off or disabled, thus reducing power consumption. Attached Figure Description

[0022] Figure 1 This is a distribution diagram of the storage sub-blocks occupied by RAM and Cache under each configuration; Figure 2 It is a schematic diagram of the storage array's organizational structure, access control flow, and data flow. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings.

[0024] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

[0025] Example: A storage system supporting dual-mode access of cache and RAM includes: The data storage array is divided into multiple structured storage sub-blocks; The storage mode register is used to store the configuration value (MMODE). The configuration value is used to dynamically configure each storage sub-block to work in cache mode or RAM mode, thereby enabling the data storage array to work in full cache mode, full RAM mode, or cache and RAM coexistence mode. Storage access control logic is used to arbitrate storage access requests. Based on the access address and the configuration value, the storage access request is mapped to the corresponding storage sub-block for read and write access. The storage sub-block mapped by the storage access request is activated, while the storage sub-block not mapped by the storage access request is not activated.

[0026] This invention allows applications to configure part or all of the storage space as Cache or RAM as needed, which can take advantage of the advantages of both storage structures at the same time, improve storage utilization and application execution efficiency, and make the usage more flexible and efficient.

[0027] In this invention, the storage capacities of multiple storage sub-blocks are different and satisfy a certain increasing relationship.

[0028] Furthermore, assume that the storage capacity of the cache data storage array is... Bytes. This invention divides the data storage array into... There are 10 sub-blocks, and the storage capacity of these sub-blocks is 1000. This enables the sharing of storage space between cache and RAM, and allows for flexible configuration between cache and RAM.

[0029] The formula for calculating the storage capacity of a storage sub-block is: (Formula 1); in, This is the total storage capacity of the data storage array. is the storage capacity of the i-th storage sub-block, and x is the total number of storage sub-blocks. It is the storage capacity of the x-th storage sub-block, where, x is a positive integer greater than or equal to 1; when hour, This indicates that there is only one storage sub-block; it also indicates that this storage sub-block is either a cache or RAM. when hour, and definition This indicates that there are two storage sub-blocks with the same storage capacity; when hour, and definition This indicates that there are 3 storage sub-blocks, and the first 2 storage sub-blocks have the same storage capacity, while the storage capacity of the 3rd storage sub-block is twice that of the 2nd. when When, define , indicating that there are x storage sub-blocks, and the storage capacity of the x-th storage sub-block is twice that of the (x-1)-th storage sub-block. That is, the storage capacity of the 4th storage sub-block is twice that of the 3rd, the 5th is twice that of the 4th, and so on.

[0030] From the above definition, it can be seen that when hour: ; ; ; And so on, ; therefore, (Formula 2); According to Formula 2, (Formula 3); According to formulas two and three, when When known, then ; When x and s are known, then That is, the size of the first storage sub-block is .

[0031] In summary, given the number of storage sub-blocks to be divided... The storage capacity of the first storage sub-block can be obtained as follows: This allows us to determine the storage capacity of each subsequent sub-block.

[0032] Given the storage capacity of the first storage sub-block Therefore, the number of storage sub-blocks is... indivual.

[0033] This invention provides a formula for calculating the storage capacity of each storage sub-block, making it easy to understand the storage capacity of each sub-block and the number of sub-blocks. Knowing the storage capacity and number of sub-blocks facilitates subsequent configuration and access.

[0034] This invention sets the data storage array as a divisible data array and uses configuration values ​​to achieve dynamic configuration of the mode, thereby improving the flexibility of the storage structure.

[0035] In this invention, the bit width of the configuration value is The bit width is 3, where x is the number of storage sub-blocks. When x = 4, the bit width is 3. This embodiment takes a bit width of 3 as an example.

[0036] In this embodiment, the configuration values ​​are 000b, 001b, 010b, 011b, and 1XXb, which can configure the working mode of the storage sub-blocks respectively. Each configuration value corresponds to a working mode. When the configuration value changes, the working mode of the storage sub-block also changes accordingly. Therefore, the present invention can dynamically adjust the working mode of the storage sub-block by changing the configuration value, thereby changing the working mode of the entire data storage array.

[0037] When the system has been running for a period of time and the user needs to change the operating mode, the user changes the configuration value. At this time, due to the change in the configuration value, the operating mode of the system changes, which replaces the hard rules that cannot be changed by coding in the existing technology and can be used flexibly.

[0038] Specifically, when the configuration value is 000b-1XXb, the corresponding data storage array operating mode is as follows: (1) When the configuration value is 000b, each storage sub-block works in RAM mode, making the data storage array work in full RAM mode; (2) When the configuration values ​​are 001b, 010b, and 011b, a portion of the storage sub-blocks work in RAM mode, and the remaining portion of the storage sub-blocks work in Cache mode, so that the data storage array works in a Cache and RAM coexistence mode. (3) When the configuration value is 1XXb (X represents 0 or 1), each storage sub-block works in Cache mode, making the data storage array work in full Cache mode.

[0039] This embodiment uses a storage device with a data capacity of 32KB as an example to illustrate how a data storage array that supports both Cache and RAM dual-mode storage mapping performs storage mapping.

[0040] Assuming a 32KB memory bank is divided into four sub-blocks, the sizes of these sub-blocks would be 4KB, 4KB, 8KB, and 16KB, respectively, based on their capacity relationships. Users can configure the spatial attributes of the data storage array using the 3-bit storage mode register MMODE.

[0041] When the data storage array is used as RAM, the address space is pre-allocated and set by the system. It is assumed that the fixed addressing range of the storage space is 0001_0000h - 0001_7FFFh.

[0042] When used as a cache data array, assuming the cache is a 2-way set-associative structure, the cache line size is 512 bits, or 64 bytes.

[0043] The organization of the data storage array under different MMODE modes is shown in the table below: Table 1 Storage Space Mapping Method

[0044] From the table, we can see that: (1) When MMODE is 000b, the entire storage is configured as RAM, occupying the complete 0001_0000h - 0001_7FFFh space. At this time, the storage array cannot be used as a cache.

[0045] (2) When MMODE is configured to 001b to 011b, RAM and Cache coexist. That is, when the data storage array is working in the Cache and RAM coexistence mode, the access to Cache and RAM is independent of each other. Where the configuration values ​​are different: The access address organization of storage sub-blocks operating in Cache mode is different. The larger the storage capacity of the storage sub-block, the wider the Set segment used as the index in the corresponding access address, and the shorter the Tag segment used for matching and searching. The base address of the storage sub-block operating in RAM mode remains unchanged, but the corresponding end address increases when the configuration value increases.

[0046] In this configuration, the higher segment of the address space is used as cache, and the lower segment is used as RAM. Alternatively, depending on requirements, the lower segment can be used as cache and the higher segment as RAM; this embodiment uses the former. The cache access address organization differs for each configuration. The larger the cache storage capacity, the wider the Set segment used as the index in the access address, and the shorter the Tag segment used for matching and lookup. The RAM space base address remains unchanged, but the upper limit of the storage space varies accordingly with the configuration size. Cache and RAM accesses are independent. The cache does not cache data in the same level of RAM. Using addresses within the RAM address range but not within the RAM space allows for determining whether to access data in the cache based on requirements.

[0047] (3) When MMODE is configured as 1XXb (X can be 0 or 1), the entire 32KB memory is used as a cache. At this time, there is no RAM. If you still access it with the RAM space address, an error will be reported or the access request will be forwarded to the next level of storage system.

[0048] In this invention, each storage sub-block is associated with a Tag array. The Tag array is used to store address Tag tags and is activated when the storage sub-block is working in Cache mode to support data matching and lookup. The logical structure of the Tag array is the same as the Cache structure, that is, the number of Tag paths is the same as the number of Cache paths.

[0049] The distribution of storage sub-blocks occupied by RAM and Cache under each configuration is as follows: Figure 1 As shown, each storage sub-block is equipped with several Tag arrays for use when the storage sub-block is configured as a cache. The number of Tag arrays is the same as the number of cache paths. For example, in a 2-way set-associative cache, each storage sub-block is equipped with 2 Tag arrays.

[0050] The width of the Tag array varies depending on the configuration. When MMODE is 001, Seg0 is used as the only cache, and the cache capacity is only 4KB. When MMODE is 010, Seg0 and Seg1 are used as caches at the same time, and the cache capacity is 8KB. The index has 1 more bit, and the Tag will have 1 less bit, and so on.

[0051] For example, the Tag array corresponding to the storage sub-block Seg0 has the widest width, including address bits [31:11], which is sufficient to accommodate Tag under various configurations. The Tag array corresponding to Seg2 only needs to contain address bits [31:13], because the Seg2 sub-block will only be used as a cache when MMODE is 011b and 1XXb. At this time, the cache capacity is not less than 16KB, the Set becomes longer, and the Tag becomes shorter.

[0052] To facilitate tag comparison, all tag arrays can be set to the same tag width as in the minimum cache configuration, and the corresponding addresses can be stored in them. The tag arrays in higher segments may overlap with the set index, but the overlapping part is certain. For example, the redundant storage of bits [13:12] in the tag array of Seg3 must be 00b, and the corresponding set index [13:12] bits of Seg3 must also be 00b.

[0053] In another embodiment, the present invention provides an access method for a storage system supporting dual-mode access of cache and RAM, comprising the following steps: based on the storage system supporting dual-mode access of cache and RAM described above, S10. Configure the working mode of each storage sub-block according to the configuration value of the storage mode register, wherein the working mode is Cache mode or RAM mode, so that the data storage array works in full Cache mode or full RAM mode or Cache and RAM coexistence mode, wherein the data storage array is divided into multiple structured storage sub-blocks. S20. Arbitrate storage access requests. Based on the access address and the configuration value, map the storage access request to the corresponding storage sub-block for read and write access. The storage sub-block mapped by the storage access request is activated, while the storage sub-block not mapped by the storage access request is not activated.

[0054] Specifically, based on the working mode of the storage sub-block, the lookup index form of each storage sub-block is determined, wherein the lookup index form includes generating the number of the storage sub-block and the index value within the storage sub-block from the access address, as well as the request tag bit of the cache space, and the index value is used to access the tag array and the data storage array; When the storage sub-block is working in Cache mode, the corresponding Tag array and the data storage array work simultaneously. Each time it is accessed, the storage sub-block with the matching number is searched for index. When the storage sub-block is operating in RAM mode, the storage sub-block is accessed directly according to the number and the index value; The storage sub-blocks operating in Cache mode and the storage sub-blocks operating in RAM mode can be accessed in parallel.

[0055] Before determining the lookup index format for each storage sub-block, the following is also included: When core requests and external DMA requests access the data storage array simultaneously, all requests are arbitrated to generate an arbitration result. Based on the arbitration results and the working mode of the storage sub-blocks, determine the lookup index format for each storage sub-block.

[0056] When accessing the Tag array, if the Tag of a certain path in the corresponding Set segment matches the high segment of the access address, the cache is hit; otherwise, it is not hit. At the same time, it is checked whether the access address falls within the RAM space under the current configuration value. If it does, the RAM is hit; otherwise, it is not hit. When accessing the data storage array, data in each path is accessed simultaneously based on the index value: for the storage sub-block operating in Cache mode, one path of data is selected based on the Tag hit; for the storage sub-block operating in RAM mode, one path of data is selected based on the address mapping relationship.

[0057] Specifically, kernel-initiated access requests will access both the cache and RAM simultaneously, but only one or both will be hit, or neither will be hit. External DMA access requests can generally only access RAM, but can also support accessing data in the cache using RAM space addressing as needed. Arbitration is required when kernel requests and DMA requests access the memory array simultaneously.

[0058] Arbitration methods include: 1. Always prioritize core access; 2. Core access and DMA are rotated; 3. The core and DMA perform weighted rotation.

[0059] Once an access request is arbitrated, index values ​​for accessing the Tag array and data storage array are generated according to the MMODE configuration, in order to access the Tag array and data storage array.

[0060] Once the cache structure is determined, the distribution of Tags, Sets, and Offsets within the address can be determined. During access, the set field is used as the index, and a set from both the Tag array and the data storage array is accessed simultaneously. A set contains multiple data paths, and the address Tag field is compared with the field read from the Tag array. If they are equal, a cache hit occurs.

[0061] For a Tag array, if a Tag in a certain path within the corresponding Set matches the high segment of the access address, a cache hit occurs; otherwise, a cache miss occurs. At the same time, it checks whether the access address falls within the RAM space under the current configuration. If it does, a RAM hit occurs; otherwise, a cache miss occurs.

[0062] For read operations: When accessing the storage sub-block configured in Cache mode, the data storage array can be accessed simultaneously with the Tag array, or the data storage array can be accessed after the Tag array is accessed. Specifically, when the data storage array and Tag array are accessed simultaneously, since no hit result is obtained, data in each path is accessed simultaneously based on the index value, and the hit path data is selected only after a hit result is obtained. When the data storage array is accessed after the Tag array is accessed, since the hit result is already known, only the hit path array is accessed. When accessing the storage sub-block configured in RAM mode, if a hit occurs, the data storage array can be directly accessed; For write operations: When accessing the storage sub-block configured in Cache mode, the data storage array can only access it after obtaining hit path information; When accessing the storage sub-block configured in RAM mode, if a hit occurs, it can be accessed directly.

[0063] For data storage arrays, data in each path is accessed simultaneously based on the index address.

[0064] If a cache hit occurs, and it's a read request, the requested data is selected from the data read from each data array based on the hit path number. If it's a write request, the write data is written to the corresponding data array based on the hit path number.

[0065] If a RAM hit occurs, the access path number can be obtained directly from the address, and corresponding read and write operations can be performed on the hit path data array.

[0066] This embodiment still takes a memory bank with a total capacity of 32KB, containing 4 logical storage sub-blocks, and configurable as a 2-way set-associative cache structure as an example. The access conditions of each sub-block under different configuration modes are shown in Table 2 below.

[0067] Table 2 Access conditions for each storage sub-block under various configuration modes

[0068] This embodiment takes MMODE as 011b as an example. The organization structure, access control flow, and data flow of the entire storage array are as follows: Figure 2As shown, Seg3 is configured as RAM at this time, and the corresponding Tag array is not working. The index addresses of Seg3, Seg2, Seg1 and Seg0 are ReqAddr[12:6], ReqAddr[11:6], ReqAddr[10:6] and ReqAddr[10:6] respectively. Because the cache is a 2-way set-associative structure, the read data of the cache array is selected by the Tag comparison result, and the read data of the RAM array is directly selected by ReqAddr

[13] . Finally, the final result is selected according to the storage sub-block access conditions.

[0069] Other storage sub-block partitioning methods and cache organization structures can be deduced from the above methods, and will not be elaborated here.

[0070] The diagram illustrates a logical division of the data storage array based on storage sub-blocks and set associativity, with the basic memory access unit being a cache line. In specific designs, the physical organization of each storage block can be further optimized based on performance, area, and power consumption. For example, the smaller value between the core access width and the DMA access width can be used as the basic access granularity, dividing each storage block into multiple banks. During access, only the memory bank corresponding to the specified bank needs to be activated, thus reducing power consumption. Regarding the access order, this invention accesses the Tag array and the data storage array simultaneously. This allows for direct selection of the read data from the data storage array output after obtaining the Tag comparison result, saving latency. Alternatively, the data in the hit path can be accessed precisely after obtaining the Tag comparison result to save energy, but this will increase read latency. Specific implementations can be tailored to specific needs, and similar variations fall within the scope of this invention.

[0071] The storage system of the present invention, which supports dual-mode access of cache and RAM, can dynamically switch configuration modes and adjust the size of cache and RAM during operation to adapt to the needs of different applications.

[0072] The MMODE of this invention can be configured as 011, which is half cache mode and half RAM mode. After running for a period of time, it can be switched to 100, which is full cache mode. Compared with the existing technology where the configuration cannot be changed midway, this invention can change the configuration at any time to change the working mode, making it flexible in use and configuration.

[0073] Because the original storage space mapping changes after switching modes, data already stored in RAM and Cache can no longer be used according to the new access method. Therefore, data consistency operations must be performed before adjusting the configuration mode. This includes writing back dirty data in the Cache and invalidating all cached Cache lines, while simultaneously reading and saving sensitive data stored in RAM. During the consistency operation, the entire storage system will block core access and other DMA accesses (non-consistent DMA). This invention hides the mode switching within the system's own switching time, without consuming additional time, thus improving switching efficiency.

[0074] In this invention, the RAM memory has a defined access space range, but its organization is similar to a directly mapped cache, without a tag array. Given an access address, if it falls within the RAM space, data access can be performed. The index is determined based on the address set segment, and then the specific location of the accessed data is determined based on the offset.

[0075] The cache storage consists of two parts: a tag array and a data storage array, which store address tags and data, respectively. During access, a tag comparison is performed based on the address index. Only when a tag is matched is the data to be accessed in the corresponding cache line. Then, the exact location of the accessed data is determined based on the offset.

[0076] To support dual-mode access to memory (RAM and cache), the data storage array needs to be divided into blocks, and a configuration register MMODE is added to delineate the boundaries between cache and RAM within the memory. Once the MMODE configuration value is determined, the attribute of each data block—whether it's cache or RAM—is determined. Then, based on the RAM space distribution and cache organization structure, the lookup index format for each data block can be determined, including how to generate the data block number and index value within the data block from the access address, and which bits of the address are used as tags for cache space requests.

[0077] For data blocks configured as cache, the tag array and data storage array work simultaneously, and only data blocks with matching numbers will be searched for on each access.

[0078] For data blocks configured as RAM, they can be accessed directly based on the data block number and index value. The corresponding Tag array is inactive, and power or clock can be turned off to save energy.

[0079] The RAM and Cache capacities differ under each MMODE configuration, meaning the number of data blocks contained in the RAM and Cache spaces varies. When the MMODE changes, the sizes of the RAM and Cache spaces can be dynamically switched.

[0080] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An access method for a storage system supporting dual-mode access of Cache and RAM, characterized in that, It is applied to a storage system that supports dual-mode access of cache and RAM. The system includes: The data storage array is divided into multiple structured storage sub-blocks; A storage mode register is used to store configuration values, which are used to dynamically configure each of the storage sub-blocks to work in cache mode or RAM mode, thereby enabling the data storage array to work in full cache mode, full RAM mode, or cache and RAM coexistence mode. Storage access control logic is used to arbitrate storage access requests and map the storage access request to the corresponding storage sub-block for read and write access based on the access address and the configuration value. The storage sub-block mapped by the storage access request is activated, and the storage sub-block not mapped by the storage access request is not activated. The method includes the following steps: According to the configuration value of the storage mode register, the working mode of each storage sub-block is configured, wherein the working mode is Cache mode or RAM mode, thereby enabling the data storage array to work in full Cache mode, full RAM mode, or Cache and RAM coexistence mode, wherein the data storage array is divided into multiple structured storage sub-blocks; Arbitrate storage access requests, and map the storage access request to the corresponding storage sub-block for read and write access based on the access address and the configuration value. The storage sub-block mapped by the storage access request is activated, and the storage sub-block not mapped by the storage access request is not activated. Based on the working mode of the storage sub-block, the lookup index form of each storage sub-block is determined, wherein the lookup index form includes the storage sub-block number generated from the access address and the index value within the storage sub-block, as well as the request tag bit of the cache space, and the index value is used to access the tag array and the data storage array; When the storage sub-block is working in Cache mode, the corresponding Tag array and the data storage array work simultaneously. Each time it is accessed, the storage sub-block with the matching number is searched for index. When the storage sub-block is working in RAM mode, the corresponding data storage array is working, and the Tag array is not working. Each time it is accessed, the storage sub-block is accessed directly according to the number and the index value. The memory sub-blocks operating in Cache mode and the memory sub-blocks operating in RAM mode can be accessed in parallel; When accessing the Tag array, if the Tag of a certain path in the corresponding Set segment matches the high segment of the access address, the cache is hit; otherwise, it is not hit. At the same time, it is checked whether the access address falls within the RAM space under the current configuration value. If it does, the RAM is hit; otherwise, it is not hit. For read operations: When accessing the storage sub-block configured in Cache mode, the data storage array can be accessed simultaneously with the Tag array, or the data storage array can be accessed after the Tag array is accessed. Specifically, when the data storage array and Tag array are accessed simultaneously, since no hit result is obtained, data in each path is accessed simultaneously based on the index value, and the hit path data is selected after a hit result is obtained. When the data storage array is accessed after the Tag array is accessed, since the hit result is already known, only the hit path array is accessed. When accessing the storage sub-block configured in RAM mode, if a hit occurs, the data storage array can be directly accessed; For write operations: When accessing the storage sub-block configured in Cache mode, the data storage array can only access it after obtaining hit path information; When accessing the storage sub-block configured in RAM mode, if a hit occurs, it can be accessed directly.

2. The access method for a storage system supporting dual-mode access of Cache and RAM according to claim 1, characterized in that, The storage capacity of the multiple storage sub-blocks is different.

3. The access method for a storage system supporting dual-mode access of Cache and RAM according to claim 2, characterized in that, The formula for calculating the storage capacity of the storage sub-block is as follows: (Formula 1); in, This is the total storage capacity of the data storage array. is the storage capacity of the i-th storage sub-block, and x is the total number of storage sub-blocks. It is the storage capacity of the x-th storage sub-block, where, x is a positive integer greater than or equal to 1; when hour, This indicates that there is only one such storage sub-block; when hour, and definition This indicates that there are two storage sub-blocks with the same storage capacity. when hour, and definition This indicates that there are 3 storage sub-blocks, and the first 2 storage sub-blocks have the same storage capacity, while the storage capacity of the 3rd storage sub-block is twice that of the 2nd. when When, define , indicating that there are x storage sub-blocks, and the storage capacity of the xth storage sub-block is twice that of the (x-1)th storage sub-block.

4. The access method for a storage system supporting dual-mode access of Cache and RAM according to claim 3, characterized in that, when At that time, it can be known that: ； ； ； And so on, ； but, (Formula 2); According to Formula 2, (Formula 3); According to formulas two and three, when When known, then ; When x and s are known, then That is, the size of the first storage sub-block is .

5. The access method for a storage system supporting dual-mode access of Cache and RAM according to claim 1, characterized in that, The bit width of the configuration value is The bit width is 3, where x is the number of storage sub-blocks. When x is 4, the configuration bit width is 3. When the configuration value is 000b, each of the storage sub-blocks operates in RAM mode, making the data storage array operate in full RAM mode; When the configuration values ​​are 001b, 010b, and 011b, a portion of the storage sub-blocks operate in RAM mode, and the remaining portion of the storage sub-blocks operate in Cache mode, so that the data storage array operates in a Cache and RAM coexistence mode. When the configuration value is 1XXb, X represents 0 or 1, each of the storage sub-blocks operates in cache mode, making the data storage array operate in full cache mode.

6. The access method for a storage system supporting dual-mode access of Cache and RAM according to claim 1, characterized in that, When the data storage array operates in a cache and RAM coexistence mode, access to the cache and RAM is independent of each other; When the configuration values ​​are different: The access address organization of the storage sub-blocks operating in Cache mode is different, and the larger the storage capacity of the storage sub-block, the wider the Set segment used as the index and the shorter the Tag segment used for matching and searching in the corresponding access address. The spatial base address of the storage sub-block operating in RAM mode remains unchanged, and the corresponding end address increases when the configuration value increases.

7. The access method for a storage system supporting dual-mode access of Cache and RAM according to claim 1, characterized in that, Each of the storage sub-blocks is associated with a Tag array, which is used to store address tags and is activated when the storage sub-block is operating in Cache mode to support data matching and lookup. The logical structure of the Tag array is the same as that of the Cache structure.

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