A digital in-memory computing circuit and method based on memristors

Abstract

This invention discloses a digital in-memory computing circuit and method based on memristors, belonging to the field of novel computing technology. The invention utilizes the voltage divider characteristics of memristors and transistors to generate a voltage divider at their connection point. This voltage divider is then converted into a digital signal by an inverter, transforming the in-memory computing process into digital logic operations. The digital in-memory computing unit based on the memristor 2T1R unit is expanded into a cell array, combined with a digital circuit adder, to achieve large-scale matrix-vector multiplication operations. This invention avoids the cumulative calculation based on Kirchhoff's current law in traditional methods, reducing static current loss and improving calculation accuracy and energy efficiency. Parallel array computing improves calculation speed and reduces data transfer costs. This invention enhances the application of memristor in-memory computing technology in the field of digital computing, promoting the development of artificial intelligence chips and high-efficiency computing architectures.

Description

Technical Field

[0001] This invention belongs to the field of novel computing technology, specifically relating to a digital in-memory computing implementation method based on memristor cell structure. Background Technology

[0002] With the development of artificial intelligence, the network size and parameter count of deep neural networks are constantly increasing. Traditional von Neumann architecture computing platforms have reached their bottlenecks, and emerging AI chips are seen as a powerful solution to the problems of low energy efficiency and high latency in computing. In-memory computing architecture is an important direction for the development of AI chips, integrating computing units with memory, greatly reducing data movement during computation, thereby achieving high energy efficiency and high computing power. Among various in-memory computing implementation methods, memristor-based in-memory computing utilizes the non-volatile characteristics of memristor devices, resulting in extremely small area and low power consumption, enabling chips to possess characteristics such as large capacity, high computing power, and high energy efficiency, thus having a very broad application prospect.

[0003] Matrix-vector multiplication is one of the most frequently used computational operations in deep learning algorithms, and improving its computational efficiency has become an important research direction for artificial intelligence chips. Memristor-based in-memory computing technology can efficiently implement matrix-vector multiplication. Traditional methods mainly utilize Ohm's law for multiplication and Kirchhoff's current law for accumulation. The accumulated current is output as a digital signal through an analog-to-digital converter before subsequent operations. This method can perform large-scale matrix-vector multiplication operations in situ on large-capacity arrays, reducing data transfer and achieving in-memory computing integration. However, device fluctuations lead to inaccurate memristor resistance programming, resulting in decreased computational accuracy. Large-scale matrix-vector multiplication operations also generate a large amount of static current within the array, causing a significant increase in power consumption and voltage drop. Currently, there is no accurate and efficient in-memory computing unit structure in the field of memristor-based in-memory computing. Therefore, researching a digital in-memory computing implementation method based on memristor unit structures to improve the computational accuracy, computing power, and energy efficiency of large-scale memristor in-memory computing is of great significance. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a digital in-memory computing circuit and method based on memristors. The circuit is based on a digital in-memory computing unit using a 2T1R memristor cell. Utilizing the principle of resistor voltage division, the memristor and transistor in the 2T1R memristor cell are connected in series, causing a voltage divider value to be generated at the connection point. Combined with an inverter, the voltage divider value is converted into a digital signal, transforming the in-memory computing process into digital logic operations. The digital in-memory computing unit based on the 2T1R memristor cell is expanded into a cell array, combined with a digital circuit adder, to realize matrix-vector multiplication operations.

[0005] The technical solution of the present invention is as follows:

[0006] A digital in-memory computing circuit based on memristors, characterized in that it includes an array of digital in-memory computing units composed of memristor 2T1R units and a digital circuit adder.

[0007] The digital in-memory computing unit based on the memristor 2T1R unit includes a memristor 2T1R unit and an inverter;

[0008] The memristor 2T1R unit includes two transistors and one memristor. One transistor and the memristor are connected in series to form a main voltage divider circuit. The drain of the main voltage divider transistor is connected to the bottom electrode of the memristor, the source is connected to the source line SL, and the gate is connected to the word line WL. The top electrode of the memristor is connected to the bit line BL. The voltage divider value is output at the intermediate node of the main voltage divider transistor and the memristor connected in series. The drain of the other transistor is also connected to the bottom electrode of the memristor, the source is the read terminal of the memristor 2T1R unit connected to the calculation line CL, and the gate is connected to the select line SELECT. The other end of the calculation line CL is connected to the input terminal of the inverter. This transistor and the inverter are connected in series to form a readout branch. This readout branch converts the voltage divider value output by the main voltage divider circuit into a digital signal and outputs it from the output terminal of the inverter.

[0009] n×m digital memory computing units based on memristor 2T1R cells are arranged into an array of n rows and m columns. In each row, the word lines WL of each cell are connected. In each column, the bit lines BL and source lines SL of each cell are connected. The select lines SELECT of all cells in the array are connected. The inverter outputs of all cells are connected to the same digital circuit adder. The digital circuit adder sums the digital signals output by each cell in each column to obtain the final matrix-vector multiplication result.

[0010] The digital circuit adder is a traditional multi-bit digital adder.

[0011] Furthermore, the two transistors in the memristor 2T1R unit are NMOS transistors.

[0012] This invention also provides a digital in-memory computation method implemented on the aforementioned memristor-based digital in-memory computation circuit. This method utilizes the circuit to perform a multiplication calculation between an n×m dimensional weight matrix and an n-dimensional input vector, specifically including the following steps:

[0013] (1) Encode each weight value bit of the n×m dimension weight matrix into a conductance value and store it in the memristor device of each main voltage divider circuit in the n row m column array circuit, corresponding to the high resistance state HRS or the low resistance state LRS.

[0014] (2) The n-dimensional single-bit input vector is mapped to the input voltage on the n word lines WL in the n-row m-column array circuit, and the voltage of the word line WL is 0 or the read voltage Von.

[0015] (3) Connect all m columns BL to the power supply voltage VDD and SL to ground. At this time, depending on the different conductances of the memristor devices, the on-resistances of the transistors in the main voltage divider circuit are different. The voltage division of the transistors and memristors in the main voltage divider circuit will result in different voltages at the intermediate nodes.

[0016] (4) Apply voltage to the common selected line SELECT and pull it high. At this time, the intermediate node is connected to the input terminal of the inverter of the read branch. The output of the inverter represents the product of the single-bit input of the unit and the single-bit weight stored in the memristor device of the unit. Read out the n×m products of the n single-bit input elements in the n-dimensional input vector and the n×m single-bit weight elements in the n×m-dimensional weight matrix from the inverters of the n×m read branches.

[0017] (5) Read out the product result and send it to the digital circuit adder. The multi-bit product result is multiplied and added in the digital domain. The output of each column is summed by the digital circuit adder to obtain the final matrix-vector multiplication result.

[0018] Furthermore, in step (1), the high-resistivity state HRS and the low-resistivity state LRS of the memristor correspond to logic weights 1 and 0, respectively.

[0019] Furthermore, in step (2), the input voltage on the word line WL, the input voltage Von or 0, respectively correspond to logic input 1 and 0.

[0020] Furthermore, in step (4), the voltage applied to the selected line SELECT is the power supply voltage VDD.

[0021] The technical effects of this invention are as follows:

[0022] This invention discloses a digital in-memory computing circuit and method based on memristors. The circuit utilizes a digital in-memory computing unit based on a 2T1R memristor cell. By leveraging the voltage divider characteristics of the memristor and transistor in the 2T1R structure, the in-memory computing process is converted into digital logic operations, avoiding the cumulative calculations based on Kirchhoff's current law in traditional methods. This reduces static current loss and improves calculation accuracy and energy efficiency. The computing unit of this invention uses the high and low impedance states of the memristor to represent logic weights 1 and 0, respectively. The input signal is applied with voltage through the word line WL, and combined with the inverter circuit in the readout branch, the calculation result is directly converted into a digital signal. The digital in-memory computing unit based on the 2T1R memristor cell of this invention is expanded into a cell array, combined with a digital circuit adder, to achieve large-scale matrix-vector multiplication operations. Parallel array computing improves calculation speed and reduces data transfer costs. Attached Figure Description

[0023] Figure 1 This is a structural diagram of the memristor 2T1R unit on which the present invention is based;

[0024] Figure 2 This is a schematic diagram of the working principle of the digital in-memory computing unit based on the memristor 2T1R unit of the present invention;

[0025] Figure 3 This is a schematic diagram of the working principle of the main voltage divider circuit in the digital in-memory computing unit based on the memristor 2T1R unit of the present invention, including four cases;

[0026] Figure 4 This is a schematic diagram of the readout branch in the digital in-memory computing unit based on the memristor 2T1R unit of the present invention, which converts analog voltage into digital signal.

[0027] Figure 5 This is a diagram showing the four input-output relationships of the digital in-memory computing unit based on the memristor 2T1R unit of the present invention;

[0028] Figure 6 This is a schematic diagram of the matrix-vector multiplication of a [3×3] weight matrix and a [3×1] input vector by an array circuit composed of digital in-memory computing units based on memristor 2T1R units, wherein (a) implements the product part of the matrix-vector multiplication, and (b) implements the accumulation part of the matrix-vector multiplication.

[0029] Figure 7 This is a schematic diagram illustrating the matrix-vector multiplication of an n×m weight matrix and an nx1 input vector by an array circuit composed of digital in-memory computing units based on the memristor 2T1R unit of the present invention. Detailed Implementation

[0030] The present invention will be further clearly and completely described below with reference to the accompanying drawings and specific embodiments.

[0031] This invention discloses a memristor-based digital in-memory computing circuit, comprising an array of digital in-memory computing units based on memristor 2T1R cells and a digital circuit adder. Each memristor 2T1R cell includes one memristor 2T1R cell and an inverter. The memristor 2T1R cell includes two transistors and one memristor. One transistor and the memristor are connected in series to form a main voltage divider circuit. The drain of the main voltage divider transistor is connected to the bottom electrode of the memristor, the source is connected to the source line (SL), and the gate is connected to the word line (WL). The top electrode of the memristor is connected to the bit line (BL). A voltage divider value is output at the intermediate node of the series connection between the main voltage divider transistor and the memristor. Similarly, the drain of the other transistor is connected to the bottom electrode of the memristor, the source is the read terminal of the memristor 2T1R cell connected to the calculation line (CL), and the gate is connected to the select line (SE). The transistor (LECT) is connected to the input of an inverter at the other end of the compute line (CL). The transistor and the inverter are connected in series to form a readout branch. This readout branch converts the voltage division value output by the main voltage divider circuit into a digital signal and outputs it from the output of the inverter. n×m digital in-memory compute units based on memristor 2T1R units are arranged into an array of n rows and m columns. In each row, the word lines WL of each digital in-memory compute unit based on memristor 2T1R units are connected, the source lines SL of each unit are connected, and the select lines SELECT of all units in the array are connected. The inverter outputs of all units are connected to the same digital circuit adder. The digital circuit adder sums the digital signals output by each digital in-memory compute unit based on memristor 2T1R units in each column to obtain the final matrix-vector multiplication result. The digital circuit adder is a traditional multi-bit digital adder.

[0032] This invention utilizes the principle of resistor voltage division to generate a voltage divider value at the connection between the memristor and the transistor. This voltage divider value is then converted into a digital signal through the readout branch, and the result of matrix-vector multiplication is obtained by summing the values ​​using a digital circuit adder.

[0033] The structure of the memristor 2T1R unit is as follows: Figure 1 As shown, the 2T1R cell consists of two NMOS transistors (2T) and one memristor (1R). One NMOS transistor is connected in series with the memristor (denoted as T1). The top electrode of the memristor is connected to the bit line BL, and the bottom electrode is connected to the drain of T1. The source of T1 is connected to the source line SL, and the gate is connected to the word line WL. The drain of the other NMOS transistor (denoted as T2) is also connected to the bottom electrode of the memristor, the source is connected to the read operation line CL, and the gate is connected to the select line SELECT.

[0034] A digital in-memory computing unit composed of a memristor 2T1R cell and an inverter can be used to perform multiplication operations in neural network calculations. When performing calculations using this digital in-memory computing unit, such as... Figure 2As shown, the memristor will be in a high-resistance or low-resistance state (HRS / LRS). BL is connected to the power supply voltage (VDD), SL is connected to the power supply ground (GND), and WL is the input voltage Von or 0, where Von is between 0 and VDD, making transistor T1 in a "semi-conducting" state. At this time, the main circuit forms a series voltage divider circuit, and the intermediate node can receive different voltages Vx. In the readout branch where T2 is located, the SELECT terminal is connected to VDD, that is, T2 is turned on, and an inverter is connected to the CL terminal. This branch can read the Vx voltage and convert the calculation result into a digital signal value of 0 or 1 according to the high or low value of Vx.

[0035] The detailed principle of the main voltage divider circuit, which consists of a transistor and a memristor connected in series, is as follows: Figure 3 As shown, Figure 3 (1) When the memristor is in a high resistance state and Von voltage is applied to WL, the resistance R of the memristor is greater than the resistance RT of the transistor T1, so the Vx voltage is lower at this time. Figure 3 (2) When the memristor is in a low resistance state, and Von voltage is applied to WL, since the resistance R of the memristor is less than the resistance RT of the transistor T1, Vx receives a higher voltage. Figure 3 (3)(4) When 0 voltage is applied to WL, T1 can be regarded as an open circuit, that is, the resistance RT of T1 transistor is much greater than R. At this time, regardless of whether the memristor is in a high resistance state or a low resistance state, Vx is evenly distributed to a higher voltage.

[0036] The principle of the readout branch consisting of a transistor and an inverter connected in series is as follows: Figure 4 As shown, when Vx receives a higher voltage (greater than 0.5 times VDD), it reaches the input terminal Vcl of the inverter after passing through the fully conducting transistor T2. At this time, the Vcl voltage value is greater than half of the inverter's operating voltage VDD, so it becomes a digital 0 output after the inverter. When Vx receives a lower voltage (less than 0.5 times VDD), the Vcl voltage value is less than half of the inverter's operating voltage VDD, so it becomes a digital 1 output after the inverter. In this way, the Vx voltage is converted into a 0 / 1 digital signal output, completing the conversion from analog to digital signal. When the resistance of the memristor device fluctuates, the voltage at point Vx also fluctuates with the resistance. However, as long as the fluctuation of Vx affects Vcl by no more than 0.5VDD, the output will not change. Therefore, the readout branch can suppress the calculation error caused by the fluctuation of the device resistance.

[0037] The output relationship of the digital in-memory computing unit, which combines the main circuit and the readout branch, under different inputs and different resistance states is as follows: Figure 5 As shown, the truth table can be summarized as follows:

[0038] Table 1 Input / Output Truth Table

[0039]

[0040] As can be seen from Table 1, if the high impedance state of the memristor corresponds to a logic weight value of 1 and the low impedance state corresponds to a logic weight value of 0; and if the input voltage applied to WL is Von, it is recorded as logic input 1 and 0, it is recorded as logic input 0, then the logic function of this digital in-memory computing unit can be regarded as completing the multiplication between the weight and the input (Output = Input × Weight). That is, the output value is 1 only when both the logic weight value and the logic input value are 1, otherwise the output is 0.

[0041] Since the output product is a digital value, the addition part of the multiplication-addition operation can be implemented by a digital circuit adder.

[0042] Taking matrix-vector multiplication, the most common operation in neural networks, as an example, this invention demonstrates how a memristor-based digital in-memory computation method is implemented on the aforementioned memristor-based digital in-memory computation circuit.

[0043] Matrix-vector multiplication, taking the multiplication of a [3×3] weight matrix W with a [3×1] input vector IN to obtain a [3×1] output vector Result as an example, the specific calculation formula is as follows:

[0044]

[0045] Multiplying the input vector with the weight matrix can be divided into two steps: the first step is to multiply the elements of the vector with the elements of the matrix to obtain the product, and the second step is to add the products according to the rules to obtain the elements of the output vector.

[0046] like Figure 6 As shown in (a), an example is given of multiplying a [3×3] weight matrix W with a [3×1] input vector IN to obtain its product. The input vector IN is multiplied by the weight matrix W, which is stored in the resistance value R of the 2T1R unit: if the weight is 1, the R in the unit is in a high resistance state; if the weight is 0, the R in the unit is in a low resistance state. The input vector is the voltage input to the 2T1R unit WL: if the input is 1, a Von voltage is applied to WL; if the input is 0, a 0 voltage is applied to WL (consistent with the correspondence between logical variables and actual physical variables in Table 1).

[0047] Connect the three columns BL to VDD, SL to ground, and connect the SELECT signal to VDD. Then, as follows: Figure 6 As shown, the OUT output from the readout branch inverter is the product of the input element and the weight element.

[0048] Then perform the multiplication-accumulation-addition operation, such as... Figure 6As shown in (b), the output of each column is summed by the same digital circuit adder (Adder) to obtain the final matrix-vector multiplication result (Result). Thus, matrix-vector multiplication is completed using the array composed of these 2T1R units.

[0049] Multiplication of matrices and vectors of different sizes is also based on this principle, such as... Figure 7 As shown, Figure 7 This is a schematic diagram illustrating how the present invention uses an array circuit composed of digital in-memory computing units based on memristor 2T1R units to perform matrix-vector multiplication of an n×m weight matrix with an nx1 input vector.

[0050] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A digital in-memory computing circuit based on memristors, characterized in that, This includes an array of digital in-memory computing units based on memristor 2T1R cells and a digital circuit adder; The digital in-memory computing unit based on the memristor 2T1R unit includes a memristor 2T1R unit and an inverter; The memristor 2T1R unit includes two transistors and one memristor. One transistor and the memristor are connected in series to form a main voltage divider circuit. The drain of the main voltage divider transistor is connected to the bottom electrode of the memristor, the source is connected to the source line SL, and the gate is connected to the word line WL. The top electrode of the memristor is connected to the bit line BL. The voltage divider value is output at the intermediate node of the main voltage divider transistor and the memristor connected in series. The drain of the other transistor is also connected to the bottom electrode of the memristor, the source is the read terminal of the memristor 2T1R unit connected to the calculation line CL, and the gate is connected to the select line SELECT. The other end of the calculation line CL is connected to the input terminal of the inverter. This transistor and the inverter are connected in series to form a readout branch. This readout branch converts the voltage divider value output by the main voltage divider circuit into a digital signal and outputs it from the output terminal of the inverter. n×m digital memory computing units based on memristor 2T1R cells are arranged into an array of n rows and m columns. In each row, the word lines WL of each cell are connected. In each column, the bit lines BL and source lines SL of each cell are connected. The select lines SELECT of all cells in the array are connected. The inverter outputs of all cells are connected to the same digital circuit adder. The digital circuit adder sums the digital signals output by each cell in each column to obtain the final matrix-vector multiplication result. The digital circuit adder is a traditional multi-bit digital adder.

2. The digital in-memory computing circuit based on memristors as described in claim 1, characterized in that, The two transistors in the memristor 2T1R unit are NMOS transistors.

3. A digital in-memory computing method implemented on the memristor-based digital in-memory computing circuit as described in claim 1 or 2, characterized in that, The specific steps are as follows: (1) Encode each weight value bit of the n×m dimensional weight matrix into a conductance value and store it in the n-row m-column array circuit. In each main voltage divider circuit, the memristor device corresponds to the high-resistivity state HRS or the low-resistivity state LRS of the memristor. (2) Map the n-dimensional single-bit input vector to the n word lines WL in the n-row m-column array circuit. Input voltage, word line WL voltage is 0 or read voltage Von; (3) Connect all m columns BL to the power supply voltage VDD and SL to ground. At this time, depending on the different conductivities of the memristor devices, the main... The different on-resistances of the transistors in the voltage divider circuit will result in different voltages at the intermediate nodes due to the voltage division between the transistors and the memristor in the main voltage divider circuit. (4) Apply voltage to the shared selected line SELECT and pull it high. At this time, the intermediate node is connected to the input terminal of the inverter of the readout branch. The inverter output represents the product of a single-bit input to the cell and a single-bit weight stored in the memristor device of the cell; the n×m products of the n single-bit input elements in the n-dimensional input vector and the n×m single-bit weight elements in the n×m-dimensional weight matrix are read out from the inverters of the n×m readout branches. (5) The product result is read out and sent to the digital circuit adder. The multi-bit product result is multiplied and added in the digital domain. Operation: The output of each column is summed by a digital circuit adder to obtain the final matrix-vector multiplication result.

4. The digital in-memory computation method as described in claim 3, characterized in that, In step (1), the high-resistivity state HRS and the low-resistivity state LRS of the memristor correspond to logic weights 1 and 0, respectively.

5. The digital in-memory computation method as described in claim 3, characterized in that, In step (2), the input voltage on word line WL, the input voltage Von or 0, correspond to logic input 1 and 0 respectively.

6. The digital in-memory computation method as described in claim 3, characterized in that, In step (4), the voltage applied to the selected line SELECT is the power supply voltage VDD.

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