Metal density and via density drc rule detection method, system and terminal

Abstract

The application provides a metal density and via density DRC rule detection method, system and terminal, wherein local metal density and via density thresholds of different stress regions of metal layers and dielectric material layers inside a chip are defined, different density detection window regions of adjacent metal layers directly below BUMP PAD UBM inside the flip chip are defined, and newly added DRC design rules are set; the DRC design rules are run, density detection results of the different density detection window regions below each BUMP UBM region inside the chip are detected, and density violation positions on the chip are determined, so as to perform optimization design before chip Tapeout manufacturing. In the chip design process, the application timely discovers design defects that may cause chip quality problems in the subsequent PCB SMT process in the packaging manufacturing through the supplementary metal density and via rule detection, and improves the local density and the mechanical strength of the chip against external thermal stress through metal and via filling and other design optimization, solves potential product quality problems caused by materials and thermal stress, reduces manufacturing cost, thereby improves product yield and reliability, and realizes that the chip can be mass-produced earlier to put the product into the market in the first time.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a method, system and terminal for detecting metal density and via density DRC rules. Background Technology

[0002] Currently, wafer foundries responsible for chip manufacturing provide chip design companies with Design Rule Manuals (DRMs) and Process Design Kits (PDKs) based on wafer manufacturing process nodes and process requirements (such as etching speed, chemical mechanical polishing planarization, etc.).

[0003] The physical verification reference flow in a PDK typically uses a rule checking language (such as StandardVerification Rule Format-SVRF, Tcl Verification Format-TVF) to define the rule parameters for metal density or via density at each layer, forming a design rule runset. Chip design companies use physical verification tools like Mentor Calibre and the PDK DRC Runset to perform design rule checks (DRC) on the designed chip layout GDSII file to determine whether the metal density and via density meet the requirements of the wafer fab's manufacturing process.

[0004] Existing DRC (Density Reduction) rules for metal density and via density based on process requirements cannot cover chip failures and reliability issues caused by thermal stress during subsequent packaging manufacturing processes and chip soldering (Reflow SMT) on the PCB. Even if the metal density and via density DRC rules required by the chip manufacturing process are met, local delamination or cracking of the inter-metal-dielectric (IMD) material within the chip may still occur during the subsequent chip package bump manufacturing and solder ball PCB SMT reflow soldering process, causing some chip functions to malfunction and even chip failure. Due to the temperature rise (1-4 minutes, from 25°C to 250°C) and drop (2°C / s) during reflow soldering, the difference in thermal expansion coefficients between the chip and package materials causes thermal stress within the silicon and substrate materials, leading to deformation and warping of the package and PCB, which in turn results in local delamination or cracking of the inter-metal-dielectric (IMD) material within the chip. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method, system and terminal for detecting metal density and via density DRC rules, which can solve the technical problems that existing methods for detecting metal density and via density DRC rules cannot cover chip failure and reliability issues caused by thermal stress during subsequent packaging and PCB board soldering. Even if the existing rules are met, thermal stress caused by the difference in thermal expansion coefficients between the chip and the packaging material during reflow soldering can still cause local delamination or fracture of the interlayer material in the chip, thus affecting the function or even causing failure.

[0006] To achieve the above and other related objectives, this invention provides a method for detecting metal density and via density DRC rules, comprising: defining local metal density and via density thresholds in different stress regions on a chip; defining different density detection window regions below each BUMP UBM region inside the chip, and setting newly added DRC design rules based on the local metal density and via density thresholds of each stress region; running the DRC design rules to detect the density detection results in different density detection window regions below each BUMP UBM region inside the chip, and determining the density violation locations on the chip for optimization design before chip fabrication.

[0007] In one embodiment of the present invention, defining the local metal density and via density thresholds for different stress regions on the chip includes: dividing the chip into a first stress region, a second stress region, and a third stress region corresponding to different stresses; wherein the stress in the first stress region is greater than that in the second stress region, and the stress in the second stress region is greater than that in the third stress region; setting local metal density thresholds and via density thresholds for the first stress region, the second stress region, and the third stress region; wherein the values ​​of the local metal density threshold and the via density threshold for each of the first stress region, the second stress region, and the third stress region are equal; the values ​​of the local metal density threshold and the via density threshold for the first stress region are greater than those for the second stress region, and the values ​​of the local metal density threshold and the via density threshold for the second stress region are greater than those for the third stress region.

[0008] In one embodiment of the present invention, defining different density detection window regions below each BUMP UBM region inside the chip, and setting newly added DRC design rules based on the local metal density and via density thresholds of each stress region includes: dividing the area below each BUMP UBM region inside the chip into multiple density detection window regions; determining the local metal density threshold and via density threshold below each BUMP UBM region based on the local metal density and via density thresholds of each stress region, and setting newly added DRC design rules.

[0009] In one embodiment of the present invention, dividing the area below each BUMP UBM region inside the chip into multiple density detection window regions includes: dividing the area below each BUMP UBM region inside the chip into 11 density detection window regions according to different dimensions based on density detection window region division rules.

[0010] In one embodiment of the present invention, the density detection window region division rule includes: dividing the rectangular region enclosed below the BUMP UBM region into three equally sized and sequentially adjacent density detection window regions in the horizontal direction; dividing the rectangular region enclosed below the BUMP UBM region into three equally sized and sequentially adjacent density detection window regions in the vertical direction; using the center point of the BUMP UBM region as a reference, dividing the rectangular region enclosed below the BUMP UBM region into four centrally symmetrically distributed density detection window regions; and using the entire rectangular region enclosed below the BUMP UBM region as one density detection window region.

[0011] In one embodiment of the present invention, the step of determining the local metal density threshold and via density threshold below each BUMP UBM region based on the local metal density and via density threshold of each stress region, and setting the newly added DRC design rule includes: determining the stress region where each BUMP UBM region is located, and using the local metal density threshold and via density threshold of the corresponding stress region as the local metal density threshold and via density threshold below the corresponding BUMP UBM region; setting the newly added DRC design rule for detecting whether each BUMP UBM region is a density violation location based on the local metal density threshold and via density threshold below each BUMP UBM region.

[0012] In one embodiment of the present invention, the metal density and via density of different density detection window areas below each BUMP UBM region inside the detection chip are detected, and the density violation location is determined based on the density detection results of each density detection window area below each BUMP UBM region. This includes: detecting the local metal density and via density of different density detection window areas below each BUMP UBM region inside the detection chip to obtain the density detection results of each density detection window area below each BUMP UBM region; taking the minimum value of the local metal density and via density in the density detection results of each density detection window area below each BUMP UBM region as the density detection result corresponding to each BUMP UBM region; comparing the local metal density and via density corresponding to each BUMP UBM region with the corresponding local metal density threshold and via density threshold below the BUMP UBM region to determine the non-compliant BUMP UBM region, and taking the location of the BUMP UBM region as the density violation location, and issuing the corresponding DRC alarm information.

[0013] In one embodiment of the present invention, the density detection results corresponding to each BUMP UBM region are identified by different colors.

[0014] To achieve the above and other related objectives, this invention provides a metal density and via density DRC rule detection system, comprising: a stress region definition module for defining local metal density and via density thresholds in different stress regions on a chip; a density detection window definition module connected to the stress region definition module for defining different density detection window regions below each BUMP UBM region inside the chip, and setting newly added DRC design rules based on the local metal density and via density thresholds of each stress region; and a density detection module connected to the density detection window definition module for running the DRC design rules, detecting the density detection results of different density detection window regions below each BUMP UBM region inside the chip, and determining the density violation locations on the chip for optimization design before chip fabrication.

[0015] To achieve the above and other related objectives, the present invention provides an electronic terminal, comprising: one or more memories and one or more processors; the one or more memories being used to store a computer program; and the one or more processors being connected to the memories and used to run the computer program to perform the method described.

[0016] As described above, this invention provides a method, system, and terminal for detecting metal density and via density DRC rules, offering the following advantages: This invention defines local metal density and via density thresholds for different stress regions on the chip, as well as different density detection window regions below each BUMP UBM region within the chip. It also sets newly added DRC design rules, runs these rules, detects the density detection results of different density detection window regions below each BUMP UBM region within the chip, and identifies density violation locations on the chip for optimization design before chip tapeout manufacturing. During chip design, this invention, through supplementary metal density and via rule detection, promptly identifies design defects that may lead to chip quality problems during subsequent packaging and PCB SMT processes. By optimizing design such as metal and via filling, it improves local density, ultimately resolving product quality issues caused by material and thermal stress. This improves product yield, reduces manufacturing costs, ensures chips meet mass production requirements, and enhances the competitiveness of enterprise products. Attached Figure Description

[0017] Figure 1 The diagram shown is a structural schematic of the DRC rule detection method for metal density and via density according to an embodiment of the present invention.

[0018] Figure 2 The diagram shown is a schematic representation of the stress region definition in one embodiment of the present invention.

[0019] Figure 3 The diagram shown is a schematic representation of the density detection window region division in one embodiment of the present invention.

[0020] Figure 4 The diagram shown is a schematic representation of the density detection window region division in one embodiment of the present invention.

[0021] Figure 5 The diagram shown is a schematic representation of the full chip density violation location marking in one embodiment of the present invention.

[0022] Figure 6 The diagram shown is a structural schematic of a metal density and via density DRC rule detection system according to an embodiment of the present invention.

[0023] Figure 7 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of the present invention. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0025] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of the invention. The following detailed description should not be considered limiting, and the scope of the embodiments of the invention is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0026] Throughout this specification, when it is said that a part is "connected" to another part, this includes not only "direct connection" but also "indirect connection" by placing other elements in between. Furthermore, when it is said that a part "includes" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather means that other constituent elements may also be included.

[0027] The terms "first," "second," and "third," etc., used herein are for the purpose of describing various parts, components, regions, layers, and / or segments, but are not limiting. These terms are used only to distinguish one part, component, region, layer, or segment from others. Therefore, the "first part," "component," "region," "layer," or "segment" described below may refer to a "second part," "component," "region," "layer," or "segment" without departing from the scope of this invention.

[0028] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0029] This invention provides a method for detecting metal density and via density DRC rules. It defines local metal density and via density thresholds for different stress regions on the chip, as well as different density detection window regions below each BUMP UBM region within the chip. A newly added DRC design rule is set, and by running this rule, the density detection results of different density detection window regions below each BUMP UBM region within the chip are detected, and the locations of density violations on the chip are determined for optimization design before chip tapeout manufacturing. In the chip design process, this invention, through supplementary metal density and via rule detection, can promptly identify design defects that may lead to chip quality problems in subsequent packaging and PCB SMT processes. Through design optimizations such as metal and via filling, local density is improved, ultimately resolving product quality issues caused by material and thermal stress. This improves product yield, reduces manufacturing costs, ensures chips meet mass production requirements, and enhances the competitiveness of enterprise products.

[0030] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0031] like Figure 1 This diagram illustrates the structure of a method for detecting metal density and via density DRC rules in an embodiment of the present invention.

[0032] The method includes:

[0033] Step S1: Define the local metal density and via density thresholds for different stress regions on the chip.

[0034] In one embodiment, the threshold values ​​for local metal density and via density in different stress regions on the chip include:

[0035] Based on the distribution of stress levels, the chip is divided into a first stress region, a second stress region, and a third stress region, each corresponding to different stress levels. The stress in the first stress region is greater than that in the second stress region, and the stress in the second stress region is greater than that in the third stress region. High-stress regions (such as the chip edge) correspond to the first stress region, low-stress regions (such as the signal processing core area) correspond to the third stress region, and other regions correspond to the second stress region.

[0036] Set local metal density thresholds and via density thresholds for the first stress region, the second stress region, and the third stress region; wherein the values ​​of the local metal density thresholds and via density thresholds for the first stress region, the second stress region, and the third stress region are equal; the values ​​of the local metal density thresholds and via density thresholds for the first stress region are greater than the values ​​of the local metal density thresholds and via density thresholds for the second stress region, and the values ​​of the local metal density thresholds and via density thresholds for the second stress region are greater than the values ​​of the local metal density thresholds and via density thresholds for the third stress region.

[0037] In one specific embodiment, such as Figure 2 According to industry standards and thermal stress deformation mechanism, the chip package warps due to thermal stress deformation, and three stress regions are divided on the chip: LR1, LR2 and LR3, and their stress distribution satisfies: LR1>LR2>LR3.

[0038] LR1 region (maximum stress): Both the local metal density threshold (MDN_LR1) and the via density threshold (VDN_LR1) must be greater than 0.15, i.e., MDN_LR1>0.15, VDN_LR1>0.15;

[0039] LR2 region (medium stress): Both the local metal density threshold (MDN_LR2) and the via density threshold (VDN_LR2) must be greater than 0.1, i.e., MDN_LR2>0.1, VDN_LR2>0.1;

[0040] LR3 region (minimum stress): The local metal density threshold (MDN_LR3) and the via density threshold (VDN_LR3) must both be greater than 0.05, i.e., MDN_LR3>0.05, VDN_LR3>0.05.

[0041] Step S2: Define different density detection window regions below each BUMP UBM region inside the chip, and set new DRC design rules based on the local metal density and via density thresholds of each stress region.

[0042] In one embodiment, step S2 includes:

[0043] The area beneath each BUMP UBM region within the chip is divided into multiple density detection window regions. Specifically, the BUMP / UBM region is the vertical projection area directly beneath each BUMP (bump) and UBM (under-bump metal layer) region within the chip. These areas are critical interfaces connecting the chip and the packaging substrate and are susceptible to thermal-mechanical stress concentration. Multiple rectangular detection windows are then divided beneath each BUMP / UBM region.

[0044] Based on the local metal density and via density thresholds of each stress region, the local metal density thresholds and via density thresholds below each BUMP UBM region are determined, and new DRC design rules are set.

[0045] In one embodiment, dividing the area below each BUMP UBM region inside the chip into multiple density detection window regions includes: dividing the area below each BUMP UBM region inside the chip into 11 density detection window regions according to different dimensions based on density detection window region division rules.

[0046] In one specific embodiment, the density detection window division rule achieves fine coverage of the stress-sensitive area below the BUMP UBM region through multi-dimensional segmentation and symmetrical layout. The density detection window region division rule includes:

[0047] The geometric dimensions (length Lx, width Ly) of the rectangular area below the BUMP UBM and the location of the coordinate origin (usually the center of the UBM) need to be clearly defined.

[0048] Due to differences in thermal expansion coefficients, the edges of UBMs are prone to lateral tensile stress. Therefore, it is necessary to densely divide the area into windows along the X-axis to capture local density changes. The rectangular area is divided into three window areas in the horizontal direction. The three windows are exactly the same size and are adjacent to each other in the horizontal direction (distributed continuously from left to right or from right to left).

[0049] The connection between the UBM and the convex point is prone to electromigration due to the concentrated current density, so a longitudinal window is needed to cover the critical height section. The rectangular area is divided into three window areas along the longitudinal (vertical) direction: the three windows are exactly the same size and are adjacent to each other in the longitudinal direction (distributed continuously from top to bottom or from bottom to top).

[0050] To address potential asymmetric stress distribution within the BUMP UBM region (such as eccentric stress caused by differences in thermal expansion coefficients), a centrally symmetrical window ensures that critical areas (such as convex edge areas and UBM layer overlaps) are independently monitored. Using the geometric center of the BUMP UBM region as the origin, the rectangular area is divided into four rectangular sub-windows. These four windows are centrally symmetrically distributed (e.g., a cross-shaped division forming four symmetrical regions: upper left, upper right, lower left, and lower right), and all are identical in size.

[0051] The entire rectangular region enclosed below the BUMP UBM region is directly used as a single density detection window region without segmentation.

[0052] For example, taking a UBM size of 48μm × 63μm as an example, Figure 3 The region is divided into three equal-width regions (each 16 μm wide and 63 μm high) along the horizontal direction (48 μm direction), and is defined as follows:

[0053] Window A: Left 1 / 3 region (horizontal 0–16μm, vertical 0–63μm)

[0054] Window B: Middle 1 / 3 region (16–32 μm horizontally, 0–63 μm vertically)

[0055] C window: Right 1 / 3 region (32–48 μm horizontally, 0–63 μm vertically)

[0056] The area was divided into three equal-height regions (each 21 μm high and 48 μm wide) along the longitudinal direction (63 μm direction), and defined as follows:

[0057] D window: Upper 1 / 3 region (horizontal 0–48μm, vertical 0–21μm)

[0058] E-window: Middle 1 / 3 region (0–48 μm horizontally, 21–43 μm vertically)

[0059] F window: Lower 1 / 3 region (0–48 μm horizontally, 43–63 μm vertically)

[0060] like Figure 4 Using the center point of UBM (24μm horizontally and 31.5μm vertically) as a reference, the area is divided into four symmetrical regions (each region 24μm × 31.5μm) along the horizontal and vertical centerlines:

[0061] G window: Top left region (horizontal 0–24 μm, vertical 0–31.5 μm)

[0062] H window: Upper right region (horizontal 24–48 μm, vertical 0–31.5 μm)

[0063] I-window: Lower left region (0–24 μm horizontally, 31.5–63 μm vertically)

[0064] J window: Lower right region (24–48 μm horizontally, 31.5–63 μm vertically)

[0065] K window: The rectangular area below the entire UBM (48μm×63μm, i.e., 0~48μm horizontally and 0~63μm vertically).

[0066] The above 11 detection windows cover horizontal subdivision, vertical subdivision, central symmetric subdivision, and overall area, enabling refined detection of metal density in different local areas below the UBM.

[0067] In one embodiment, each stress region (e.g., LR1, LR2, LR3) contains multiple BUMP UBM regions; that is, each BUMP UBM region belongs to only one stress region, and there is no cross-region situation. The process of determining the local metal density threshold and via density threshold below each BUMP UBM region based on the local metal density and via density threshold of each stress region, and setting the newly added DRC design rules, includes:

[0068] For each BUMP UBM region, identify its stress region. Use the local metal density threshold (MDN) and via density threshold (VDN) of the stress region to which the BUMP UBM region belongs as the density threshold below that UBM region.

[0069] A new DRC design rule is established based on the local metal density threshold and via density threshold below each BUMP UBM region to detect whether each BUMP UBM region is a density violation location. The stress region to which each BUMP UBM region belongs is clearly defined in the design rule file. Corresponding metal density thresholds and via density thresholds are set according to the stress region to which each BUMP UBM region belongs; these thresholds will serve as the detection benchmark. The DRC rule is implemented using EDA tools, and the detection logic is configured to detect the metal density and via density of 11 detection windows below each BUMP UBM region. Violation conditions are set; if the metal density or via density of the corresponding detection window of a BUMP UBM region is lower than its corresponding threshold, the BUMP UBM region is marked as a violation.

[0070] Step S3: Run the DRC design rule to detect the density detection results of different density detection window areas under each BUMP UBM area inside the chip, and determine the density violation locations on the chip for optimization design before chip tape-out manufacturing.

[0071] In one embodiment, by running DRC design rules, the density data of each detection window below all BUMP UBM regions in the chip is detected, and non-compliant locations with substandard density are identified, providing a precise basis for design optimization before chip tapeout (tape-out, tape-out). Step S3 specifically includes:

[0072] The local metal density and via density are detected in different density detection window areas under each BUMP UBM region inside the chip, and the density detection results of each density detection window area under each BUMP UBM region are obtained. Specifically, the DRC Runset command for design rule detection is run to detect each of the 11 detection windows (A to K) under all BUMP UBM regions inside the chip, and the local metal density and via density data of each window are collected.

[0073] The minimum values ​​of local metal density and via density in the density detection results of each detection window area below each BUMP UBM area are taken as the density detection results corresponding to each BUMP UBM area. Specifically, for each BUMP UBM area, the minimum values ​​of metal density and via density are extracted from the detection results of its 11 windows, respectively, as the representative density results of that UBM area.

[0074] The local metal density and via density corresponding to each BUMP UBM region are compared with the corresponding local metal density threshold and via density threshold below the BUMP UBM region to identify non-compliant BUMP UBM regions. The location of this BUMP UBM region is designated as a density violation location, and a corresponding DRC alarm is issued. Specifically, the minimum metal density of each UBM region is compared with the metal density threshold of the stress zone to which that region belongs, and the minimum via density is compared with the corresponding via density threshold. If either minimum value is less than or equal to the corresponding threshold, the UBM region is determined to be a "density violation location," triggering a DRC alarm and recording the specific location information (such as coordinates, module, etc.). Before chip tapeout, the design of the violation locations is adjusted based on the DRC alarm information until all UBM regions meet the corresponding threshold requirements after re-testing, thus eliminating the DRC error.

[0075] In one embodiment, the density detection results for all BUMP UBM regions (i.e., the minimum metal density and minimum via density for each UBM region) are categorized and visually labeled, for example, as follows: Figure 5When the minimum density of the UBM area is >0.15, it is marked in purple, indicating sufficient density, far exceeding the highest threshold (such as the 0.15 standard for the LR1 area), and belongs to a low-risk area. When the minimum density of the UBM area is between 0.1 and 0.15 (inclusive of the critical value), it is marked in green, indicating that the density meets the medium threshold requirement (such as the 0.1 standard for the LR2 area), but does not reach the highest threshold, and belongs to a medium-low risk area. When the minimum density of the UBM area is <0.1, it is marked in red, indicating that the density is below the medium threshold and may not meet the standards for any stress area (even for the 0.05 standard for the LR3 area, caution is needed regarding situations approaching the critical value), and belongs to a high-risk area, requiring priority handling.

[0076] Based on the color-coded results, accurately mark the location information (such as coordinates, functional modules, and surrounding wiring) of each UBM region on the chip layout diagram. For high-risk areas marked in red, further correlate the raw data of its 11 detection windows to pinpoint which specific window (e.g., the left side of window A, the upper left side of window G, etc.) has insufficient density. For red-marked areas: increase the density of weak windows to above the corresponding threshold by increasing the number of local metal traces or vias (e.g., ≥0.05 for LR3 area, ≥0.1 for LR2 area). For green-marked areas (if the stress area is LR1): appropriately supplement the density to >0.15 to reduce potential risks. During optimization, the surrounding circuit layout must be considered to avoid new design conflicts (such as short circuits, signal interference, etc.) caused by adding metal / vias. After optimization, rerun the DRC detection to confirm that the red-marked areas have turned green or purple and no new violations have occurred; continue until all UBM regions meet the threshold requirements of their respective stress areas, eliminate DRC errors, and ensure design compliance before chip tapeout.

[0077] This application adds specific DRC design rules to the existing metal density and via density DRC rules. The complete set of rules, including these new rules, not only continues the chip manufacturing process requirements for metal density and via density set by the original rules, but also effectively addresses chip failure issues that may be caused by thermal stress during subsequent packaging manufacturing processes and chip soldering to the PCB board. Specifically, by introducing new design rules, the aim is to compensate for the defects and deficiencies in the current DRC design rules provided by wafer foundries based on process requirements, thereby resolving potential quality risks, yield reductions, and failures that may occur in chip packaging manufacturing and PCB SMT reflow soldering.

[0078] Similar to the above embodiments, the present invention provides a metal density and pore density DRC rule detection system.

[0079] The following specific embodiments are provided in conjunction with the accompanying drawings:

[0080] like Figure 6 This diagram illustrates the structure of a metal density and via density DRC rule detection system according to an embodiment of the present invention. The system includes:

[0081] Stress region definition module 1 is used to define the local metal density and via density thresholds for different stress regions on the chip;

[0082] The density detection window definition module 2 is connected to the stress region definition module 1. It is used to define different density detection window regions below each BUMP UBM region inside the chip, and to set new DRC design rules based on the local metal density and via density threshold of each stress region.

[0083] The density detection module 3 is connected to the density detection window definition module 2. It is used to run the DRC design rule, detect the density detection results of different density detection window areas under each BUMP UBM area inside the chip, and determine the density violation location on the chip for optimization design before chip fabrication.

[0084] Since the implementation principle of the DRC rule detection system for metal density and pore density has been described in the foregoing embodiments, it will not be repeated here.

[0085] The metal density and via density DRC rule detection method provided in this invention can be implemented on the terminal side or the server side. For the hardware structure of the electronic terminal, please refer to [link to relevant documentation]. Figure 7 This is a schematic diagram of an optional hardware structure of an electronic terminal 1000 provided in an embodiment of the present invention. The terminal 1000 can be a mobile phone, computer device, tablet device, personal digital processing device, factory back-end processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010, and a user interface 1009. The various components in the device are coupled together through a bus system 1005. It is understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 1005 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 7 The general will label all buses as bus systems.

[0086] The user interface 1009 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0087] It is understood that memory 1002 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0088] In this embodiment of the invention, the memory 1002 is used to store various types of data to support the operation of the terminal 1000. Examples of this data include: any executable program for operation on the terminal 1000, such as the operating system 10021 and application program 10022; the operating system 10021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 10022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The quartz crystal microbalance resonant frequency detection system provided in this embodiment of the invention can be included in the application program 10022.

[0089] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 1001 or by instructions in the form of software. The processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 1001 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in a memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0090] In an exemplary embodiment, the terminal 1000 may be used to execute the aforementioned method by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0091] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0092] In the embodiments provided in this application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, flash memory, USB flash drive, portable hard drive, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended for non-transient, tangible storage media. The disks and optical discs used in the application include compact discs (CDs), laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically.

[0093] In summary, the metal density and via density DRC rule detection method, system, and terminal of this invention define local metal density and via density thresholds for different stress regions on the chip, as well as different density detection window regions below each BUMP UBM region inside the chip. By setting newly added DRC design rules and running these rules, the density detection results of different density detection window regions below each BUMP UBM region inside the chip are detected, and the density violation locations on the chip are determined for optimization design before chip tapeout manufacturing. During the chip design process, this invention, through supplementary metal density and via rule detection, promptly identifies design defects that may lead to chip quality problems in subsequent packaging and PCB SMT processes. Through design optimizations such as metal and via filling, local density is improved, ultimately completely resolving product quality problems caused by material and thermal stress. This improves product yield, reduces manufacturing costs, ensures chips meet mass production requirements, and enhances the competitiveness of enterprise products. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for detecting metal density and via density according to DRC rules, characterized in that, include: Define the local metal density and via density thresholds for different stress regions on the chip; Define different density detection window regions below each BUMP UBM region inside the chip, and set new DRC design rules based on the local metal density and via density thresholds of each stress region. The DRC design rule is run to detect the density detection results of different density detection window areas under each BUMP UBM region inside the chip, and to determine the density violation locations on the chip for optimization design before chip fabrication. The definition of local metal density and via density thresholds for different stress regions on the chip includes: dividing the chip into a first stress region, a second stress region, and a third stress region corresponding to different stresses; wherein the stress in the first stress region is greater than that in the second stress region, and the stress in the second stress region is greater than that in the third stress region; setting local metal density thresholds and via density thresholds for the first stress region, the second stress region, and the third stress region; wherein the values ​​of the local metal density threshold and via density threshold for each of the first stress region, the second stress region, and the third stress region are equal; the values ​​of the local metal density threshold and via density threshold for the first stress region are greater than those for the second stress region, and the values ​​of the local metal density threshold and via density threshold for the second stress region are greater than those for the third stress region. The definition of different density detection window regions below each BUMP UBM region inside the chip, and the setting of newly added DRC design rules based on the local metal density and via density threshold of each stress region, include: dividing the area below each BUMP UBM region inside the chip into multiple density detection window regions; determining the local metal density threshold and via density threshold below each BUMP UBM region based on the local metal density and via density threshold of each stress region, and setting the newly added DRC design rules.

2. The method for detecting metal density and via density according to claim 1, characterized in that, The step of dividing the area below each BUMP UBM region inside the chip into multiple density detection window regions includes: Based on the density detection window region division rules, the area below each BUMP UBM region inside the chip is divided into 11 density detection window regions according to different dimensions.

3. The method for detecting metal density and via density according to claim 2, characterized in that, The density detection window region division rules include: The rectangular area enclosed below the BUMP UBM region is divided horizontally into three density detection window regions of identical size that are sequentially adjacent in the horizontal direction. The rectangular area enclosed below the BUMP UBM region is divided longitudinally into three equally sized density detection window regions that are sequentially adjacent in the longitudinal direction. Using the center point of the BUMP UBM region as a reference, the rectangular region enclosed below the BUMP UBM region is divided into four density detection window regions that are centrally symmetrically distributed. The entire rectangular area enclosed below the BUMP UBM region is used as a density detection window area.

4. The method for detecting metal density and via density according to claim 1, characterized in that, Based on the local metal density and via density thresholds of each stress region, the local metal density threshold and via density threshold below each BUMP UBM region are determined, and the newly added DRC design rules are set, including: Determine the stress region where each BUMP UBM region is located, and use the local metal density threshold and via density threshold of the corresponding stress region as the local metal density threshold and via density threshold below the corresponding BUMP UBM region. A new DRC design rule is added to detect whether each BUMP UBM region is a density violation location, based on the local metal density threshold and via density threshold set below each BUMP UBM region.

5. The method for detecting metal density and via density according to claim 4, characterized in that, The detection chip detects the metal density and via density in different density detection window areas below each BUMP UBM region, and determines the density violation locations based on the density detection results of each density detection window area below each BUMP UBM region, including: The local metal density and via density are detected in different density detection window areas below each BUMP UBM region inside the chip, and the density detection results of each density detection window area below each BUMP UBM region are obtained. The minimum value of the local metal density and via density in the density detection results of each degree detection window area below each BUMP UBM area is taken as the density detection result corresponding to each BUMP UBM area. The local metal density and via density corresponding to each BUMP UBM area are compared with the local metal density threshold and via density threshold below the corresponding BUMP UBM area to determine the non-compliant BUMP UBM area. The location of the BUMP UBM area is then designated as the density violation location, and a corresponding DRC alarm message is issued.

6. The method for detecting metal density and via density DRC according to claim 5, characterized in that, The density detection results for each BUMP UBM area are indicated by different colors.

7. A DRC (Diameter Reduction Code) detection system for metal density and via density, characterized in that, include: The stress region definition module is used to define the local metal density and via density thresholds for different stress regions on the chip; The density detection window definition module is connected to the stress region definition module. It is used to define different density detection window regions below each BUMP UBM region inside the chip, and to set new DRC design rules based on the local metal density and via density threshold of each stress region. The density detection module, connected to the density detection window definition module, is used to run the DRC design rule, detect the density detection results of different density detection window areas under each BUMP UBM area inside the chip, and determine the density violation location on the chip for optimization design before chip fabrication. The definition of local metal density and via density thresholds for different stress regions on the chip includes: dividing the chip into a first stress region, a second stress region, and a third stress region corresponding to different stresses; wherein the stress in the first stress region is greater than that in the second stress region, and the stress in the second stress region is greater than that in the third stress region; setting local metal density thresholds and via density thresholds for the first stress region, the second stress region, and the third stress region; wherein the values ​​of the local metal density threshold and via density threshold for each of the first stress region, the second stress region, and the third stress region are equal; the values ​​of the local metal density threshold and via density threshold for the first stress region are greater than those for the second stress region, and the values ​​of the local metal density threshold and via density threshold for the second stress region are greater than those for the third stress region. The definition of different density detection window regions below each BUMP UBM region inside the chip, and the setting of newly added DRC design rules based on the local metal density and via density threshold of each stress region, include: dividing the area below each BUMP UBM region inside the chip into multiple density detection window regions; determining the local metal density threshold and via density threshold below each BUMP UBM region based on the local metal density and via density threshold of each stress region, and setting the newly added DRC design rules.

8. An electronic terminal, characterized in that, include: One or more memories and one or more processors; The one or more memories are used to store computer programs; The one or more processors are connected to the memory and are used to run the computer program to perform the method as described in any one of claims 1 to 6.

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