Storage circuit, memory and method of performing a write operation

Abstract

The application discloses a storage circuit, which comprises a storage unit, a first switch unit and a coupling unit. The storage unit comprises a bit line. The first switch unit is connected with the bit line and is used for being turned on to provide a first working voltage to the bit line when a write operation is performed on the storage unit. The coupling unit is connected with the first switch unit and is used for coupling and boosting the first working voltage according to a coupling level signal when the write operation is performed on the storage unit. The circuit can balance the write operation time and the service life of the storage element.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a storage circuit, a memory, and a method for performing write operations. Background Technology

[0002] In recent years, with the continuous deepening of research on novel non-volatile memories, RRAM (Resistive Random-Access Memory), as a new type of non-volatile memory technology, can store data based on resistance changes by adjusting the resistance state in the material. RRAM has faster read and write speeds and lower energy consumption.

[0003] However, in the prior art, in order to reduce the write operation time and complete the data writing quickly, RRAM needs to use a longer pulse to write data "1" each time, which causes the WLMOS element to be subjected to high voltage for a long time, thus affecting the lifespan of the WLMOS element. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a memory circuit that can achieve a balance between write operation time and memory element lifespan.

[0005] The second objective of this invention is to provide a memory.

[0006] The third objective of this invention is to provide a method for performing write operations.

[0007] To address the aforementioned problems, a first aspect of the present invention provides a storage circuit comprising: a storage cell including a bit line; and a first switching unit connected to the bit line, wherein the first switching unit is configured to be turned on when a write operation is performed on the storage cell to provide a first operating voltage to the bit line. A coupling unit is connected to the first switching unit. The coupling unit is used to couple and boost the first operating voltage according to the coupling level signal when performing a write operation on the memory unit.

[0008] According to the storage circuit of the present invention, by setting a coupling unit, the first working voltage is coupled and boosted when the storage cell performs a write operation, and the bit line voltage of the storage cell is instantly boosted, reducing the time when the storage cell performs a write operation. Furthermore, during the write operation, the first working voltage is reduced due to the influence of the bit line current. Compared with the prior art where the bit line is maintained at a high voltage for a long time, this application avoids the storage element being subjected to high voltage for a long time, increases the lifespan of the storage element, and achieves the purpose of balancing the write operation time and the lifespan of the storage element through the coupling boost method.

[0009] In some embodiments, the coupling unit includes a capacitor, a first end of which is adapted to receive the coupling level signal, and a second end of which is connected to the first switching unit.

[0010] In some embodiments, the coupling level signal is a level-jumping signal.

[0011] In some embodiments, the first switching unit includes: a first switching subunit, a first end of which is adapted to receive the first operating voltage, and a second end of which is connected to the coupling unit; and a second switching subunit, a first end of which is connected to the second end of the first switching subunit, and a second end of which is connected to the bit line.

[0012] In some embodiments, the first switching subunit includes: a first MOSFET, the first non-gate terminal of the first MOSFET being adapted to receive the first operating voltage, and the gate of the first MOSFET being connected to a reference voltage; a second MOSFET, the first non-gate terminal of the second MOSFET being connected to the second non-gate terminal of the first MOSFET, and the second non-gate terminal of the second MOSFET being connected to the coupling unit and the first terminal of the second switching subunit; and a NAND gate U, the NAND gate being connected to the gate of the second MOSFET and used to control whether the second MOSFET is turned on.

[0013] In some embodiments, the second switching subunit includes: a third MOS transistor, wherein the non-gate first terminal of the third MOS transistor is connected to the coupling unit and the second terminal of the first switching subunit, the non-gate second terminal of the third MOS transistor is connected to the bit line, and the gate of the third MOS transistor is used to receive a first switch enable signal; and a fourth MOS transistor, wherein the non-gate first terminal of the fourth MOS transistor is connected to the non-gate first terminal of the third MOS transistor and the coupling unit, the non-gate second terminal of the fourth MOS transistor is connected to the non-gate second terminal of the third MOS transistor and the bit line, and the gate of the fourth MOS transistor is used to receive a second switch enable signal.

[0014] In some embodiments, the storage circuit further includes a second switching unit, which is connected in series between the first switching unit and the bit line.

[0015] In some embodiments, the storage circuit further includes: a third switching unit, wherein the control terminal of the third switching unit is adapted to receive a static control signal, the first terminal of the third switching unit is connected to the first switching unit and the second switching unit, the second terminal of the third switching unit is grounded, and the third switching unit is used to turn on when no read / write operation is performed on the storage unit.

[0016] In some embodiments, the storage circuit further includes a fourth switching unit connected to the first switching unit, the second switching unit, and the third switching unit, the fourth switching unit being configured to be turned on when a read operation is performed on the storage cell to apply a second operating voltage to the bit line.

[0017] In some embodiments, both the second switching unit and the fourth switching unit include a CMOS transmission gate.

[0018] In some embodiments, there are multiple storage cells, and the bit lines of the multiple storage cells are connected together.

[0019] A second aspect of the present invention provides a memory including the storage circuit described in the above embodiments.

[0020] According to the memory of the present invention, data writing through the storage circuit can achieve a balance between write operation time and storage element lifespan.

[0021] A third aspect of the present invention provides a method for performing a write operation for a memory described in the above embodiments. The method includes: reading a write operation instruction; and, in response to the write operation instruction, sending a coupling level signal to the coupling unit to couple and boost a first operating voltage.

[0022] According to the method for performing a write operation according to an embodiment of the present invention, when the memory reads a write operation instruction, it performs a write operation and controls the coupling unit to couple and boost the first working voltage through a coupling level signal, so that the bit line voltage of the memory cell 1 is raised, reducing the time when the memory cell performs a write operation. After the write operation is completed, the first working voltage will decrease and the bit line voltage of the memory cell will recover, avoiding the memory element from being subjected to high voltage for a long time and increasing the life of the memory element. The purpose of balancing the write operation time and the life of the memory element is achieved through dynamic voltage boosting.

[0023] In some embodiments, the coupling level signal is a level-jumping signal.

[0024] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the operating circuit structure; Figure 2 This is a write operation timing diagram; Figure 3 This is a schematic diagram of the circuit topology of a storage circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit topology of a storage circuit according to another embodiment of the present invention; Figure 5 This is a timing diagram of a write operation according to an embodiment of the present invention; Figure 6 This is a structural block diagram of a memory according to an embodiment of the present invention; Figure 7 This is a flowchart of a method for performing a write operation according to an embodiment of the present invention.

[0026] Figure label: Memory 100; Storage circuit 10; Storage unit 1; first switching unit 2; coupling unit 3; second switching unit 4; third switching unit 5; fourth switching unit 6; capacitor C; first switching subunit 21; second switching subunit 22; first MOSFET M1; second MOSFET M2; third MOSFET M3; fourth MOSFET M4. Detailed Implementation

[0027] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0028] In existing technology, writing data "1" to RRAM involves applying a high voltage to the BL (bit line) and 0V to the SL (source line), thus enabling the WL (word line) to switch the RRAM cell data from data "0" to data "1". There are two methods for writing data: 1. Using a high voltage + short pulse method. This method involves many pulses and multiple state machine repetitions, writing data "1" with a short pulse each time. Each state machine repetition results in a longer write operation time. 2. Using a slightly lower voltage + long pulse method. This method involves fewer pulses and fewer state machine repetitions, writing data "1" with a longer pulse each time. However, this causes the WL MOS element to be subjected to high voltage for extended periods, which can affect the lifespan of the WL MOS element. For example, ... Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of a storage circuit in the prior art. Figure 2 This is a timing diagram of a write operation in the prior art. When performing a write operation, the prior art needs to maintain a high voltage for a long time, which causes the WL MOS device to be subjected to high voltage for a long time, affecting the device's lifespan.

[0029] To address the aforementioned problems, a first aspect of the present invention provides a storage circuit that can achieve a balance between write operation time and storage element lifespan.

[0030] The following is for reference. Figure 3 A storage circuit 10 according to an embodiment of the present invention is described. The storage circuit 10 includes a storage unit 1, a first switching unit 2, and a coupling unit 3.

[0031] The storage unit 1 includes a bit line; a first switching unit 2 is connected to the bit line and is used to turn on when a write operation is performed on the storage unit 1 to provide a first operating voltage to the bit line; a coupling unit 3 is connected to the first switching unit 2 and is used to couple and boost the first operating voltage according to the coupling level signal when a write operation is performed on the storage unit 1.

[0032] Specifically, the storage circuit 10 can change the resistance state of the storage cell 1 by applying voltage to the bit line to achieve data writing. When the storage circuit 10 is writing data, it controls the first switching unit to turn on, transmitting the first operating voltage to the bit line, such as... Figure 3As shown, the arrow points to the transmission direction of the first operating voltage, which is transmitted from the first switching unit 2 to the memory unit 1. Simultaneously, the coupling unit 3 receives the coupling level signal and couples the first operating voltage VPROG to boost it, instantly raising the bit line voltage. A higher bit line voltage shortens the write operation time of memory unit 1. After the coupling boost, during the write operation, the first operating voltage gradually decreases due to the influence of the bit line current, unlike the long-term high voltage maintained in existing technologies. This avoids prolonged high voltage exposure to the memory element, increasing its lifespan. Dynamic boosting achieves a balance between write operation time and memory element lifespan, reducing damage to the memory element while shortening the write operation time, thus increasing its lifespan. The coupling level signal provides a clear moment to begin data transmission, ensuring that data is written to the memory at the correct time, which is especially important in asynchronous or semi-synchronous bus systems.

[0033] According to the storage circuit 10 of the present invention, by setting a coupling unit 3, the first working voltage is coupled and boosted when the storage cell 1 performs a write operation, and the bit line voltage of the storage cell 1 is instantly boosted, reducing the time when the storage cell 1 performs a write operation. Furthermore, during the write operation, the first working voltage is reduced due to the influence of the bit line current. Compared with the prior art where the bit line is maintained at a high voltage for a long time, this application avoids the storage element being subjected to high voltage for a long time, increases the lifespan of the storage element, and achieves the purpose of balancing the write operation time and the lifespan of the storage element through the coupling boost method.

[0034] In some embodiments, such as Figure 3 As shown, coupling unit 3 includes capacitor C.

[0035] The first end of capacitor C is adapted to receive coupled level signals, and the second end of capacitor C is connected to the first switching unit 2.

[0036] Specifically, since the voltage across capacitor C does not change abruptly, the capacitor can couple the coupling level signal received at the first end to the second end, thereby superimposing the coupling level signal with the first operating voltage, thus raising the bit line voltage of memory cell 1 and reducing the time when memory cell 1 performs a write operation.

[0037] In some embodiments, the coupling level signal is a level-hopping signal.

[0038] Specifically, before performing a write operation on memory cell 1, the first terminal of capacitor C receives a coupling level signal. At this time, the coupling level signal remains in the initial low level state, and there is no voltage difference across capacitor C. When a write operation needs to be performed on memory cell 1, the coupling level signal will periodically switch between the initial low level state and the high level state. When the coupling level signal jumps from the initial low level state to the high level state instantaneously, since the voltage across capacitor C cannot change abruptly, the coupling level signal is coupled to the first switching unit through capacitor C and superimposed on the first operating voltage to couple and boost the first operating voltage, thereby raising the bit line voltage of memory cell 1 and reducing the time for memory cell 1 to perform a write operation. After a fixed time interval, the coupling level signal will also return from the high level state to the initial low level state. When the coupling level signal is in the high level state, the storage write cycle for memory cell 1 will be started. After the write operation on memory cell 1 is completed, the coupling level signal will also return to the initial low level state. In this design, after the first operating voltage is coupled and boosted, the first operating voltage will gradually decrease with the bit line current, instead of maintaining a high voltage continuously as in existing technologies. This avoids the memory element being subjected to high voltage for extended periods, thus increasing the lifespan of the memory element. The time interval between the coupling level signal transitioning from a low to a high state can be set according to actual conditions and is not specifically limited here.

[0039] It should be noted that the coupling level signal can work in conjunction with the memory's clock signal and other control signals to meet the specific write timing requirements of memory cell 1.

[0040] For example, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the write operation timing in an embodiment of the present invention. In this diagram, PIO-TRIG is a coupling level signal. The coupling level signal changes from TCL low level to TCH high level multiple times. The coupling level signal can achieve one coupling boost of the first working voltage by changing from TCL low level to TCH high level. By repeatedly changing from TCL low level to TCH high level, the bit line can be given high voltage multiple times, thereby realizing the write operation on memory cell 1.

[0041] In some embodiments, such as Figure 3 As shown, the first switch unit 2 includes a first switch subunit 21 and a second switch subunit 22.

[0042] The first terminal of the first switch subunit 21 is adapted to receive the first working voltage, and the second terminal of the first switch subunit 21 is connected to the coupling unit 3; the first terminal of the second switch subunit 22 is connected to the second terminal of the first switch subunit 21, and the second terminal of the second switch subunit 22 is connected to the bit line.

[0043] Specifically, such as Figure 3 As shown, the first end of capacitor C is adapted to receive the coupled level signal, and the second end of capacitor C is connected to the second end of the first switch subunit 21 and the first end of the second switch subunit 22. Before the memory cell 1 performs a write operation, both the first switch subunit 21 and the second switch subunit 22 are in the off state. At this time, the PIO node is in a floating or preset low level state, and the coupled level signal is in the initial low level state. When the memory cell 1 is written, the first switch subunit 21 is turned on to charge the PIO node and transmit the first working voltage to the PIO node. Then the coupled level signal jumps from the initial low level state to the high level state. Since the voltage across capacitor C cannot change abruptly, the high-level coupled level signal is coupled to the second end of capacitor C, i.e., the PIO node. At this time, the PIO node is instantly boosted to the superposition of the first working voltage and the coupled level signal. Then, turning on the second switch subunit 22 can transmit the voltage of the PIO node to the second end of the second switch subunit 22, providing the first working voltage after coupling boost to the bit line.

[0044] For example, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the circuit topology for PIO node coupling boost, where V(PIO_TRIG) is the coupling level signal, V(PIO) is the voltage of the PIO node, the total charge of the storage circuit is Q, and Cb1 is the circuit between the PIO node and the bit line. When a write operation is performed on storage cell 1, the first switch subunit 21 is turned on to charge the PIO node, transmitting the first working voltage to the PIO node. At this time, V(PIO_TRIG) is 0V, V(PIO) is Vpgm, and the total charge Q of the circuit is V(PIO)×C+V(PIO)×Cbl. The coupling level signal changes from the initial low level state to the high level state, and V(PIO_TRIG) changes from 0V to VH. If the voltage of the PIO node after coupling boost is Vcouple(PIO), referring to formulas 1, 2, and 3, according to the principle of charge conservation, we know... Both the capacitance of capacitor C and the high-level state of the coupled signal can increase the boost value of the first operating voltage. Specifically, the voltage boost from the first operating voltage is VH × C / (C + Cbl).

[0045] [Vcouple(PIO)-V(PIO)]×C+Vcouple(PIO)×Cbl=V(PIO)×C+V(PIO)×Cbl Formula 1 [Vcouple(PIO)-VH]×C+Vcouple(PIO)×Cbl= Vpgm×C+Vpgm×Cbl (Formula 2) Vcouple(PIO) = Vpgm + VH × C / (C + Cbl) (Formula 3) In some embodiments, such as Figure 3 As shown, the first switching subunit 21 includes: a first MOS transistor M1, a second MOS transistor M2, and a NAND gate U.

[0046] The first non-gate terminal of the first MOS transistor is adapted to receive the first operating voltage, and the gate of the first MOS transistor is connected to the reference voltage; the first non-gate terminal of the second MOS transistor is connected to the second non-gate terminal of the first MOS transistor, and the second non-gate terminal of the second MOS transistor is connected to the first terminal of the coupling unit 3 and the second switch sub-unit 22; the NAND gate is connected to the gate of the second MOS transistor M2 and is used to control whether the second MOS transistor M2 is turned on.

[0047] Specifically, the magnitude of the reference voltage VPBIAS is controlled to control whether the first MOSFET M1 is turned on, thereby determining whether the first working voltage is transmitted to the second MOSFET M2. The NAND gate U determines whether to input a control signal to the gate of the second MOSFET M2 based on its input logic signals PCKON and SIBUS. When the control signal meets the turn-on condition of the second MOSFET, the second MOSFET M2 is turned on, and the first working voltage can be further transmitted to the first terminal of the coupling unit 3 and the second switch subunit 22.

[0048] It should be noted that the non-gate first terminal of the first MOSFET M1 can be either the source or the drain, and the corresponding non-gate second terminal of the first MOSFET M1 can be either the drain or the source. The non-gate first terminal of the second MOSFET M1 can be either the source or the drain, and the corresponding non-gate second terminal of the second MOSFET M2 can be either the drain or the source. These settings can be configured according to actual conditions, and no specific restrictions are imposed here. For example, the non-gate first terminal of the first MOSFET M1 can be the source and the non-gate second terminal can be the drain, and the non-gate first terminal of the second MOSFET M2 can be the source and the non-gate second terminal can be the drain; or the non-gate first terminal of the first MOSFET M1 can be the drain and the non-gate second terminal can be the source, and the non-gate first terminal of the second MOSFET M2 can be the drain and the non-gate second terminal can be the source.

[0049] Taking the non-gate first terminal as the source and the non-gate second terminal as the drain as an example, the control reference voltage is the conduction voltage of the first MOS transistor M1. When the first MOS transistor M1 is turned on, the source of the first MOS transistor receives the working voltage and transmits the first working voltage to the source of the second MOS transistor M2 through its gate, thus entering the second MOS transistor M2. The NAND gate U determines that the second MOS transistor M2 is turned on according to its input logic signal and outputs the control signal as the conduction voltage of the second MOS transistor M2, controlling the second MOS transistor M2 to turn on. The first working voltage is transmitted from the gate of the second MOS transistor M2 to the first terminal of the coupling unit 3 and the second switch subunit 22.

[0050] In some embodiments, such as Figure 3 As shown, the second switching subunit 22 includes a third MOS transistor M3 and a fourth MOS transistor M4.

[0051] In this configuration, the non-gate first terminal of the third MOS transistor M3 is connected to the coupling unit 3 and the second terminal of the first switch subunit 21, the non-gate second terminal of the third MOS transistor M3 is connected to the bit line, and the gate of the third MOS transistor M3 is used to receive the first switch enable signal; the non-gate first terminal of the fourth MOS transistor M4 is connected to the non-gate first terminal of the third MOS transistor M3 and the coupling unit 3, the non-gate second terminal of the fourth MOS transistor M4 is connected to the non-gate second terminal of the third MOS transistor M3 and the bit line, and the gate of the fourth MOS transistor M4 is used to receive the second switch enable signal.

[0052] Specifically, when the third MOSFET M3 is turned on and the fourth MOSFET is turned off, or when the third MOSFET M3 is turned off and the fourth MOSFET is turned on, the second switching unit 22 is turned on. Since PMOS transistors have poor low-voltage transmission capability and NMOS transistors have poor high-voltage transmission capability, in order to ensure the transmission of the first working voltage, the third MOSFET M3 and the fourth MOSFET M4 are designed to be a combination of PMOS transistors and NMOS transistors, thereby ensuring that the working voltage can be transmitted smoothly in both low-voltage and high-voltage states.

[0053] In this configuration, the third MOS transistor M3 is an NMOS transistor, meaning that the first non-gate terminal of the third MOS transistor is the source and the second non-gate terminal is the drain; the fourth MOS transistor M4 is a PMOS transistor, meaning that the first non-gate terminal of the fourth MOS transistor M4 is the drain and the second non-gate terminal is the source; or the third MOS transistor M3 is an NMOS transistor, meaning that the first non-gate terminal of the third MOS transistor M3 is the drain and the second non-gate terminal is the source, and the fourth MOS transistor M4 is a PMOS transistor, meaning that the first non-gate terminal of the fourth MOS transistor M4 is the source and the second non-gate terminal is the drain. No specific restrictions are imposed here.

[0054] For example, the third MOSFET M3 is an NMOS transistor, and the fourth MOSFET M4 is a PMOS transistor. That is, the non-gate first terminal of the third MOSFET is the source and the non-gate second terminal is the drain, and the non-gate first terminal of the fourth MOSFET M4 is the drain and the non-gate second terminal is the source. If the first operating voltage is a low voltage signal, the third MOSFET M3 is turned on by the first switch enable signal PIOENb, and the first operating voltage is transmitted to the source of the third MOSFET M3 and then to the bit line from the drain of the third MOSFET M3. If the first operating voltage is a high voltage signal, the fourth MOSFET M4 is turned on by the second switch enable signal PIOEN, and the first operating voltage is transmitted to the drain of the fourth MOSFET M4 and then to the bit line from the source of the fourth MOSFET M4.

[0055] In some embodiments, such as Figure 3 As shown, the storage circuit also includes a second switching unit 4.

[0056] The second switch unit 4 is connected in series between the first switch unit 2 and the bit line.

[0057] Specifically, the second switching unit 4 is controlled independently of the first switching unit 2. The transmission of the working voltage can be controlled by controlling the on and off of the first switching unit 2 and the second switching unit 4. The first working voltage can be transmitted to the bit line only when the first switching unit 2 and the second switching unit 4 are on at the same time, so that a write operation can be performed on the memory unit 1.

[0058] In some embodiments, such as Figure 3 As shown, the storage circuit 10 also includes a third switching unit 5.

[0059] Among them, the control terminal of the third switch unit 5 is adapted to receive static control signals, the first terminal of the third switch unit 5 is connected to the first switch unit 2 and the second switch unit 4, the second terminal of the third switch unit 5 is grounded, and the third switch unit 5 is used to turn on when no read / write operation is performed on the storage unit 1.

[0060] Specifically, the IO GND, or static control signal, determines the conduction state of the third switch unit 5. When the storage circuit 10 does not perform read / write operations on the storage unit 1, the static control signal IO GND controls the third switch unit 5 to conduct, pulling the connection node between the first switch unit 2 and the second switch unit 4 down to ground potential, releasing the residual charge between the storage unit 1 and the bit line, and preventing the accumulation of charge from affecting subsequent read / write operations on the storage unit 1.

[0061] In some embodiments, such as Figure 3 As shown, the storage circuit also includes a fourth switching unit 6.

[0062] The fourth switch unit 6 is connected to the first switch unit 2, the second switch unit 4, and the third switch unit 8. The fourth switch unit 6 is used to turn on when a read operation is performed on the storage unit 1 to apply a second working voltage to the bit line.

[0063] Specifically, when no read operation is performed on memory cell 1, the fourth switch unit 6 is turned off. When a read operation is performed on memory cell 1, the fourth switch unit 6 is turned on, and the second operating voltage is transmitted to the bit line through the fourth switch unit 6. After receiving the second operating voltage, memory cell 1 executes the data reading function, reads the data from the specified address, and sends it to the data bus. The second operating voltage can be set according to the actual situation, and no specific restrictions are imposed here.

[0064] In some embodiments, both the second switching unit and the fourth switching unit include a CMOS transmission gate.

[0065] Specifically, due to the inherent limitations of voltage transmission capability of a single MOS transistor, PMOS transistors have poor low-voltage transmission capability while NMOS transistors have poor high-voltage transmission capability. To ensure the transmission of the operating voltage, both the second switching unit 4 and the fourth switching unit 6 are designed to include CMOS transmission gates, ensuring the smooth transmission of the first and second operating voltages.

[0066] For example, when the first operating voltage is a low-voltage signal, the second switching unit 4 controls the NMOS transistor to turn on through the control signal YSELb, while the PMOS transistor remains off, and the NMOS transistor transmits the first operating voltage to the bit line; when the first operating voltage is a high-voltage signal, the second switching unit 4 controls the PMOS transistor to turn on through the control signal YSEL, while the NMOS transistor remains off, and the PMOS transistor transmits the first operating voltage to the bit line; when the second operating voltage is a low-voltage signal, the fourth switching unit 6 controls the NMOS transistor to turn on through the control signal SAENb, while the PMOS transistor remains off, and the NMOS transistor transmits the first operating voltage to the bit line; when the first operating voltage is a high-voltage signal, the second switching unit 4 controls the PMOS transistor to turn on through the control signal SAEN, while the NMOS transistor remains off, and the PMOS transistor transmits the first operating voltage to the bit line.

[0067] In some embodiments, there are multiple storage cells 1, and the bit lines of the multiple storage cells are connected together.

[0068] Specifically, using the same bit line for multiple memory cells can reduce the number of bit lines and the occupation of metal interconnects. The target memory cell 1 can be selected by the word line. Applying a high level to the word line of the target memory cell 1 and applying a low level to the word lines of other memory cells 1 can select the target memory cell 1 to perform a write operation.

[0069] For example, such as Figure 3 As shown, taking two storage cells 1 as an example, storage cell 1 includes storage cell 11 and storage cell 12. To perform a write operation on storage cell 11, a high level is applied to the WLO word line and a low level is applied to the WLn word line; or to perform a write operation on storage cell 12, a high level is applied to the WLn word line and a low level is applied to the WLO word line.

[0070] A second aspect of the present invention provides a memory 100, such as Figure 6 As shown, the memory 100 includes a storage circuit 10.

[0071] According to the memory 100 of the present invention, data writing is performed through the storage circuit 10, which can achieve the purpose of balancing the write operation time and the lifespan of the storage element.

[0072] A third aspect of the present invention provides a method for performing a write operation in a memory 100, as described in the following reference. Figure 7 As shown, a method for performing a write operation according to an embodiment of the present invention includes at least steps S1-S2, and the specific steps are as follows.

[0073] Step S1: Read the write operation instruction.

[0074] Specifically, the CPU or other processor prepares the data to be written in advance, places it on the data bus, and sets the corresponding address lines to point to the target memory cell 1. After the above preparation is completed, a write operation is issued to the memory 100. After receiving the write operation instruction, the memory 100 begins to execute the data writing process, capturing the data from the data bus and storing it at the specified address.

[0075] Step S2: In response to the write operation command, a coupling level signal is sent to the coupling unit to couple and boost the first operating voltage.

[0076] Specifically, after receiving a write operation instruction, the memory 100 captures the data from the data bus and stores it at the specified address, and sends a coupling level signal to the coupling unit 3. This couples and boosts the first operating voltage through the coupling unit 3, instantly raising the bit line voltage. A higher bit line voltage can shorten the write operation time of the memory cell 1. After the coupling boost, during the write operation, the first operating voltage will gradually decrease due to the influence of the bit line current, instead of maintaining a high voltage for a long time as in the prior art. This avoids the memory element being subjected to high voltage for a long time, increasing the lifespan of the memory element. The dynamic boost achieves a balance between the write operation time and the lifespan of the memory element, shortening the write operation time while reducing damage to the memory element and increasing the lifespan of the memory element.

[0077] According to the method for performing a write operation according to an embodiment of the present invention, when the memory reads a write operation instruction, it performs a write operation and controls the coupling unit 3 to couple and boost the first working voltage through a coupling level signal, so that the bit line voltage of the memory cell 1 is raised, reducing the time when the memory cell 1 performs a write operation. After the write operation is completed, the first working voltage will decrease and the bit line voltage of the memory cell 1 will recover, avoiding the memory element from being subjected to high voltage for a long time and increasing the life of the memory element. The purpose of balancing the write operation time and the life of the memory element is achieved through dynamic voltage boosting.

[0078] In some embodiments, the coupling level signal is a level-hopping signal.

[0079] Specifically, before the write operation is performed in memory cell 1, the first terminal of capacitor C receives a coupling level signal. At this time, the coupling level signal remains at its initial low level, and there is no voltage difference across capacitor C. When memory cell 1 needs to perform a write operation, the coupling level signal instantly jumps from its initial low level to a high level. Since the voltage across capacitor C cannot change abruptly, the coupling level signal is coupled to the first switching unit through capacitor C, superimposed on the first operating voltage, and coupled to boost the first operating voltage, thereby raising the bit line voltage of memory cell 1 and reducing the time required for memory cell 1 to perform a write operation. After the write operation of memory cell 1 is completed, the coupling level signal returns to its initial low level. Notably, after the first operating voltage is coupled and boosted, the first operating voltage gradually decreases with the bit line current, rather than being maintained at a high voltage as in existing technologies. This avoids the memory element being subjected to high voltage for extended periods, increasing the lifespan of the memory element.

[0080] It should be noted that the time interval between the low-level signal transitioning to the high-level signal can be set according to the actual situation, and no specific limit is imposed here.

[0081] For example, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the write operation timing in an embodiment of the present invention. In this diagram, PIO-TRIG is a coupling level signal. The coupling level signal changes from TCL low level to TCH high level multiple times. The coupling level signal can achieve a coupling boost of the first working voltage by changing from TCL low level to TCH high level. By repeatedly changing from TCL low level to TCH high level, the high voltage of the bit line can be applied multiple times, thereby performing a write operation on memory cell 1.

[0082] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0083] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A storage circuit, characterized in that, include: Storage unit; A first switching unit is connected to the memory cell via a bit line. The first switching unit is used to turn on when a write operation is performed on the memory cell to provide a first operating voltage to the bit line. A coupling unit is connected to the first switching unit, and the coupling unit is used to couple and boost the first operating voltage according to the coupling level signal when performing a write operation on the memory unit. The first switching unit includes a first switching subunit and a second switching subunit. The first terminal of the first switching subunit is adapted to receive the first operating voltage, and the second terminal of the first switching subunit is connected to the coupling unit. The first switch subunit includes: A first MOS transistor, wherein the non-gate first terminal of the first MOS transistor is adapted to receive the first operating voltage, and the gate of the first MOS transistor is connected to a reference voltage; The second MOSFET has its non-gate first terminal connected to the non-gate second terminal of the first MOSFET, and its non-gate second terminal is connected to the first terminal of the coupling unit and the second switching subunit. A NAND gate, which is connected to the gate of the second MOS transistor, is used to control whether the second MOS transistor is turned on.

2. The storage circuit according to claim 1, characterized in that, The coupling unit includes: A capacitor, wherein a first end of the capacitor is adapted to receive the coupled level signal, and a second end of the capacitor is connected to the first switching unit.

3. The storage circuit according to claim 1, characterized in that, The coupling level signal is a level-jumping signal.

4. The storage circuit according to any one of claims 1-3, characterized in that, The first end of the second switch subunit is connected to the second end of the first switch subunit, and the second end of the second switch subunit is connected to the bit line.

5. The storage circuit according to claim 4, characterized in that, The second switching subunit includes: The third MOS transistor has its non-gate first terminal connected to the coupling unit and the second terminal of the first switch subunit, and its non-gate second terminal connected to the bit line. The gate of the third MOS transistor is used to receive the first switch enable signal. The fourth MOS transistor has its non-gate first terminal connected to the non-gate first terminal of the third MOS transistor and the coupling unit, and its non-gate second terminal connected to the non-gate second terminal of the third MOS transistor and the bit line. The gate of the fourth MOS transistor is used to receive the second switch enable signal.

6. The storage circuit according to claim 1, characterized in that, The storage circuit also includes: The second switching unit is connected in series between the first switching unit and the bit line.

7. The storage circuit according to claim 6, characterized in that, The storage circuit also includes: The third switching unit has a control terminal adapted to receive a static control signal, a first terminal connected to the first switching unit and the second switching unit, and a second terminal grounded. The third switching unit is used to turn on when no read / write operation is performed on the storage unit.

8. The storage circuit according to claim 7, characterized in that, The storage circuit also includes: A fourth switching unit is connected to the first switching unit, the second switching unit, and the third switching unit. The fourth switching unit is used to turn on when a read operation is performed on the memory unit to apply a second operating voltage to the bit line.

9. The storage circuit according to claim 8, characterized in that, Both the second switching unit and the fourth switching unit include CMOS transmission gates.

10. The storage circuit according to claim 1, characterized in that, The storage unit comprises multiple units, and the bit lines of the multiple storage units are connected together.

11. A memory, characterized in that, Includes the storage circuit described in any one of claims 1-10.

12. A method for performing a write operation, characterized in that, For the memory of claim 11, the method includes: A write operation command was read. In response to the write operation command, a coupling level signal is sent to the coupling unit to couple and boost the first operating voltage.

13. The method for performing a write operation according to claim 12, characterized in that, The coupling level signal is a level-jumping signal.

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