多通道同步的数字TR组件
By combining the phase-locked loop module and the clock synchronization module, the multi-channel synchronization of the digital TR component is realized by using the interface control FPGA, which solves the synchronization problem in the existing technology and ensures the stability of clock synchronization and information transmission of each channel.
Patent Information
- Application Number
- CN202511334457.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-18
- Publication Date
- 2026-07-17
- Estimated Expiration
- 2045-09-18
AI Technical Summary
In existing technologies, multi-channel synchronization technology for digital TR components is difficult to achieve high efficiency, and existing technologies cannot guarantee efficient synchronization and stable information transmission between multiple channels in large-scale complex systems.
A phase-locked loop (PLL) module receives the first reference clock signal and outputs the second reference clock signal. A clock synchronization module distributes the clock signal. An interface control FPGA controls the PLL module and the clock synchronization module. A clock divider is used to achieve synchronization of each target device.
This achieves consistency in the clock phase of each channel, ensures clock synchronization between target devices, and promotes synchronous transmission of multi-channel signals.
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Figure CN121261730B_ABST
Abstract
Citation Information
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