A method of manufacturing a field effect transistor and a field effect transistor

Abstract

This invention provides a method for manufacturing a field-effect transistor (FET) and the FET itself. The method includes: forming a first trench in a first conductivity type semiconductor drift region; forming a second trench in the first trench; anisotropically etching a first oxide layer formed in the second trench; ion implantation into the etched second trench to form a superjunction-like pillar region; and forming a shielding gate polysilicon electrode within the second trench. The FET manufacturing method provided in this application integrates a superjunction structure and a shielding gate structure within the same FET, giving the FET the advantages of both superjunction and shielding gate structures. This significantly reduces on-resistance, increases breakdown voltage, overcomes the limitations of ion diffusion in traditional superjunction processes, controls the formation width of the superjunction structure, and simplifies the process implementation.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a method for manufacturing a field-effect transistor and the field-effect transistor itself. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in various power systems due to their advantages such as fast switching speed, low power consumption, easy gate driving, low drive power, high input impedance, and fast frequency response.

[0003] In practical applications, superjunction structures are used to break the "silicon limit" of traditional power MOSFETs, forming devices with high voltage withstand, low on-resistance, and fast switching speed. However, due to limitations in aspect ratio and ion diffusion effects during the manufacturing process, superjunction structures are primarily used in high-voltage devices. Shielded gate structures are used to optimize the electric field distribution inside traditional power MOSFETs, thereby reducing gate-drain charge, on-resistance, and switching losses. As the trench depth increases, the electric field in the longitudinal center of the shielded gate structure significantly dips, leading to a decrease in breakdown voltage. Shielded gate structures are mainly used in low-voltage devices.

[0004] Therefore, in low-voltage devices, how to provide a manufacturing method that can reduce on-resistance, increase breakdown voltage, and combine the advantages of superjunction structure and shielded gate structure is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides a method for manufacturing a field-effect transistor and a field-effect transistor to solve the problems mentioned above, such as the inability to introduce superjunction structures into low-voltage devices, the inability to combine them with shielded gate structures, and the inability to properly balance on-resistance and breakdown voltage.

[0006] In a first aspect, the present invention provides a method for manufacturing a field-effect transistor, comprising: A substrate is provided, comprising a front side and a back side disposed opposite to each other, wherein a first conductivity type semiconductor drift region is generated on the front side of the substrate; A first trench is formed in the drift region of the first conductivity type semiconductor, and a second trench is formed based on the first trench; A first oxide layer is formed in the second trench, and the first oxide layer is anisotropically etched. Ion implantation is performed on the etched second trench to form a superjunction-like column region. Remove the first oxide layer, and perform thermal oxidation growth or deposition on the second trench to form a second oxide layer; Polysilicon is deposited on the second oxide layer to form a shielded gate polysilicon electrode, and the second oxide layer encapsulates the shielded gate polysilicon electrode. A gate structure is formed within the drift region of the semiconductor of the first conductivity type; Ion implantation, passivation, and photolithography are performed on the side of the first conductivity type semiconductor drift region away from the substrate to form a semiconductor body region, and a portion of the semiconductor body region is located on the side of the gate structure away from the substrate. A source metal layer is formed by depositing metal on the side of the semiconductor body region away from the substrate, and the source metal layer covers the semiconductor body region. Metal is deposited on the back side of the substrate to form a drain metal layer.

[0007] In one embodiment of the present invention, forming a first trench within a first conductivity type semiconductor drift region and forming a second trench based on the first trench includes: performing a masking process on the first conductivity type semiconductor drift region to generate a first mask layer; coating, exposing, and developing the first mask layer to determine the location of the first trench; etching the first conductivity type semiconductor drift region to form the first trench; performing a masking process on the first conductivity type semiconductor drift region to generate a second mask layer; coating, exposing, and developing the second mask layer to determine the location of the second trench; and etching the first conductivity type semiconductor drift region to form the second trench.

[0008] In one embodiment of the present invention, the first oxide layer is anisotropically etched, and the etched second trench is ion implanted to form a superjunction-like pillar region. The method includes: etching a portion of the first oxide layer in the second trench to determine the ion implantation region; using the remaining first oxide layer as a mask, ion implanting is performed on the ion implantation region to form a superjunction-like pillar region within the first conductivity type semiconductor drift region.

[0009] In a second aspect, the present invention also provides a field-effect transistor, which is manufactured based on the manufacturing method of a field-effect transistor as described above, comprising: A substrate, comprising a front side and a back side disposed opposite to each other; A first conductivity type semiconductor drift region is disposed on the front side of the substrate; A superjunction-type pillar region is disposed within the drift region of the first conductivity type semiconductor. The second oxide layer is disposed within the first conductivity type semiconductor drift region, and the second oxide layer is located on the side of the superjunction-like pillar region away from the substrate, and part of the second oxide layer is wrapped by the superjunction-like pillar region; A shielding gate polysilicon electrode is disposed within the drift region of the first conductivity type semiconductor, and the second oxide layer encapsulates the shielding gate polysilicon electrode. A gate structure disposed within the drift region of the first conductivity type semiconductor; A semiconductor body region is disposed on the side of the first conductivity type semiconductor drift region away from the substrate, and a portion of the semiconductor body region is located on the side of the gate structure away from the substrate; A source metal layer is disposed on the side of the semiconductor body region opposite to the substrate; A drain metal layer is disposed on the back side of the substrate.

[0010] In one embodiment of the present invention, the second oxide layer is isolated from the first conductivity type semiconductor drift region in the horizontal direction through the superjunction-like pillar region; in the horizontal direction, the shielding gate polysilicon electrode is isolated from the superjunction-like pillar region and the first conductivity type semiconductor drift region respectively through the second oxide layer, wherein the horizontal direction is a direction parallel to the substrate.

[0011] In one embodiment of the present invention, the semiconductor body region includes: a second conductivity type semiconductor region disposed on the side of the first conductivity type semiconductor drift region away from the substrate; a first conductivity type semiconductor source region disposed on the side of the second conductivity type semiconductor region away from the substrate; a second conductivity type semiconductor ohmic contact region disposed within the second conductivity type semiconductor region and the first conductivity type semiconductor source region, wherein a portion of the second conductivity type semiconductor ohmic contact region is located between the second conductivity type semiconductor regions and a portion is located between the first conductivity type semiconductor source regions in the horizontal direction; and a gate-source dielectric layer disposed on the side of the first conductivity type semiconductor source region away from the substrate, wherein the gate-source dielectric layer covers the first conductivity type semiconductor source region and a portion of the second oxide layer, and the gate-source dielectric layer is located on the side of the gate structure away from the substrate.

[0012] In one embodiment of the present invention, a portion of the source metal layer is located between the ohmic contact regions of the second conductivity type semiconductor, a portion is located between the source regions of the first conductivity type semiconductor, and a portion is located between the gate-source dielectric layers in the horizontal direction.

[0013] In one embodiment of the present invention, the gate structure includes: a third oxide layer disposed within the first conductivity type semiconductor drift region, wherein the third oxide layer is isolated from the second oxide layer in the horizontal direction by the second conductivity type semiconductor region, the first conductivity type semiconductor source region, the second conductivity type semiconductor ohmic contact region and the source metal layer; and a gate polysilicon electrode disposed on the side of the third oxide layer away from the substrate, wherein the third oxide layer encapsulates the gate polysilicon electrode.

[0014] In one embodiment of the present invention, the gate structure includes: a gate polysilicon electrode disposed on the side of the second oxide layer away from the substrate, and the second oxide layer encapsulates the gate polysilicon electrode; the gate structure is isolated from the second conductivity type semiconductor region and the first conductivity type semiconductor source region respectively in the horizontal direction through the second oxide layer.

[0015] The beneficial effects of this invention: This invention provides a method for manufacturing a field-effect transistor (FET) and the FET itself. The method includes: forming a first trench in a first conductivity type semiconductor drift region; forming a second trench in the first trench; anisotropically etching a first oxide layer formed in the second trench; ion implantation into the etched second trench to form a superjunction-like pillar region; and forming a shielding gate polysilicon electrode within the second trench. The FET manufacturing method provided in this application integrates a superjunction structure and a shielding gate structure within the same FET, giving the FET the advantages of both superjunction and shielding gate structures. It significantly reduces on-resistance, increases breakdown voltage, overcomes the limitations of ion diffusion in traditional superjunction processes, controls the formation width of the superjunction structure, and simplifies the process implementation. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram: Figure 1 This is a flowchart of a method for manufacturing a field-effect transistor according to an embodiment of the present invention; Figures 2-13 This is a cross-sectional schematic diagram of a method for manufacturing a field-effect transistor according to an embodiment of the present invention; Figure 14 This is a cross-sectional schematic diagram of a field-effect transistor provided in another embodiment of the present invention.

[0018] Reference numerals: 1-Drain metal layer; 2-Substrate; 3-First conductivity type semiconductor drift region; 4-First oxide layer; 5-Superjunction type pillar region; 6-Second oxide layer; 7-Shielding gate polysilicon electrode; 8-Third oxide layer; 9-Gate polysilicon electrode; 10-Second conductivity type semiconductor region; 11-First conductivity type semiconductor source region; 12-Gate-source dielectric layer; 13-Second conductivity type semiconductor ohmic contact region; 14-Source metal layer. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0020] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0022] As described in the background section, metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in various power systems due to their advantages such as fast switching speed, low power consumption, easy gate driving, low driving power, high input impedance, and fast frequency response.

[0023] In practical applications, superjunction structures are used to break the "silicon limit" of traditional power MOSFETs, forming devices with high voltage withstand, low on-resistance, and fast switching speed. However, due to limitations in aspect ratio and ion diffusion effects during the manufacturing process, superjunction structures are primarily used in high-voltage devices. Shielded gate structures are used to optimize the electric field distribution inside traditional power MOSFETs, thereby reducing gate-drain charge, on-resistance, and switching losses. As the trench depth increases, the electric field in the longitudinal center of the shielded gate structure significantly dips, leading to a decrease in breakdown voltage. Shielded gate structures are mainly used in low-voltage devices.

[0024] Firstly, such as Figure 1 As shown, this application provides a method for manufacturing a field-effect transistor, which includes at least steps S1 to S9: S1. A substrate 2 is provided, which includes a front side and a back side disposed opposite to each other, and a first conductivity type semiconductor drift region 3 is formed on the front side of the substrate 2.

[0025] Specifically, such as Figure 2 As shown, a substrate 2 is provided, which includes a front side and a back side disposed opposite to each other. Thermal oxidation growth, photoresist coating, ion implantation and annealing are performed sequentially on the front side of the substrate 2 to form a first conductivity type semiconductor drift region 3 on the front side of the substrate 2.

[0026] S2. A first trench is formed in the first conductivity type semiconductor drift region 3, and a second trench is formed based on the first trench.

[0027] Specifically, forming a first trench within a first conductivity type semiconductor drift region 3, and forming a second trench based on the first trench, includes: applying a mask on the first conductivity type semiconductor drift region 3 to generate a first mask layer; coating, exposing, and developing the first mask layer to determine the location of the first trench; etching the first conductivity type semiconductor drift region 3 to form the first trench; applying a mask on the first conductivity type semiconductor drift region 3 to generate a second mask layer; coating, exposing, and developing the second mask layer to determine the location of the second trench; and etching the first conductivity type semiconductor drift region 3 to form the second trench.

[0028] Specifically, a mask is applied to the side of the first conductivity type semiconductor drift region 3 facing away from the substrate 2 to form a first mask layer. The first mask layer is then subjected to coating, exposure, and development processes, revealing the position of the first trench on the first mask layer, thereby determining the position of the first trench at the top of the first conductivity type semiconductor drift region 3. Using the first mask layer as a mask, the first conductivity type semiconductor drift region 3 is etched, and after etching, the first mask layer is removed. Figure 3As shown, a first trench is formed in a first conductivity type semiconductor drift region 3. A mask is applied to the first conductivity type semiconductor drift region 3 with the first trench, and a second mask layer is formed on the side of the first conductivity type semiconductor drift region 3 facing away from the substrate 2. The second mask layer is subjected to coating, exposure, and development processes in sequence, revealing the position of the second trench on the second mask layer, thereby determining the position of the second trench at the top of the first conductivity type semiconductor drift region 3. Using the second mask layer as a mask, the first conductivity type semiconductor drift region 3 under the second mask layer is etched. After etching, the second mask layer is removed, and based on the first trench, as shown... Figure 4 As shown, a second trench is formed within the first conductivity type semiconductor drift region 3; wherein, a trench step is provided between the bottom and top of the second trench, as shown. Figure 4 As shown by the dashed line.

[0029] S3. A first oxide layer 4 is formed in the second trench, and the first oxide layer 4 is anisotropically etched. Ion implantation is performed on the etched second trench to form a superjunction-like column region 5.

[0030] Specifically, such as Figure 5 As shown, the second trench is subjected to oxidative growth, and a first oxide layer 4 is formed at the bottom of the second trench, the trench steps and the sidewalls.

[0031] In detail, the first oxide layer 4 is anisotropically etched, and the etched second trench is ion implanted to form a superjunction-like pillar region 5. This includes: etching a portion of the first oxide layer 4 in the second trench to determine the ion implantation area; using the remaining first oxide layer 4 as a mask, ion implantation is performed on the ion implantation area to form a superjunction-like pillar region 5 within the first conductivity type semiconductor drift region 3.

[0032] Specifically, such as Figure 6 As shown, a portion of the first oxide layer 4 on the top sidewall of the second trench and the first oxide layer 4 on the bottom of the trench and the trench steps are etched to determine the ion implantation region as the bottom of the trench and the trench steps, as shown. Figure 6 As shown, the remaining first oxide layer 4 in the second trench is used as a mask to perform ion implantation on the bottom and steps of the trench. By controlling the energy, dose, and number of ion implantations, the device achieves a high breakdown voltage and a low on-resistance. The ion implantation concentration range is [1×10]. 11 cm -2 5×10 13 cm -2During ion implantation, a portion of the first conductivity type semiconductor drift region 3 is shielded by the first oxide layer 4 and is almost unaffected by ion implantation. The actual area undergoing ion implantation is the exposed silicon region. A superjunction-like pillar region 5 is formed within the first conductivity type semiconductor drift region 3 between the two trench steps and the bottom of the trench, and below the bottom of the trench. Figure 7 As shown, the structure formed by the superjunction column region 5 is a superjunction structure.

[0033] S4. Remove the first oxide layer 4, and perform thermal oxidation growth or deposition on the second trench to form the second oxide layer 6.

[0034] Specifically, after forming the superjunction-like column region 5, the first oxide layer 4 is removed by chemically reacting with the etching solution. Then, thermal oxidation growth or deposition occurs at the bottom, steps, and sidewalls of the second trench, such as... Figure 7 As shown, a second oxide layer 6 is formed in the second trench. The etching solution includes buffered oxide etching solution, dilute hydrofluoric acid solution, etc. The first oxide layer 4 can also be removed by dry etching and / or chemical mechanical polishing.

[0035] S5. Polycrystalline silicon is deposited on the second oxide layer 6 to form a shielded gate polycrystalline silicon electrode 7, and the second oxide layer 6 encapsulates the shielded gate polycrystalline silicon electrode 7.

[0036] Specifically, such as Figure 8 As shown, polysilicon is deposited on the second oxide layer 6 to form a shielding gate polysilicon electrode 7 in the second trench. Then, thermal oxidation growth or deposition is performed on the shielding gate polysilicon electrode 7 to form the second oxide layer 6, which encapsulates the shielding gate polysilicon electrode 7.

[0037] S6. A gate structure is formed in the first conductivity type semiconductor drift region 3.

[0038] Specifically, when the gate structure includes a third oxide layer 8 and a gate polysilicon electrode 9, the gate structure is formed in the following manner: Figure 8 As shown, the two sides of the first conductivity type semiconductor drift region 3 are etched to form two third trenches on both sides of the first conductivity type semiconductor drift region 3. Thermal oxidation growth is performed in the two third trenches to form a third oxide layer 8 on the sidewalls and bottom of the two third trenches. Polysilicon deposition is performed on the third oxide layer 8 in the third trenches to form gate polysilicon electrodes 9 in the two third trenches. Then, thermal oxidation growth is performed on the gate polysilicon electrodes 9 to form the third oxide layer 8, thereby making the third oxide layer 8 encapsulate the gate polysilicon electrodes 9.

[0039] When the gate structure only includes the gate polysilicon electrode 9, the gate structure is formed by depositing polysilicon on the side of the second oxide layer 6 away from the shielding gate polysilicon electrode 7 to form the gate polysilicon electrode 9, and then thermally oxidizing the side of the gate polysilicon electrode 9 away from the shielding gate polysilicon electrode 7 so that the second oxide layer 6 encapsulates the gate polysilicon electrode 9.

[0040] S7. Ion implantation, passivation and photolithography are performed on the side of the first conductivity type semiconductor drift region 3 away from the substrate 2 to form a semiconductor body region, and part of the semiconductor body region is located on the side of the gate structure away from the substrate 2.

[0041] Specifically, the semiconductor body region includes a second conductivity type semiconductor region 10, a first conductivity type semiconductor source region 11, a gate-source dielectric layer 12, and a second conductivity type semiconductor ohmic contact region 13.

[0042] like Figure 9 As shown, ion implantation and push-bonding are performed on the first conductivity type semiconductor drift region 3 to form the second conductivity type semiconductor region 10. The second conductivity type semiconductor region 10 is located at the top of the first conductivity type semiconductor drift region 3 in the vertical direction and on both sides of the second oxide layer 6 in the horizontal direction. The vertical direction is perpendicular to the substrate 2 and the horizontal direction is parallel to the substrate 2.

[0043] like Figure 10 As shown, ion implantation and push-junction are performed on the second conductivity type semiconductor region 10 to form a first conductivity type semiconductor source region 11. The first conductivity type semiconductor source region 11 is located on the side of the second conductivity type semiconductor region 10 away from the substrate 2. In the horizontal direction, the first conductivity type semiconductor source region 11 is located on both sides of the second oxide layer 6.

[0044] like Figure 11 As shown, a passivation process is performed on the side of the first conductivity type semiconductor source region 11 away from the substrate 2 to form a gate-source dielectric layer 12. The gate-source dielectric layer 12 covers a portion of the second oxide layer 6 and the first conductivity type semiconductor source region 11. When the gate structure is located on both sides of the first conductivity type semiconductor drift region 3, the gate-source dielectric layer 12 covers a portion of the second oxide layer 6, a portion of the third oxide layer 8, and the first conductivity type semiconductor source region 11.

[0045] like Figure 12 As shown, photolithography is performed on the gate-source dielectric layer 12, and the bottom of the etched trench is located within the first conductivity type semiconductor source region 11, forming two fourth trenches. In the horizontal direction, part of the fourth trench is between the gate-source dielectric layer 12 and part is between the first conductivity type semiconductor source regions 11.

[0046] like Figure 12As shown, ion implantation is performed on the two fourth trenches respectively. Part of the ions are implanted into the second conductivity type semiconductor region 10 and part of the ions are implanted into the first conductivity type semiconductor source region 11, forming a second conductivity type semiconductor ohmic contact region 13 between the contact surface of the second conductivity type semiconductor region 10 and the first conductivity type semiconductor source region 11.

[0047] S8. Metal is deposited on the side of the semiconductor body region away from the substrate 2 to form a source metal layer 14, and the source metal layer 14 covers the semiconductor body region.

[0048] Specifically, such as Figure 13 As shown, a source metal layer 14 is formed by metal deposition on the gate-source dielectric layer 12, as follows: Figure 13 As shown, the source metal layer 14 fills two fourth trenches and covers the gate-source dielectric layer 12, part of the second conductivity type semiconductor ohmic contact region 13 and part of the first conductivity type semiconductor source region 11.

[0049] S9, such as Figure 13 As shown, metal is deposited on the back side of substrate 2 to form drain metal layer 1.

[0050] Secondly, such as Figure 13 and Figure 14 As shown, this application also provides a field-effect transistor, which is fabricated based on the field-effect transistor manufacturing method described above, comprising: Substrate 2, which includes a front side and a back side disposed opposite to each other; The first conductivity type semiconductor drift region 3 is disposed on the front side of the substrate 2; Superjunction-type pillar region 5 is disposed within the first conductivity type semiconductor drift region 3; The second oxide layer 6 is disposed within the first conductivity type semiconductor drift region 3, and the second oxide layer 6 is located on the side of the superjunction pillar region 5 away from the substrate 2, and part of the second oxide layer 6 is wrapped by the superjunction pillar region 5. The shielding gate polysilicon electrode 7 is disposed within the first conductivity type semiconductor drift region 3, and the second oxide layer 6 encapsulates the shielding gate polysilicon electrode 7. A gate structure is disposed within a first conductivity type semiconductor drift region 3; The semiconductor body region is disposed on the side of the first conductivity type semiconductor drift region 3 away from the substrate 2, and a portion of the semiconductor body region is located on the side of the gate structure away from the substrate 2. The source metal layer 14 is disposed on the side of the semiconductor bulk region away from the substrate 2; Drain metal layer 1 is disposed on the back side of substrate 2.

[0051] Specifically, the second oxide layer 6 is horizontally isolated from the first conductivity type semiconductor drift region 3 via the superjunction-like pillar region 5; in the horizontal direction, the shielding gate polysilicon electrode 7 is isolated from both the superjunction-like pillar region 5 and the first conductivity type semiconductor drift region 3 via the second oxide layer 6, wherein the horizontal direction is parallel to the substrate 2. Specifically, as... Figure 13 and Figure 14 As shown, the superjunction-like pillar region 5 is U-shaped, partially encapsulating the second oxide layer 6. In a horizontal direction parallel to the substrate 2, the superjunction-like pillar region 5 isolates the second oxide layer 6 from the first conductivity type semiconductor drift region 3. Figure 13 and Figure 14 As shown, in the horizontal direction parallel to the substrate 2, a portion of the shielded gate polysilicon electrode 7 is isolated from the superjunction-like pillar region 5 based on the second oxide layer 6, and a portion of the shielded gate polysilicon electrode 7 is isolated from the first conductivity type semiconductor drift region 3 through the second oxide layer 6.

[0052] Specifically, the semiconductor body region includes: a second conductivity type semiconductor region 10, disposed on the side of the first conductivity type semiconductor drift region 3 away from the substrate 2; a first conductivity type semiconductor source region 11, disposed on the side of the second conductivity type semiconductor region 10 away from the substrate 2; a second conductivity type semiconductor ohmic contact region 13, disposed within the second conductivity type semiconductor region 10 and the first conductivity type semiconductor source region 11, wherein a portion of the second conductivity type semiconductor ohmic contact region 13 is located between the second conductivity type semiconductor regions 10 and a portion is located between the first conductivity type semiconductor source region 11 in the horizontal direction; and a gate-source dielectric layer 12, disposed on the side of the first conductivity type semiconductor source region 11 away from the substrate 2, and the gate-source dielectric layer 12 covers the first conductivity type semiconductor source region 11 and a portion of the second oxide layer 6, and the gate-source dielectric layer 12 is located on the side of the gate structure away from the substrate 2. Specifically, as shown... Figure 13 and Figure 14 As shown, the semiconductor body region includes a second conductivity type semiconductor region 10, a first conductivity type semiconductor source region 11, a gate-source dielectric layer 12, and a second conductivity type semiconductor ohmic contact region 13. The second conductivity type semiconductor region 10 is located on the first conductivity type semiconductor drift region 3. The first conductivity type semiconductor source region 11 is located on the side of the second conductivity type semiconductor region 10 away from the substrate 2. A portion of the second conductivity type semiconductor ohmic contact region 13 is located within the second conductivity type semiconductor region 10, and a portion of the second conductivity type semiconductor ohmic contact region 13 is located within the first conductivity type semiconductor source region 11. The second conductivity type semiconductor ohmic contact region 13 is located between the contact surfaces of the second conductivity type semiconductor region 10 and the first conductivity type semiconductor source region 11. The gate-source dielectric layer 12 is located on the side of the first conductivity type semiconductor source region 11 away from the second conductivity type semiconductor region 10. The gate-source dielectric layer 12 covers the first conductivity type semiconductor source region 11 and a portion of the second oxide layer 6.

[0053] Specifically, the source metal layer 14 is partially located between the second conductivity type semiconductor ohmic contact regions 13, partially located between the first conductivity type semiconductor source regions 11, and partially located between the gate-source dielectric layer 12 in the horizontal direction. For example... Figure 13 and 14 As shown, the source metal layer 14, in a direction parallel to the substrate 2, from bottom to top, is partially located within the second conductivity type semiconductor ohmic contact region 13, partially located between the first conductivity type semiconductor source regions 11, and partially located between the gate-source dielectric layers 12.

[0054] In detail, the gate structure includes: a third oxide layer 8 disposed within the first conductivity type semiconductor drift region 3, and the third oxide layer 8 being isolated from the second oxide layer 6 in the horizontal direction through the second conductivity type semiconductor region 10, the first conductivity type semiconductor source region 11, the second conductivity type semiconductor ohmic contact region 13, and the source metal layer 14; and a gate polysilicon electrode 9 disposed on the side of the third oxide layer 3 facing away from the substrate 2, and the third oxide layer 8 encapsulating the gate polysilicon electrode 9. Specifically, as shown in Figure 13, the gate structure includes a third oxide layer 8 and a gate polysilicon electrode 9. The third oxide layer 8 is located within the first conductivity type semiconductor drift region 3. In a direction parallel to the substrate 2, the third oxide layer 3 contacts the second conductivity type semiconductor region 10 and the first conductivity type semiconductor source region 11. The second oxide layer 6 contacts the second conductivity type semiconductor region 10 and the first conductivity type semiconductor source region 11. A source metal layer 14 is disposed in the fourth trench between the second conductivity type semiconductor region 10 and the first conductivity type semiconductor source region 11. A second conductivity type semiconductor ohmic contact region 13 is disposed below the fourth trench. The gate polysilicon electrode 9 is located on the third oxide layer 8, and the third oxide layer 8 encapsulates the gate polysilicon electrode 9.

[0055] Specifically, the gate structure includes: a gate polysilicon electrode 9 disposed on the side of the second oxide layer 6 facing away from the substrate 2, and the second oxide layer 6 encapsulating the gate polysilicon electrode. The gate structure is horizontally isolated from the second conductivity type semiconductor region 10 and the first conductivity type semiconductor source region 11 by the second oxide layer 6, respectively. Specifically, as... Figure 14 As shown, the gate structure includes a gate polysilicon electrode 9, which is located on the side of the shielding gate polysilicon electrode 7 away from the substrate 2. The gate polysilicon electrode 9 and the shielding gate polysilicon electrode 7 are isolated by a second oxide layer 6. In a direction parallel to the substrate 2, the gate polysilicon electrode 9 is isolated from the second conductivity type semiconductor region 10 by the second oxide layer 6, and the gate polysilicon electrode 9 is isolated from the first conductivity type semiconductor source region 11 by the second oxide layer 6.

[0056] It needs to be emphasized that, Figure 13 The provided field-effect transistors and Figure 14 The difference between the provided field-effect transistors lies in the location of the gate structure.

[0057] This invention provides a method for manufacturing a field-effect transistor (FET) and the FET itself. The method includes: forming a second trench in a first conductivity type semiconductor drift region; etching a portion of a second oxide layer in the second trench to form an ion implantation region; defining the ion implantation region during the formation of a superjunction-like pillar region; and forming a shielding gate polysilicon electrode within the second trench. The FET manufacturing method provided in this application integrates a superjunction structure and a shielding gate structure within the same FET, giving the FET the advantages of both superjunction and shielding gate structures. This significantly reduces on-resistance, increases breakdown voltage, overcomes the limitations of ion diffusion in traditional superjunction processes, controls the formation width of the superjunction structure, and simplifies the process implementation.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of manufacturing a field effect transistor, characterized by, include: A substrate is provided, comprising a front side and a back side disposed opposite to each other, wherein a first conductivity type semiconductor drift region is generated on the front side of the substrate; A first trench is formed in the drift region of the first conductivity type semiconductor, and a second trench is formed based on the first trench; A first oxide layer is formed in the second trench, and the first oxide layer is anisotropically etched. Ion implantation is performed on the etched second trench to form a superjunction-like column region. Remove the first oxide layer, and perform thermal oxidation growth or deposition on the second trench to form a second oxide layer; Polysilicon is deposited on the second oxide layer to form a shielded gate polysilicon electrode, and the second oxide layer encapsulates the shielded gate polysilicon electrode. A gate structure is formed within the drift region of the semiconductor of the first conductivity type; Ion implantation, passivation, and photolithography are performed on the side of the first conductivity type semiconductor drift region away from the substrate to form a semiconductor body region, and a portion of the semiconductor body region is located on the side of the gate structure away from the substrate. A source metal layer is formed by depositing metal on the side of the semiconductor body region away from the substrate, and the source metal layer covers the semiconductor body region. Metal is deposited on the back side of the substrate to form a drain metal layer.

2. The method of manufacturing a field effect transistor according to claim 1, wherein Forming a first trench within the drift region of the first conductivity type semiconductor, and forming a second trench based on the first trench, including: A mask is applied to the drift region of the first conductivity type semiconductor to generate a first mask layer; The first mask layer is coated, exposed, and developed to determine the position of the first trench. The first conductivity type semiconductor drift region is etched to form the first trench; A mask is applied to the first conductivity type semiconductor drift region to generate a second mask layer; The second mask layer is coated, exposed, and developed to determine the position of the second trench; The first type of conductivity semiconductor drift region is etched to form the second trench.

3. The method of manufacturing a field effect transistor according to claim 1, wherein The first oxide layer is anisotropically etched, and the etched second trench is ion implanted to form a superjunction-like pillar region, including: Etch a portion of the first oxide layer in the second trench to define the ion implantation region; Using the remaining first oxide layer as a mask, ion implantation is performed on the ion implantation region to form a superjunction-like pillar region within the first conductivity type semiconductor drift region.

4. A field effect transistor, characterized by The field-effect transistor is manufactured based on the manufacturing method of the field-effect transistor according to any one of claims 1-3, comprising: A substrate, comprising a front side and a back side disposed opposite to each other; A first conductivity type semiconductor drift region is disposed on the front side of the substrate; A superjunction-type pillar region is disposed within the drift region of the first conductivity type semiconductor. The second oxide layer is disposed within the first conductivity type semiconductor drift region, and the second oxide layer is located on the side of the superjunction-like pillar region away from the substrate, and part of the second oxide layer is wrapped by the superjunction-like pillar region; A shielding gate polysilicon electrode is disposed within the drift region of the first conductivity type semiconductor, and the second oxide layer encapsulates the shielding gate polysilicon electrode; A gate structure disposed within the drift region of the first conductivity type semiconductor; A semiconductor body region is disposed on the side of the first conductivity type semiconductor drift region away from the substrate, and a portion of the semiconductor body region is located on the side of the gate structure away from the substrate; A source metal layer is disposed on the side of the semiconductor body region opposite to the substrate; A drain metal layer is disposed on the back side of the substrate.

5. The field effect transistor of claim 4, wherein, The second oxide layer is horizontally isolated from the first conductivity type semiconductor drift region through the superjunction-like pillar region; in the horizontal direction, the shielding gate polysilicon electrode is isolated from the superjunction-like pillar region and the first conductivity type semiconductor drift region respectively through the second oxide layer, wherein the horizontal direction is a direction parallel to the substrate.

6. The field effect transistor of claim 5, wherein, The semiconductor body region includes: A second conductivity type semiconductor region is disposed on the side of the first conductivity type semiconductor drift region away from the substrate; A first conductivity type semiconductor source region is disposed on the side of the second conductivity type semiconductor region away from the substrate; A second type of conductive semiconductor ohmic contact region is disposed within the second type of conductive semiconductor region and the first type of conductive semiconductor source region. In the horizontal direction, a portion of the second type of conductive semiconductor ohmic contact region is located between the second type of conductive semiconductor region and a portion is located between the first type of conductive semiconductor source region. A gate-source dielectric layer is disposed on the side of the first conductivity type semiconductor source region away from the substrate, and the gate-source dielectric layer covers the first conductivity type semiconductor source region and part of the second oxide layer, and the gate-source dielectric layer is located on the side of the gate structure away from the substrate.

7. The field effect transistor of claim 6, wherein The source metal layer is located in the horizontal direction, with a portion between the ohmic contact regions of the second type of conductivity semiconductor, a portion between the source regions of the first type of conductivity semiconductor, and a portion between the gate-source dielectric layers.

8. The field effect transistor of claim 7, wherein, The gate structure includes: A third oxide layer is disposed within the first conductivity type semiconductor drift region, and the third oxide layer is isolated from the second oxide layer in the horizontal direction by the second conductivity type semiconductor region, the first conductivity type semiconductor source region, the second conductivity type semiconductor ohmic contact region and the source metal layer; A gate polysilicon electrode is disposed on the side of the third oxide layer away from the substrate, and the third oxide layer encapsulates the gate polysilicon electrode.

9. The field effect transistor of claim 7, wherein, The gate structure includes: A gate polysilicon electrode is disposed on the side of the second oxide layer away from the substrate, and the second oxide layer encapsulates the gate polysilicon electrode. The gate structure is isolated from the second conductivity type semiconductor region and the first conductivity type semiconductor source region in the horizontal direction by the second oxide layer.

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