Thin film transistor, array substrate and display panel

Abstract

The application discloses a thin film transistor, an array substrate and a display panel, and belongs to the technical field of display. The thin film transistor comprises a light shielding layer, an active layer, a gate and a source-drain electrode. The light shielding layer and the active layer have an intersection area in the orthographic projection on the surface of a substrate. The active layer comprises an extension part located in the intersection area and a main part connected with the extension part. The width of the extension part is greater than the width of the main part. The array substrate comprises a substrate with an array area and a peripheral area. The thin film transistor is arranged on the substrate and located in the array area. The display panel comprises the array substrate. The extension part with the obviously enlarged width is arranged on the main part of the active layer and located in the intersection area, which is beneficial to the smooth progress of the subsequent crystallization process, avoids the crystallization deterioration problem and significantly increases the cross-sectional size of the carrier channel in the active layer in the edge climbing area of the light shielding layer, thereby improving the problem of the electron mobility reduction caused by the thinning of the active layer in the climbing area.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a thin-film transistor, an array substrate, and a display panel. Background Technology

[0002] With the trend towards high-end display panels, the market demand for high-resolution and high-refresh-rate display products is constantly increasing. This requires that the metal signal lines in the display panel adopt a low-impedance design, and that the thickness and effective width of the metal signal lines be as high as possible, while ensuring that the cost does not increase significantly.

[0003] To address these requirements, existing technologies typically employ methods such as increasing the thickness of the metal signal line film or using multilayered metals like molybdenum-aluminum (Mo-Al) or molybdenum-aluminum-molybdenum (Mo-Al-Mo) to achieve low impedance design. This leads to a continuous increase in the thickness of the metal signal line film, increasing the complexity of the manufacturing process. For liquid crystal displays (LCDs), in the Low Temperature Polycrystalline Silicon (LTPS) process, when a light shield (LS) is used as the lower metal signal line in the thin-film transistor of the driving circuit, if the LS adopts a semi-enclosed design, the upper active layer in the region at the edge of the LS will experience a significant ramping phenomenon due to the low impedance design of the metal signal line (i.e., increased film thickness). This results in a thinner film thickness in the ramping region of the active layer, which not only leads to crystallization deterioration in subsequent crystallization processes but also significantly reduces the cross-sectional area of ​​the active layer in the ramping region, narrowing the carrier pathway and reducing carrier mobility.

[0004] To address the aforementioned issues, existing technologies urgently need improvement. Summary of the Invention

[0005] This application provides a thin-film transistor, an array substrate, and a display panel. By providing an extended portion with a significantly increased width located in the junction region on the main body of the active layer, the subsequent crystallization process is facilitated, avoiding crystallization deterioration problems. Furthermore, it significantly increases the cross-sectional size of the carrier channel in the ramp region at the edge of the light-shielding layer of the active layer, improving the problem of decreased electron mobility caused by thinning in the ramp region of the active layer, thereby at least partially solving the aforementioned technical problems.

[0006] To achieve the above objectives, according to a first aspect of this application, a thin-film transistor is provided, the thin-film transistor being disposed on a substrate, the thin-film transistor including a light-shielding layer, an active layer, a gate, and source / drain electrodes patterned along the thickness direction of the thin-film transistor; In the orthographic projection of the light-shielding layer and the active layer onto the substrate surface, the active layer and the light-shielding layer have an interface area. The active layer includes: An extension portion is located within the junction area; and, The main body connects to the extension part; The width of the extension portion is greater than the width of the main body portion.

[0007] Optionally, the main body extends at least along a first direction, and the extension is disposed on the main body and arranged opposite to it at least along the first direction; Wherein, the light-shielding layer extends along the second direction and along the thickness direction of the thin-film transistor, the light-shielding layer intersects with the main body layer between the oppositely arranged extension portions; the first direction intersects with the second direction.

[0008] Optionally, the active layer includes: A channel portion is disposed on the main body portion and located between the oppositely arranged extension portions; the orthographic projection of the channel portion on the base portion is located within the junction area; The doped regions are connected to both ends of the channel portion and are arranged opposite to each other along the first direction; The doped region is at least partially disposed on the main body and at least partially disposed on the extension.

[0009] Optionally, along the first direction, the extension portion at least partially extends beyond the edge of the light-shielding layer; Along the second direction, the extension extends at least partially beyond the edge of the main body.

[0010] Optionally, the extension includes at least one shape selected from circles, ellipses, polygons, and irregular shapes.

[0011] Optionally, within the junction area, the area of ​​the overlapping region between the extension and the light-shielding layer is S2, and the area of ​​the extension is S1. The relationship between S2 and S1 satisfies: 1 / 5×S1≤S2≤4 / 5×S1.

[0012] Optionally, along the second direction, the edge of the light-shielding layer is an outer arc-shaped edge, an inner arc-shaped edge, or a toothed edge, wherein the edge structures on both sides of the light-shielding layer are the same or different.

[0013] According to a second aspect of this application, an array substrate is provided, the array substrate comprising: The substrate has an array region and a peripheral region adjacent to the array region; A thin-film transistor, including any one of the thin-film transistors described above, wherein the thin-film transistor array is disposed on the substrate and located within the array region.

[0014] Optionally, the array substrate further includes: Metal traces are arranged on the substrate and located within the peripheral area, the metal traces comprising: The first metal trace includes a first sub-line, a second sub-line, and a third sub-line patterned along the thickness direction of the thin-film transistor. The first sub-line is located in the same metal layer as the light-shielding layer, the second sub-line is located in the same metal layer as the gate, and the third sub-line is located in the same metal layer as the source and drain. The third sub-line of the same first metal trace bridges the second sub-line and the first sub-line.

[0015] According to a third aspect of this application, a display panel is also provided, the display panel comprising the array substrate described in any one of the preceding claims.

[0016] In the thin-film transistor of this application embodiment, the above technical solution provides an extended portion with a significantly increased width located in the junction region on the main body of the active layer. This facilitates the smooth progress of the subsequent crystallization process, avoids crystallization deterioration problems, and significantly increases the cross-sectional size of the carrier channel in the ramp region at the edge of the light-shielding layer of the active layer. This improves the problem of decreased electron mobility caused by thinning of the ramp region of the active layer, helps to reduce the leakage current of the active layer, ensures the realization of the device electrical performance of the thin-film transistor, and is beneficial to the high resolution, high refresh rate and low power consumption design of the display panel.

[0017] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 This is a partial cross-sectional view of the array substrate provided in an exemplary embodiment of this disclosure; Figures 2a-2eThis is a top view of the active layer and the light-shielding layer of the thin-film transistor provided in an exemplary embodiment of this disclosure; Figure 3 This is a schematic cross-sectional view of a partial structure of the peripheral region of an array substrate provided in an exemplary embodiment of this disclosure.

[0021] Explanation of reference numerals in the attached figures: 100 - Array substrate; 10 - Substrate; 101 - Array region; 102 - Peripheral region; 1021 - Wiring region; 1022 - Switching region; 103 - Interchange region; T - Thin film transistor; 104 - Source via; 105 - Drain via; 106 - First via; 107 - Second via; 11 - Light-shielding layer; 111 - Sidewall; 12 - Buffer layer; 13-Active layer; 131-Main body; 132-Extension; 133-Channel; 134-Doped region; 1341-Lightly doped region; 1342-Heavily doped source region; 1343-Heavily doped drain region; 135-Connection; 136-Electrode portion of heavily doped source region; 137-Electrode portion of heavily doped drain region; 14-Gate insulating layer; 15-Gate; 16-Interlayer dielectric layer; 17-Source / drain; 171-Source; 172-Drain; 18-Planing layer; 19-Common electrode; 20-Insulating layer; 21-Pixel electrode; 3-Metallic trace; 31-First metal trace; 311-First sub-trace; 311c-First sub-trace C; Second sub-trace 312; 312b-Second sub-trace B; 313-Third sub-trace; 313a-Third sub-trace A. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0023] To facilitate readers' understanding of the technical solution of this application, the length direction of the substrate 10 is defined as the X-axis direction, the width direction of the substrate 10 is defined as the Y-axis direction, the thickness direction of the substrate 10 is defined as the Z-axis direction, and the thickness direction of the thin film transistor T is consistent with the thickness direction of the substrate 10.

[0024] In existing technologies, metal signal lines in display panels are generally designed to have low impedance by increasing their thickness and effective width to meet market demands for high-resolution, high-refresh-rate display products. However, in the low-temperature polysilicon (LTPS) process, when a light-shielding layer (LS) is used as the lower metal signal line in a thin-film transistor (TFT), if the LS employs a semi-enclosed design, the upper active layer at the edge of the LS will experience a significant slope due to the low impedance design of the metal signal line (i.e., increased film thickness). This leads to a thinner active layer in the slope region, which not only causes crystallization deterioration in subsequent crystallization processes but also significantly reduces the cross-sectional area of ​​the active layer in the slope region, narrowing the carrier pathway and reducing carrier mobility. This problem becomes increasingly pronounced as the thickness of the metal signal line increases.

[0025] In view of this, please refer to Figure 1 The first aspect of this application provides a thin-film transistor (TFT) T disposed on a substrate 10. The substrate 10 can be a rigid substrate such as glass or a flexible substrate such as polyimide (PI). An array region 101 and a peripheral region 102 adjacent to the array region 101 can be defined on the substrate 10. The array region 101 is the functional area on the substrate 10 where the TFT T is formed. Specifically, the pattern boundary can be defined using photolithography to ensure the electrical performance of the TFT T. The peripheral region 102 refers to the wiring area surrounding the array region 101, which can be formed by extending a metal layer to form a wiring channel, undertaking the signal transmission function. The TFT T is patterned on the substrate 10 and arranged in an array on the array region 101.

[0026] The thin-film transistor T includes a light-shielding layer 11, an active layer 13, a gate 15, and source / drain electrodes 17, patterned along the thickness direction of the thin-film transistor T. The thickness direction of the thin-film transistor T is perpendicular to the surface of the substrate 10, as shown in Figure 1. The light-shielding layer 11 is disposed close to the surface of the substrate 10, the active layer 13 is disposed on the side of the light-shielding layer 11 away from the substrate 10, the gate 15 is disposed on the side of the active layer 13 away from the light-shielding layer 11, and the source / drain electrodes 17 are disposed on the side of the gate 15 away from the active layer 13. The light-shielding layer 11, active layer 13, gate 15, and source / drain electrodes 17 are arranged vertically opposite each other in the thickness direction of the thin-film transistor T. It should be noted that the term "opposite arrangement" here does not require that all layers of the thin-film transistor T be completely perpendicular to each other in the direction perpendicular to the surface of the substrate 10; the layers may be partially opposite or misaligned in space.

[0027] The active layer 13 includes at least one of the following: a low-temperature polycrystalline silicon (LTPS) active layer, an amorphous silicon (a-Si) active layer, a low-temperature polycrystalline oxide (LTPO) active layer, and a metal oxide (MO) active layer, but is not limited thereto. For example, this embodiment uses a low-temperature polycrystalline silicon active layer to improve the carrier migration efficiency of the active layer 13 and increase the on / off ratio of the thin-film transistor T, thereby achieving the display panel's design requirements of high resolution, high refresh rate, and low power consumption.

[0028] The gate 15 of the thin-film transistor T receives voltage signals from the external driving circuit via a scan line, controlling the on / off state of the thin-film transistor T. The source and drain 17 of the thin-film transistor T includes a source 171 and a drain 172. The source 171 receives data signals from the data driving circuit via a data line, and the drain 172 is electrically connected to the pixel electrode 21. The source 171 and drain 172 are electrically connected to the underlying active layer 13 via bridging lines. When the thin-film transistor T is operating, when a voltage is applied to the gate 15, an electric field is formed between the gate 15 and the underlying active layer 13, attracting charge carriers (electrons or holes) in the active layer 13 to form a conductive channel. At this time, the thin-film transistor T is in the on state. The data signals received by the source 171 flow through the conductive channel to the drain 172, and then through the drain 172 to the pixel electrode 21, controlling the light emission of the sub-pixels of the display panel. After the voltage is removed from the gate 15, the conductive channel of the active layer 13 disappears. At this time, the thin film transistor T is in the off state, and the source 171 and the drain 172 are disconnected to control the sub-pixels of the display panel to turn off.

[0029] Specifically, the light-shielding layer 11 is used to block light from the backlight source (not shown in the figure) below the substrate 10, preventing light from shining on the semiconductor material of the active layer 13 and avoiding circuit performance drift problems (such as threshold voltage change, leakage voltage increase, and on / off ratio decrease) in the thin-film transistor T. In the orthographic projection of the light-shielding layer 11 and the active layer 13 onto the surface of the substrate 10, the active layer 13 and the light-shielding layer 11 have a junction region 103 (e.g., ...). Figures 2a-2e (As shown in the diagram). The “intersection area 103” mentioned here may include the area where the orthographic projections of the light-shielding layer 11 and the active layer 13 on the surface of the substrate 10 overlap, and may also include the adjacent area adjacent to the overlapping area.

[0030] When a light-shielding layer 11 is used as the lower metal signal line in a thin-film transistor T, if the light-shielding layer 11 adopts a semi-enclosed design, at least part of the structure of the upper active layer 13 will extend beyond the edge of the light-shielding layer 11. Therefore, in the region at the edge of the light-shielding layer 11, the upper active layer 13 will exhibit a significant ramping phenomenon due to the low impedance design of the metal signal line (i.e., increased film thickness). This results in a reduction in the film thickness of the active layer 13 in the ramping region, which not only leads to crystallization deterioration in the subsequent crystallization process but also significantly reduces the cross-sectional area of ​​the active layer 13 in the ramping region, narrowing the carrier pathway and reducing the carrier mobility.

[0031] Please see Figures 2a-2e To address this issue, the thin-film transistor T provided in this application, compared with the prior art, features a compensated design for the layout shape of the active layer 13. The active layer 13 includes an extension portion 132 and a main body portion 131. The extension portion 132 is located within the junction region 103, and the main body portion 131 connects to the extension portion 132. The width of the extension portion 132 is greater than the width of the main body portion 131. Here, "width" refers to the lateral dimension of the extension portion 132 and the main body portion 131 in the layer structure plane of the active layer 13, perpendicular to the extension direction of the main body portion 131, resulting in the extension portion 132 exhibiting a "laterally widened" extension state relative to the main body portion 131. Under the premise of equal length (the dimension of the main body portion 131 in the extension direction) and equal thickness, the extension portion 132 has a relatively larger lateral cross-sectional area, resulting in a larger amount of charge carriers passing through per unit time and a higher mobility. In addition, the laterally widened extension 132 significantly increases the area of ​​the active layer 13 in the ramp region and the total amount of semiconductor material, which is beneficial for the conversion of amorphous silicon (a-Si) to polycrystalline silicon (poly-Si) in the subsequent crystallization process. It effectively avoids problems such as uneven heating, small crystal particles, and increased crystal defects caused by factors such as thinning of the film layer in the ramp region, large difference in thermal conductivity between the ramp region and the non-ramp region, and insufficient semiconductor material in the ramp region during the crystallization process.

[0032] Through the above technical solution, the thin film transistor T provided in this application has an extended portion 132 with a significantly increased width located in the junction region 103 on the main body portion 131 of the active layer 13. This facilitates the smooth progress of the subsequent crystallization process, avoids the problem of crystallization deterioration, and significantly increases the cross-sectional size of the carrier channel in the edge ramp region of the light-shielding layer 11 of the active layer 13. This improves the problem of decreased electron mobility caused by thinning of the ramp region of the active layer 13, which helps to reduce the leakage current of the active layer 13, ensures the realization of the device electrical performance of the thin film transistor T, and is conducive to the high resolution, high refresh rate and low power consumption design of the display panel.

[0033] In some embodiments, please refer to Figures 2a-2eThe thin-film transistor T provided in this application further proposes that the main body 131 extends at least along a first direction, and the extension portion 132 is disposed on the main body 131 and arranged opposite to it at least along the first direction. The light-shielding layer 11 extends at least along a second direction, and along the thickness direction of the thin-film transistor T, at least a portion of the light-shielding layer 11 intersects with the main body 131 between the oppositely arranged extension portions 132. The first direction and the second direction intersect. In this embodiment, the extension direction of the main body 131, i.e., the first direction, is exemplified by the Y-axis direction, and the extension direction of the light-shielding layer 11, i.e., the second direction, is exemplified by the X-axis direction.

[0034] In a specific implementation, the main body 131 can be designed as a strip-shaped structure extending at least along a first direction (taking the Y-axis direction as an example, which will not be elaborated further below), and the main body 131 is connected to the extension portion 132 at least along the first direction. Within the layer structure plane of the active layer 13, the main body 131 has a predetermined width W1. The extension portion 132 is disposed on the main body 131 and arranged opposite to each other at least along the first direction, that is, the extension portions 132 are arranged in pairs on the main body 131 in the first direction. Within the layer structure plane of the active layer 13, the extension portion 132 has a predetermined width W2, and W2 > W1. It should be noted that the "opposite arrangement" mentioned here does not require that the opposite extension portions 132 on the main body 131 be completely perpendicular to each other in the first direction; the extension portions 132 may be partially opposite or misaligned in the first direction. The center line connecting the oppositely arranged extension portions 132 preferably coincides with the longitudinal axis of the main body portion 131. This design ensures that the extension portions 132 are directly opposite each other and that the two ends of the oppositely arranged extension portions 132 extend beyond the two sides of the main body portion 131 to the same extent in the width direction, thus ensuring the uniform compensation effect of the extension portions 132.

[0035] In a specific implementation, the light-shielding layer 11 can be designed as a strip structure extending at least along the second direction (taking the X-axis direction as an example, which will not be elaborated further below). In the thickness direction of the thin-film transistor T, i.e., the Z-axis direction, the light-shielding layer 11 intersects the main body 131 in a non-direct contact manner between the oppositely arranged extension portions 132. The "non-direct contact" refers to the intersection of the light-shielding layer 11 and the main body 131 on different layers of the thin-film transistor T. The extension portions 132 are located at the two side edges along the length direction of the light-shielding layer 11 to ensure that the ramp region of the active layer 13 at the edge of the light-shielding layer 11 is located within the extension portions 132, ensuring that the extension portions 132 can effectively compensate for the current limiting loss caused by the thinning of the film layer and the narrowing of the carrier channels in the ramp region of the active layer 13.

[0036] In some embodiments, please refer to Figure 1The thin-film transistor T provided in this application embodiment further proposes that the active layer 13 includes a channel portion 133 and a doped region 134. The channel portion 133 is disposed on the main body portion 131 and located between the oppositely arranged extension portions 132. The orthogonal projection of the channel portion 133 on the substrate 10 is located within the junction region 103, so as to ensure that the light-shielding layer 11 below can completely block the channel portion 133 of the active layer 13, preventing light from the backlight source below the substrate 10 from directly irradiating the channel portion 133, avoiding the light from exciting the active layer 13 material (such as LTPS) in the channel portion 133 to generate additional "photoinduced carriers", and avoiding the problem of circuit performance drift (such as threshold voltage change, leakage voltage increase, and on / off ratio decrease) of the thin-film transistor T.

[0037] The doped region 134 is connected to both ends of the channel portion 133 and arranged opposite to each other along the first direction. The doped region 134 is at least partially disposed on the main body portion 131 and at least partially disposed on the extension portion 132. The doped region 134 is the core channel for current to enter and exit the channel portion 133. In a specific implementation, one end of the doped region 134 connected to the channel portion 133 is disposed on the main body portion 131, and the end of the doped region 134 away from the channel portion 133 is disposed on the extension portion 132, so that the channel portion 133 is completely within the shielding range of the light-shielding layer 11. The junction region 103 between the doped region 134 and the edge of the light-shielding layer 11 is the current-limiting bottleneck where the active layer 13's ramp region thins and the carrier channel narrows. This application extends at least a portion of the structure of the doped region 134 onto the extension portion 132, significantly increasing the cross-sectional size of the carrier channel in the ramp region of the doped region 134 at the edge of the light-shielding layer 11. The width increment of the extension portion 132 counteracts the carrier current limiting effect caused by the thinning of the film layer in the ramp region, improving the efficiency of carrier transport from the doped region 134 to the channel portion 133, and ensuring the realization of the device electrical performance of the thin film transistor T.

[0038] For further details, please refer to Figure 1 In the embodiments of this application, the thin-film transistor T includes a lightly doped region 134 and a heavily doped region in each doped region 134. One end of the lightly doped region 1341 is connected to the channel portion 133, and the other end of the lightly doped region 1341 is connected to the heavily doped region. The heavily doped region located at one end of the channel portion 133 is the source-end heavily doped region 1342, and the heavily doped region located at the other end of the channel portion 133 is the drain-end heavily doped region 1343. The source-end heavily doped region 1342 is electrically connected to the source 171 of the thin-film transistor T, and the drain-end heavily doped region 1343 is electrically connected to the drain 172 of the thin-film transistor T.

[0039] Specifically, along the thickness direction of the substrate 10, the thin-film transistor T further includes a buffer layer 12, a gate insulating layer 14, and an interlayer dielectric layer 16. In a specific implementation, a first metal layer can be deposited on the surface of the substrate 10 using a magnetron sputtering process. The material of the first metal layer includes, but is not limited to, metals, alloys, or stacked materials such as aluminum (Al), molybdenum (Mo), copper (Cu), silver (Ag), gold (Au), tungsten (W), and titanium (Ti) to reduce impedance. Then, the first metal layer is patterned using a photolithography process to form the light-shielding layer 11 of the arrayed thin-film transistors T.

[0040] A buffer layer 12 is disposed on one side of the substrate 10 and covers the light-shielding layer 11, while an active layer 13 is disposed on the side of the buffer layer 12 away from the substrate 10. Specifically, a plasma-enhanced chemical vapor deposition process can be used to deposit and form the buffer layer 12 on the patterned substrate 10 after the light-shielding layer 11 is applied, covering it with a first metal layer. The buffer layer 12 can be a single-layer structure or a multi-layer structure; this application does not limit this. For example, the buffer layer 12 can be a single-layer structure or a multi-layer structure formed by depositing inorganic non-metallic materials such as silicon nitride (SiNx) or silicon oxide (SiO2).

[0041] The buffer layer 12 can reduce the stress between the substrate 10 and the upper structure, reduce stress concentration caused by factors such as the difference in the thermal expansion coefficient of the materials, and also prevent impurities in the substrate 10 from diffusing to the upper active layer 13, thus ensuring the purity and performance stability of the semiconductor material in the active layer 13.

[0042] After forming a buffer layer 12 on the substrate 10 and covering it with a patterned light-shielding layer 11, an amorphous silicon (a-Si) layer can be deposited on the buffer layer 12 using plasma-enhanced chemical vapor deposition (PECVD). Then, the deposited amorphous silicon layer is annealed using excimer laser annealing, where laser energy causes the amorphous silicon layer to recrystallize and transform into a polycrystalline silicon (poly-Si) layer. The transformed polycrystalline silicon layer is then patterned using photolithography to form a polycrystalline silicon pattern that matches the active layer 13 of the thin-film transistor T. Finally, boron ions (B2O3) are implanted into the channel region of the polycrystalline silicon pattern using ion implantation. + Subsequently, low-temperature annealing activates the doped ions to form the channel portion 133 of the active layer 13.

[0043] Specifically, the gate insulating layer 14 is disposed on the side of the buffer layer 12 away from the substrate 10 and covers the active layer 13, and the gate 15 is disposed on the side of the gate insulating layer 14 away from the buffer layer 12. The gate insulating layer 14 can be deposited on the buffer layer 12 after the polysilicon layer is patterned using a plasma-enhanced chemical vapor deposition process. The gate insulating layer 14 can be a single-layer structure or a multi-layer structure, and this application does not limit it in this regard. Exemplarily, the gate insulating layer 14 can be a single-layer structure or a multi-layer structure formed by depositing inorganic non-metallic materials such as silicon nitride (SiNx) and silicon oxide (SiO2).

[0044] The gate insulating layer 14 electrically isolates the active layer 13 from the gate 15 and is compatible with low-temperature polysilicon manufacturing processes. After forming the channel portion 133 on the polysilicon pattern by doping with boron ions, a plasma-enhanced chemical vapor deposition process can be used to deposit the gate insulating layer 14 on the buffer layer 12 and cover the polysilicon pattern with the channel portion 133. Then, a second metal layer can be deposited on the gate insulating layer 14 using a magnetron sputtering process. The material of the second metal layer includes, but is not limited to, metals, alloys, or stacked materials such as aluminum (Al), molybdenum (Mo), copper (Cu), silver (Ag), gold (Au), tungsten (W), and titanium (Ti). Then, the second metal layer is patterned using a photolithography process to form the gate 15 that matches the channel portion 133 of the thin-film transistor T. Then, photoresist is coated on the surface of the gate insulating layer 14, and the area to be heavily doped on the polysilicon pattern is exposed using a mask. Then, a high dose of phosphorus ions (P ions) is implanted into the exposed area using an ion implantation process. + The active layer 13 is formed by creating a heavily doped source region 1342 and a heavily doped drain region 1343. After removing the photoresist used for the heavily doped regions, the gate 15 is used as a "self-aligned mask" to block the channel region below it. Then, a low dose of phosphorus ions is implanted into the portion not blocked by the gate 15 using an ion implantation process to form a lightly doped region 1341 of the active layer 13. Subsequently, rapid thermal annealing is performed to activate the dopant ions in the heavily doped and lightly doped regions 1341, while repairing the lattice damage to the polysilicon caused during ion implantation.

[0045] Specifically, the interlayer dielectric layer 16 is disposed on the side of the gate insulating layer 14 away from the buffer layer 12 and covers the second metal layer, while the source and drain electrodes 17 are disposed on the side of the interlayer dielectric layer 16 away from the gate insulating layer 14. The interlayer dielectric layer 16 can be deposited on the patterned gate insulating layer 14 using a plasma-enhanced chemical vapor deposition process. The interlayer dielectric layer 16 can be a single-layer structure or a multi-layer structure, and this application does not limit this. Exemplarily, the interlayer dielectric layer 16 can be a single-layer structure or a multi-layer structure formed by depositing inorganic non-metallic materials such as silicon nitride (SiNx) and silicon oxide (SiO2).

[0046] After depositing an interlayer dielectric layer 16 on the gate insulating layer 14, a rapid thermal annealing process is used for radial hydrogenation and activation. This process repairs dangling bonds in the polysilicon using H2 plasma (reducing interface state density) and further activates doped ions. Then, a photolithography process is used to form source vias 104 and drain vias 105 penetrating the interlayer dielectric layer 16 and the gate insulating layer 14. The source via 104 exposes the heavily doped source region 1342 of the active layer 13, and the drain via 105 exposes the heavily doped drain region 1343 of the active layer 13. A third metal layer can then be deposited on the interlayer dielectric layer 16 using magnetron sputtering. This third metal layer at least partially fills the source vias 104 and drain vias 105. The material of the third metal layer includes, but is not limited to, metals, alloys, or multilayer materials such as aluminum (Al), molybdenum (Mo), copper (Cu), silver (Ag), gold (Au), tungsten (W), and titanium (Ti). Then, the third metal layer is patterned by photolithography to form a source-drain pattern 17 that matches the heavily doped region of the thin film transistor T. The source-drain pattern 17 includes a source 171 and a drain 172. The source 171 is electrically connected to the heavily doped source region 1342 of the active layer 13 through a source via 104, and the drain 172 is electrically connected to the heavily doped drain region 1343 of the active layer 13 through a drain via 105.

[0047] In some embodiments, please refer to Figures 2a-2e This application further proposes that, along a first direction, the extension portion 132 at least partially extends beyond the edge of the light-shielding layer 11; and along a second direction, the extension portion 132 at least partially extends beyond the edge of the main body portion 131.

[0048] The first direction is the extension direction of the main body 131, and the second direction is the extension direction of the light-shielding layer 11. The first direction and the second direction intersect, so that the light-shielding layer 11 and the active layer 13 intersect in the thickness direction of the thin film transistor T. Specifically, the sidewall 111 of the extension direction of the light-shielding layer 11 generally has an angle with the plane of the substrate 10. This causes the sidewall 111 of the extension direction of the light-shielding layer 11 to extend in an inclined state that is not perpendicular to the plane of the substrate 10. Its orthographic projection on the substrate 10 is at least partially located in the junction area 103, and corresponds to the sloping area of ​​the active layer 13 at the edge of the light-shielding layer 11.

[0049] When the orthographic projection of the extension portion 132 onto the surface of the substrate 10 is limited to the area where the active layer 13 overlaps with the light-shielding layer 11, the edge of the extension portion 132 in the second direction is exactly aligned with the edge of the light-shielding layer 11. In this case, the active layer 13 is only widened in the ramp area. This design does not provide sufficient redundancy for the alignment of the active layer 13 and the light-shielding layer 11. In actual manufacturing, even a small alignment deviation may cause the extension portion 132 to fail to completely cover the ramp area of ​​the active layer 13, resulting in a weakened or even failed compensation effect of the extension portion 132.

[0050] To address this issue, the thin-film transistor T provided in this application has at least a portion of its extended portion 132 extending beyond the edge of the light-shielding layer 11, further expanding the range of the extended portion 132. This means that the orthographic projection of the extended portion 132 onto the surface of the substrate 10 includes both the region where the active layer 13 overlaps with the light-shielding layer 11 and the adjacent region adjacent to the overlapping region. In this case, the active layer 13 is widened not only in the ramp region but also in the portion extending beyond the edge of the light-shielding layer 11. Compared to widening only in the ramp region, the portion of the extended portion 132 extending beyond the edge of the light-shielding layer 11 essentially provides design redundancy for alignment accuracy deviations between the active layer 13 and the light-shielding layer 11, ensuring that the ramp region is always within the range of the extended portion 132. This avoids the problem of weakened or even failed compensation effect of the extended portion 132, significantly improving process tolerance and product yield.

[0051] Furthermore, along the second direction, the extension portion 132 at least partially extends beyond the edge of the main body portion 131. This design ensures that the extension portion 132 is "laterally widened" or "laterally protruding" relative to the strip-shaped main body portion 131 in the lateral direction. Compared to the unextended main body portion 131, this significantly increases the effective cross-sectional area of ​​the carrier path, effectively compensating for the current-limiting effect caused by the reduced cross-sectional area of ​​the active layer 13 in the ramp region at the edge of the light-shielding layer 11, and improving the efficiency of carrier transport from the doped region 134 to the channel portion 133. Simultaneously, in the laser crystallization process of low-temperature polycrystalline silicon (LTPS), the significantly enlarged extension portion 132 helps to achieve uniform heat distribution and dissipation. This not only provides more semiconductor material for the ramp region of the active layer 13 but also improves the heating uniformity of this region, promoting the formation of larger and more uniform polycrystalline silicon grains, thereby fundamentally improving carrier mobility. In some embodiments, the thin-film transistor T provided in this application includes an extension portion 132 comprising at least one shape selected from circles, ellipses, polygons, and irregular shapes. The "shape" refers to the shape of the extension portion 132 projected onto the surface of the substrate 10. Those skilled in the art will understand that the specific shape of the extension portion 132 can be flexibly selected and optimized based on the actual layout space of the thin-film transistor T in the array substrate, signal line routing requirements, and process capabilities. Its core purpose is to improve carrier mobility by increasing the cross-sectional area of ​​the ramp region, while simultaneously considering layout flexibility and process stability.

[0052] In specific implementations, the shape of the extension portion 132 can be a regular circle or an ellipse with smooth, curved edges (e.g., ...). Figure 2a , 2c As shown in Figure 2e, this design helps reduce stress concentration during subsequent thin film deposition and laser crystallization (such as LTPS processes), promoting a more uniform and less defective grain structure in the active layer 13 material (such as polycrystalline silicon). This is particularly beneficial for improving device consistency and reliability. Simultaneously, the circular or elliptical design of the extension portion 132 effectively avoids pattern distortion or residue caused by sharp corners during photolithography and etching.

[0053] In specific implementation, the shape of the extension 132 can be a regular rectangle (such as...). Figure 2b , 2d As shown in the figure), rhombus, trapezoid, etc., the extension part 132 of this type of shape has a simple structure and is easy to manufacture. It can provide sufficient and uniform cross-sectional area compensation, ensuring the carrier migration efficiency of the active layer 13.

[0054] In practical implementation, when the area where the extension section 132 is located is squeezed by other traces, devices or structures, the extension section 132 can adopt an irregular shape design to "fill in the gaps" to achieve the compensation function, maximize the use of the limited layout area, and enable the technical solution of this application to flexibly adapt to various complex and highly integrated panel design needs.

[0055] Please see Figures 2a-2e In some embodiments, the thin-film transistor T provided in this application further discloses that within the junction region 103, the area of ​​the overlapping region between the extension portion 132 and the light-shielding layer 11 is S2, and the area of ​​the extension portion 132 is S1. The relationship between S2 and S1 satisfies: 1 / 5×S1≤S2≤4 / 5×S1. By limiting the proportional relationship between the area S2 of the overlapping region between the extension portion 132 and the light-shielding layer 11 and the area S1 of the extension portion 132, this application ensures that the extension portion 132 achieves the best balance between effective compensation performance and avoiding over-design.

[0056] Specifically, the area S2 of the overlapping region between the extension portion 132 and the light-shielding layer 11 must not be less than one-fifth of the area S1 of the extension portion 132 (i.e., S2 ≥ 1 / 5 × S1). This condition ensures that the light-shielding layer 11 has a sufficiently large area to overlap with the extension portion 132. A sufficiently large overlapping area ensures that the light-shielding layer 11 not only completely blocks the channel portion 133, but also provides sufficient and reliable shielding for the doped region 134 near the channel portion 133, preventing backlight irradiation from causing optical leakage current and ensuring the electrical stability of the thin-film transistor T. In addition, the minimum proportion of the area S2 of the overlapping region between the extension portion 132 and the light-shielding layer 11 ensures that the extension portion 132 can at least cover the inclined sidewall 111 region of the light-shielding layer 11, ensuring that the expansion area of ​​the active layer 13 in the ramp region at the edge of the light-shielding layer 11 can effectively compensate for the carrier current limiting problem caused by the thinning of the film layer in the ramp region.

[0057] If the area S2 of the overlapping region between the light-shielding layer 11 and the extension 132 is too large (e.g., close to S1), it means that the extension 132 is almost completely blocked by the light-shielding layer 11, and the proportion of it extending beyond the edge of the light-shielding layer 11 will be very small. This will not provide sufficient redundancy space for possible alignment deviations, and the compensation effect and process window will deteriorate sharply. Therefore, the thin-film transistor T provided in this application further limits the area S2 of the overlapping region between the extension 132 and the light-shielding layer 11 to a maximum of no more than four-fifths of the area S1 of the extension 132 (i.e., S2 ≤ 4 / 5 × S1). This condition ensures that the extension 132 has a sufficiently large area (at least 1 / 5 of its own area) that extends beyond the edge of the light-shielding layer 11. The portion extending beyond the edge of the light-shielding layer 11 ensures that the extension 132 completely covers the entire ramp area and provides process alignment redundancy, thereby guaranteeing the redundancy compensation effect of the extension 132.

[0058] In some embodiments, the thin-film transistor T provided in this application, along the second direction, has an edge of the light-shielding layer 11 that can be configured as an outer arc-shaped edge (e.g., ...). Figure 2c (as shown in the image) or inner curved edge (such as...) Figure 2d (as shown) or toothed edges (such as) Figure 2e As shown in the figure, the edge structures on both sides of the light-shielding layer 11 can be the same, or they can be set differently according to the spatial layout or performance requirements of different sides. Preferably, the edge structures on both sides of the light-shielding layer 11 are the same to ensure that the compensation effect of the active layer 13 in the climbing area on both sides of the light-shielding layer 11 is consistent.

[0059] The edge shape of the light-shielding layer 11 directly affects the morphology of the active layer 13 in the ramp region at the edge of the light-shielding layer 11. Through the above technical solution, the thin-film transistor T provided in this application can improve the film formation uniformity and crystallization uniformity of the active layer 13 in the ramp region at the edge of the light-shielding layer 11 from the source, realize the synergistic gain effect between the edge structure of the light-shielding layer 11 and the extension portion 132 of the active layer 13, and further improve the problem of the decrease in carrier mobility caused by the thinning of the active layer 13 in the ramp region.

[0060] Specifically, the edge of the light-shielding layer 11 can be set as follows: Figure 2c As shown, the outer arc-shaped edge of the light-shielding layer 11, compared to the straight-edge structure design, smoothly protrudes outward from the outer arc-shaped edge. This transforms the steep, short slope of the light-shielding layer 11 edge into a gentle, gradual outer arc-shaped slope, resulting in a more uniform and continuous film thickness for the extended portion 132 deposited on it. This significantly alleviates the problem of the film thickness of the extended portion 132 thinning drastically in the slope region. Furthermore, during LTPS laser crystallization, the gentler outer arc-shaped slope of the light-shielding layer 11 facilitates uniform heat conduction, preventing uneven crystal grains and increased crystal defects in the extended portion 132 due to uneven heat conduction in the slope region.

[0061] Specifically, the edge of the light-shielding layer 11 can also be set as follows: Figure 2d The inner curved edge shown, or as Figure 2e The toothed edge shown in the diagram, compared to the straight edge structure design, has the edge of the light-shielding layer 11 smoothly recessed or zigzag recessed inward. Within a unit length, this effectively increases the profile length of the edge of the light-shielding layer 11, so that the extension portion 132 on its upper layer no longer thins along a straight line in the climbing region, but forms an interwoven climbing region in three-dimensional space with a larger overlap area with the edge of the light-shielding layer 11. This significantly increases the cross-sectional area of ​​the current-carrying channel of the extension portion 132 in the climbing region, effectively compensating for the current-limiting effect caused by the thinning of the active layer 13 in the climbing region.

[0062] The thin-film transistor T provided in this application, through the above-mentioned technical solution, combines the arc-shaped edge (outer arc-shaped edge or inner arc-shaped edge) or tooth-shaped edge of the light-shielding layer 11 with the extension portion 132 of the active layer 13, optimizes the edge structure of the light-shielding layer 11, improves the morphological characteristics of the extension portion 132 of the active layer 13 in the climbing region, further improves the carrier migration efficiency of the active layer 13, ensures the uniformity of the crystal particles of the active layer 13, and reduces crystal defects.

[0063] In some embodiments, please refer to Figures 2a-2eThe thin-film transistor T provided in this application further proposes that the active layer 13 may simultaneously include two main body portions 131 extending along a first direction and spaced apart, each main body portion 131 having an extension portion 132 arranged opposite to each other along the first direction. The active layer 13 also includes a connecting portion 135 connecting the two main body portions 131 outside the junction region 103, the connecting portion 135 connecting the same end of the two main body portions 131, so that the main body portions 131 of the active layer 13 form an approximate "U" shaped structure. The light-shielding layer 11 extends along a second direction, and in the thickness direction of the thin-film transistor T, the light-shielding layer 11 intersects with the oppositely arranged extension portions 132 and the two main body portions 131 in different layers.

[0064] Specifically, one of the main body portions 131 has a source-end heavily doped region electrode portion 136 for connecting the source electrode 171 at one end away from the connecting portion 135, and the other main body portion 131 can be configured as a drain-end heavily doped region electrode portion 137 for connecting the drain electrode 172 at one end away from the connecting portion 135. The source-end heavily doped region electrode portion 136 and the drain-end heavily doped region electrode portion 137 are located outside the junction region 103, and their widths can also be set to be greater than the width of the main body portion 131, so as to facilitate the alignment of the source-end via 104 with the source-end heavily doped region electrode portion 136 and the drain-end via 105 with the drain-end heavily doped region electrode portion 137.

[0065] Through the above technical solution, the thin film transistor T provided in this application embodiment can form a "dual-channel structure" in the junction area 103 between the light-shielding layer 11 and the two main body portions 131. Compared with the traditional single-channel structure design, the efficiency of carriers entering and exiting the channel portion 133 can be further improved by using the parallel dual-channel method, which significantly improves the device electrical performance of the thin film transistor T and makes it easy to realize high refresh rate drive control of display products.

[0066] Please see Figure 1 According to a second aspect of this application, an array substrate 100 is provided. The array substrate 100 includes a substrate 10 and thin-film transistors T. An array region 101 and a peripheral region 102 adjacent to the array region 101 are defined on the substrate 10. The length direction of the array substrate 100 is consistent with the length direction of the substrate 10, and in this application, the X-axis direction is used as an example. The width direction of the array substrate 100 is consistent with the width direction of the substrate 10, and in this application, the Y-axis direction is used as an example. The thickness direction of the array substrate 100 is consistent with the thickness direction of the substrate 10, and in this application, the Z-axis direction is used as an example.

[0067] The thin-film transistor T includes one of the thin-film transistors T in the above embodiments, and the thin-film transistor T array is disposed on the substrate 10 and located within the array region 101. The array substrate 100 provided in this application has all the beneficial effects of the thin-film transistor T described above, which will not be repeated here.

[0068] In some embodiments, please refer to Figure 1 and Figure 3 The array substrate 100 provided in this application embodiment also includes metal traces 3 (such as...). Figure 3 As shown in the figure, the metal traces 3 are arranged on the substrate 10 and located in the peripheral area 102.

[0069] Metal traces 3 are used to achieve efficient electrical connections between pixel functional units (such as thin-film transistors T) in the array region 101 and external driving devices (such as driver ICs). Currently, narrow bezel designs of the array substrate 100 are becoming mainstream, which requires metal traces 3 to make the most of the limited space in the peripheral region 102 for wiring.

[0070] Based on this, the array substrate 100 provided in this application further optimizes and improves the layout of the metal traces 3 in the peripheral region 102 on the basis of the thin film transistor T, making full use of the original three metal layers (first metal layer, second metal layer, and third metal layer) of the thin film transistor T to realize the multi-dimensional wiring design of the three-layer sub-line jump connection of the metal traces 3.

[0071] Specifically, please refer to Figure 1 The metal trace 3 includes multiple first metal traces 31. Along the thickness direction of the array substrate 100, i.e., the thickness direction of the thin-film transistor T (taking the Z-axis direction as an example, which will not be elaborated further below), each first metal trace 31 includes a patterned first sub-line 311, a second sub-line 312, and a third sub-line 313. The first sub-line 311 and the light-shielding layer 11 are located in the same metal layer, i.e., within the aforementioned first metal layer; the second sub-line 312 and the gate 15 are located in the same metal layer, i.e., within the aforementioned second metal layer; and the third sub-line 313 and the source / drain electrodes 17 are located in the same metal layer, i.e., within the aforementioned third metal layer. The third sub-line 313 of the same first metal trace 31 bridges the second sub-line 312 and the first sub-line 311.

[0072] During the fabrication of the array substrate 100, the first sub-line 311 and the light-shielding layer 11 of the thin-film transistor T are integrated on the first metal layer, and the patterning of the first sub-line 311 and the light-shielding layer 11 can be completed by a photomask process; the second sub-line 312 and the gate 15 of the thin-film transistor T are integrated on the second metal layer, and the patterning of the second sub-line 312 and the gate 15 can be completed by a photomask process; the third sub-line 313 and the source / drain electrode 17 of the thin-film transistor T are integrated on the third metal layer, and the patterning of the third sub-line 313 and the source / drain electrode 17 can be completed by a photomask process.

[0073] For the same first metal trace 31, at least a portion of the structure of the third sub-line 313 serves as a bridging metal line on the top layer. Its orthographic projection on the substrate 10 at least partially overlaps with the orthographic projection of the first sub-line 311 on the substrate 10 and at least partially overlaps with the orthographic projection of the second sub-line 312 on the substrate 10. This allows the third sub-line 313 to electrically connect the first sub-lines 311 and the second sub-lines 312 of different layers below through corresponding vias penetrating the interlayer medium in the vertical direction. This enables the three sub-lines belonging to different metal layers of the same first metal trace 31 to be connected across layers. Furthermore, through methods such as three-dimensional crossing and interlayer jumpers, more metal traces 3 can be arranged within the limited wiring space of the peripheral area 102, significantly increasing the wiring density of the metal traces 3. This breaks through the limits of traditional double-layer wiring of metal traces and enables the ultra-narrow bezel design of display products.

[0074] In specific implementations, the material of the first metal layer can be selected from metals, alloys, or multilayer materials such as aluminum (Al), molybdenum (Mo), copper (Cu), silver (Ag), gold (Au), tungsten (W), and titanium (Ti) to meet the low-resistance design requirements of the metal signal lines. Preferably, the material of the first metal layer can be a multilayer metal material, such as aluminum-molybdenum (Al-Mo), aluminum-Ti, copper-molybdenum (Cu-Mo), silver-molybdenum (Ag-Mo), and molybdenum-aluminum-molybdenum (Mo-Al-Mo).

[0075] Furthermore, the thickness N1 of the first metal layer satisfies the following condition: 1000Å ≤ N1 ≤ 3000Å. 1000Å is the critical thickness for the first metal layer to be continuous and free of pinholes. Controlling the thickness of the first metal layer to not less than 1000Å ensures that the light-shielding layer 11 will not have pinhole defects, thus guaranteeing the light-shielding effect. 3000Å ​​is the upper limit of the thickness of the first metal layer. Controlling the thickness of the first metal layer to not more than 3000Å ​​avoids problems such as excessive thickness of the light-shielding layer 11, which could lead to increased slope of the upper film structure (such as the buffer layer 12, active layer 13, gate insulating layer 14, etc.) at the edge of the light-shielding layer 11, and film breakage. In addition, controlling the thickness of the first metal layer to not more than 3000Å ​​also ensures that the first sub-line 311 in the peripheral region 102 meets the low impedance design requirements and guarantees the signal transmission efficiency of the first sub-line 311.

[0076] Those skilled in the art will understand that the materials for the second and third metal layers can also be selected from metals, alloys, or multilayer materials such as aluminum (Al), molybdenum (Mo), copper (Cu), silver (Ag), gold (Au), tungsten (W), and titanium (Ti) to meet the low-resistance design requirements of the metal signal lines. In specific implementations, the materials and film thicknesses of the second and third metal layers can be adjusted or improved according to the actual situation, and this application does not limit them in this regard.

[0077] Through the above technical solution, the metal traces 3 of the peripheral area 102 of the array substrate 100 provided in this application are wired in a three-layer sub-line jump-layer connection manner, which makes full use of the original three metal layers (first metal layer, second metal layer, and third metal layer) of the thin film transistor T. Without adding additional metal layer structures to the array substrate 100, or adding additional photomasks and process steps, the low-resistance design and high-density wiring of the metal traces 3 are achieved. This is beneficial for reducing the size of the peripheral area and realizing a narrow bezel design, which meets the design requirements of high resolution and high refresh rate array substrate 100, and fundamentally controls production costs and process complexity.

[0078] In some embodiments, please refer to Figure 3 The array substrate 100 provided in this embodiment further proposes that the peripheral region 102 includes a wiring region 1021 and a line-changing region 1022 adjacent to the wiring region 1021. The array substrate 100 also includes a first via 106 and a second via 107 disposed in the line-changing region 1022.

[0079] Specifically, a buffer layer 12 is disposed on one side of the substrate 10 and covers the first metal layer, a gate insulating layer 14 is disposed on the side of the buffer layer 12 away from the substrate 10 and covers the active layer 13, a second metal layer is disposed on the side of the gate insulating layer 14 away from the buffer layer 12, an interlayer dielectric layer 16 is disposed on the side of the gate insulating layer 14 away from the buffer layer 12 and covers the second metal layer, and a third metal layer is disposed on the side of the interlayer dielectric layer 16 away from the gate insulating layer 14.

[0080] In the thickness direction of the array substrate 100, a first via 106 penetrates the interlayer dielectric layer 16, the gate insulating layer 14, and the buffer layer 12 in the peripheral region 102, and exposes the first sub-line 311; a second via 107 penetrates the interlayer dielectric layer 16 in the peripheral region 102 and exposes the second sub-line 312. The third sub-line 313 of the same first metal trace 31 is bridged downwards to the first sub-line 311 located in the first metal layer via a corresponding first via 106 provided in the line-changing region 1022, and is bridged downwards to the second sub-line 312 located in the second metal layer via a corresponding second via 107 provided in the line-changing region 1022.

[0081] Within the trace area 1021, the main extension portion of the metal trace 3 can be arranged in parallel along the same direction or approximately the same direction (such as the extension direction of the edge of the array area 101). Different sub-lines of different first metal traces 31 located in the same metal layer are isolated by interlayer dielectric. Different sub-lines of different first metal traces 31 located in different metal layers may have overlapping portions when projected onto the surface of the substrate 10.

[0082] like Figure 3 As shown in the illustration, this embodiment uses three adjacent and staggered first metal traces 31 as an example for explanation. To facilitate the differentiation of the sub-lines of different first metal traces 31, the third sub-line 313 of the first first metal trace 31 is defined as the third sub-line A 313a, the second sub-line 312 of the second first metal trace 31 is defined as the second sub-line B 312b, and the first sub-line 311 of the third first metal trace 31 is defined as the first sub-line C 311c. In the thickness direction of the array substrate 100, the orthographic projections of the third sub-line A 313a, the second sub-line B 312b, and the first sub-line C 311c of three adjacent first metal traces 31 on the substrate 10 overlap. Below the third sub-line A 313a of the first first metal trace 31, the second sub-line B 312b of the second first metal trace 31, adjacent to one side of the first metal trace 31, can be arranged. Below the second sub-line B 312b, the first sub-line C 311c of the third first metal trace 31, adjacent to one side of the second first metal trace 31, can be arranged. This design allows different levels of sub-lines of different first metal traces 31 to share the wiring space in the thickness direction of the array substrate within the wiring area 1021, significantly improving the utilization rate of the wiring space in the peripheral area, thereby increasing the wiring density of the peripheral area 102, further reducing the size of the peripheral area, and achieving a narrower bezel design.

[0083] Within the switching area 1022, different levels of sub-lines of the first metal trace 31 can be appropriately bent or turned within the corresponding metal layer plane, so that different levels of sub-lines of the same first metal trace 31 can partially overlap within the switching area 1022. This design ensures that the third sub-line 313 located on the third metal layer can play a bridging role in the switching area 1022, realizing inter-layer switching and electrical connection between different levels of sub-lines in the same first metal trace 31. This maximizes the utilization of the three-layer wiring space of the wiring area 1021, significantly reduces the space occupied by the metal trace 3 in the peripheral area, facilitates the narrow bezel design of the array substrate 100, and significantly improves the wiring flexibility and redundancy of the metal trace 3 in the peripheral area 102, meeting the wiring requirements of different types of metal signal lines.

[0084] Furthermore, in the array substrate 100 provided in this application, the first metal traces 31 in the peripheral region 102 are all bridged downwards to the second sub-trace 312 and the first sub-trace 311 through the third sub-trace 313 located in the third metal layer. Therefore, in the fabrication process of the array substrate 100, after the formation of the interlayer dielectric layer 16 and before the deposition of the third metal layer, multiple vias (including source via 104, drain via 105, first via 106, and second via 107) located in the array region 101 and the peripheral region 102 can be formed simultaneously by photolithography using a single photomask. This significantly reduces the number of photomasks and process steps, which is beneficial for reducing manufacturing costs.

[0085] In some embodiments, please refer to Figure 1 The array substrate 100 provided in this application embodiment further includes a planarization layer 18, a common electrode 19, an insulating layer 20, and a pixel electrode 21 along the thickness direction of the array substrate 100. Specifically, the planarization layer 18 is disposed on the side of the interlayer dielectric layer 16 away from the gate insulating layer 14 and covers a third metal layer. The third metal layer also includes a common electrode lead (not shown in the figure), and the patterning of the third sub-line 313, the common electrode lead, and the source / drain electrode 17 can be completed by a photomask process.

[0086] Specifically, the common electrode 19 is disposed on the side of the planarization layer 18 away from the interlayer dielectric layer 16. The planarization layer 18 may be formed on the interlayer dielectric layer 16 after the third metal layer is patterned using a coating process. The planarization layer 18 may be a single-layer structure or a multi-layer structure, and this application does not limit this. For example, the planarization layer 18 may be a single-layer structure or a multi-layer structure formed by coating organic photoresist materials such as acrylates. In the thickness direction of the array substrate 100, a third via 108 and a fourth via (not shown in the figure) penetrating the planarization layer 18 are formed by a photolithography process. The third via 108 is used to expose the source and drain electrodes 17 of the thin-film transistor T, and the fourth via is used to expose the common electrode lead of the thin-film transistor T.

[0087] Specifically, the common electrode 19 is patterned on the side of the planarization layer 18 away from the interlayer dielectric layer 16, and is electrically connected to the common electrode lead in the third metal layer through a fourth via. Exemplarily, the common electrode 19 may be made of transparent contact-doped indium tin oxide (BITO) to provide a stable common voltage for the pixel structure of the array substrate 100.

[0088] Specifically, the insulating layer 20 is disposed on the side of the planarization layer 18 away from the interlayer dielectric layer 16 and covers the common electrode 19, and the insulating layer 20 at least partially fills the third via 108. The insulating layer 20 is used to isolate the common electrode 19 and the pixel electrode 21 to prevent them from short-circuiting. The insulating layer 20 may be deposited on the planarization layer 18 after the common electrode 19 is patterned using a plasma-enhanced chemical vapor deposition process. The insulating layer 20 may be a single-layer structure or a multi-layer structure, which is not limited in this application. Exemplarily, the insulating layer 20 may be a single-layer structure or a multi-layer structure formed by depositing inorganic non-metallic materials such as silicon nitride (SiNx) and silicon oxide (SiO2). In the thickness direction of the array substrate 100, the third via 108 is opened by a photolithography process to expose the source and drain electrodes 17, and the insulating layer 20 at least partially covers the sidewall 111 of the third via 108.

[0089] Specifically, the pixel electrode 21 is patterned on the side of the insulating layer 20 away from the planarization layer 18 and is electrically connected to the drain electrode 172 through the third via 108. For example, the pixel electrode 21 can be made of transparent titanium-doped indium tin oxide (TITO), allowing it to form an "electrode pair" with the underlying common electrode 19. This generates an electric field between the pixel electrode 21 and the common electrode 19 that can drive the deflection of liquid crystal molecules, thereby achieving driving control of the pixel structure.

[0090] In some embodiments, the metal traces 3 within the peripheral region 102 of the array substrate 100 provided in this application may further include a second metal trace (not shown in the figure) or a third metal trace (not shown in the figure), or may simultaneously include both a second metal trace and a third metal trace; this application does not limit this. Compared to the three-layer sub-line jump-over connection of the first metal trace 31, the second and third metal traces are wired using a double-layer sub-line jump-over connection method.

[0091] Specifically, the second metal trace includes a fourth sub-trace and a fifth sub-trace. The fourth sub-trace, the first sub-trace 311, and the light-shielding layer 11 are located in the same metal layer, i.e., within the aforementioned first metal layer; the fifth sub-trace, the third sub-trace 313, and the source / drain electrode 17 are located in the same metal layer, i.e., within the aforementioned third metal layer. The fifth sub-trace of the same second metal trace is bridged to the fourth sub-trace in the switching area 1022.

[0092] Specifically, the third metal trace includes a sixth sub-trace and a seventh sub-trace. The sixth sub-trace, the second sub-trace 312, and the gate 15 are located in the same metal layer, i.e., within the aforementioned second metal layer; the seventh sub-trace, the third sub-trace 313, and the source / drain 17 are located in the same metal layer, i.e., within the aforementioned third metal layer. The seventh sub-trace of the same third metal trace is bridged to the sixth sub-trace in the line-switching region 1022.

[0093] During the fabrication of the array substrate 100, the fourth sub-line, the first sub-line 311, and the light-shielding layer 11 of the thin-film transistor T are integrated on the first metal layer. The patterning of the fourth sub-line, the first sub-line 311, and the light-shielding layer 11 can be completed by a photomask process. The sixth sub-line, the second sub-line 312, and the gate 15 of the thin-film transistor T are integrated on the second metal layer. The patterning of the sixth sub-line, the second sub-line 312, and the gate 15 can be completed by a photomask process. The seventh sub-line, the fifth sub-line, the third sub-line 313, and the source / drain electrode 17 of the thin-film transistor T are integrated on the third metal layer. The patterning of the seventh sub-line, the fifth sub-line, the third sub-line 313, and the source / drain electrode 17 can be completed by a photomask process.

[0094] For the same second metal trace, at least a portion of the structure of the fifth sub-line serves as a bridging metal line at the top layer. Its orthographic projection on the substrate 10 at least partially overlaps with the orthographic projection of the fourth sub-line on the substrate 10, enabling the fifth sub-line to be electrically connected to the fourth sub-line via a corresponding via penetrating the interlayer medium in the vertical direction. For the same third metal trace, at least a portion of the structure of the seventh sub-line serves as a bridging metal line at the top layer. Its orthographic projection on the substrate 10 at least partially overlaps with the orthographic projection of the sixth sub-line on the substrate 10, enabling the seventh sub-line to be electrically connected to the sixth sub-line via a corresponding via penetrating the interlayer medium in the vertical direction. This allows two sub-lines belonging to different metal layers within the same second or third metal trace to be connected across layers. Furthermore, through methods such as three-dimensional crossings and interlayer jumpers, more metal traces 3 can be arranged within the limited wiring space of the peripheral area 102. Even when it is unsuitable to lay the first metal trace 31, the wiring requirements of different types of metal signal lines can be met through the second or third metal trace.

[0095] Those skilled in the art will understand that the second and third metal traces are only used to supplement wiring when it is not suitable to lay the first metal trace 31. It is not required that the array substrate 100 must include the second and third metal traces. In specific implementation, the second and third metal traces can be selected according to the actual situation. This application does not limit this.

[0096] According to a third aspect of this application, an embodiment of this application provides a display panel (not shown in the figures). The display panel can be a liquid crystal display (LCD) panel, which includes an array substrate and a counter substrate disposed opposite each other. The array substrate includes the array substrate 100 described in one of the above embodiments, and the counter substrate can be a color filter substrate, a BM substrate, a polarizer, or other film layers. The display panel provided by this application has all the beneficial effects of the array substrate 100 described above, which will not be repeated here.

[0097] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0098] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0099] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0100] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A thin-film transistor disposed on a substrate, characterized in that, It includes a light-shielding layer, an active layer, a gate, and source / drain electrodes arranged sequentially along the thickness direction of the thin-film transistor; The orthographic projection of the light-shielding layer on the substrate overlaps with the orthographic projection of a portion of the active layer on the substrate; The active layer includes: An extension portion, a portion of which overlaps with the light-shielding layer; and, The main body connects to the extension part; The width of the extension portion is greater than the width of the main body portion; The area of ​​the overlapping region between the extended portion and the light-shielding layer is S2, and the area of ​​the extended portion is S1. The relationship between S2 and S1 satisfies: 1 / 5×S1≤S2≤4 / 5×S1.

2. The thin-film transistor according to claim 1, characterized in that, The main body extends at least along a first direction, and the two extensions are connected to the two ends of the main body along the first direction; Wherein, the light-shielding layer extends along the second direction and overlaps with the main body along the thickness direction of the thin-film transistor; the first direction intersects with the second direction.

3. The thin-film transistor according to claim 2, characterized in that, The active layer includes: A channel portion is disposed on the main body portion and located between the oppositely arranged extension portions; the channel portion overlaps with the light-shielding layer; The doped regions are connected to both ends of the channel portion and are arranged opposite to each other along the first direction; The doped region is at least partially disposed on the main body and at least partially disposed on the extension.

4. The thin-film transistor according to claim 2, characterized in that, Along the first direction, the extension portion extends at least partially beyond the edge of the light-shielding layer; Along the second direction, the extension extends at least partially beyond the edge of the main body.

5. The thin-film transistor according to claim 4, characterized in that, The extension includes at least one shape selected from circles, ellipses, regular polygons, and irregular shapes.

6. The thin-film transistor according to claim 4, characterized in that, Along the second direction, the edge of the light-shielding layer is an outer arc-shaped edge, an inner arc-shaped edge, or a toothed edge, wherein the edge structures on both sides of the light-shielding layer are the same or different.

7. An array substrate, characterized in that, include: The substrate has an array region and a peripheral region adjacent to the array region; A thin-film transistor, including the thin-film transistor according to any one of claims 1-6, wherein the thin-film transistor array is disposed on the substrate and located within the array region.

8. The array substrate according to claim 7, characterized in that, The array substrate further includes: Metal traces are arranged on the substrate and located within the peripheral area, the metal traces comprising: The first metal trace includes a first sub-line, a second sub-line, and a third sub-line sequentially arranged along the thickness direction of the thin-film transistor. The first sub-line is located in the same metal layer as the light-shielding layer, the second sub-line is located in the same metal layer as the gate, and the third sub-line is located in the same metal layer as the source and drain. The third sub-line of the same first metal trace bridges the second sub-line and the first sub-line.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 7 to 8.

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