An optoelectronic hermetic 3D packaging structure

Abstract

This invention belongs to the field of chip packaging technology, specifically relating to a 3D packaging structure for optoelectronic co-packaging, including a substrate. A first adapter plate is disposed on a first surface of the substrate. At least one second adapter plate and at least one optical chip are disposed on the first surface of the first adapter plate. An electrical chip is disposed on the first surface of the second adapter plate and the optical chip. A first gap exists between the second adapter plate and the optical chip. The electrical chip crosses the first gap and is connected to the second adapter plate and the optical chip respectively. This application provides a cross-connection structure for chip packaging structures with more complex functions or larger data processing volumes. While improving heat dissipation performance, it enables the system to dynamically optimize signal transmission according to task requirements, thereby comprehensively improving the performance, reliability, and flexibility of the packaging structure.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically relating to a 3D packaging structure for optoelectronic co-packaging. Background Technology

[0002] With the continuous development of integrated circuit technology, three-dimensional (3D) packaging technology has gradually become an important direction for high-performance chip packaging due to its advantages in improving integration density, shortening interconnect length, and improving signal integrity. In the field of optoelectronic integration, packaging optical chips and electrical chips together has become a key path to achieve high-speed, high-bandwidth data communication.

[0003] However, existing optoelectronic 3D packaging structures mostly employ a one-to-one stacking of optical and electrical chips on a silicon interposer. In this structure, signals must be transmitted via a directional path between the optical and electrical chips, resulting in a single signal path and poor flexibility. Furthermore, since all signals must interact with the optical chip through a specific electrical chip, the chip experiences concentrated workload when processing high-speed data, easily creating a performance bottleneck and limiting the long-term reliability of the overall system.

[0004] For example, the applicant's earlier application CN119224947B discloses a photoelectric chip packaging structure, including a substrate, a signal transmission layer disposed on the upper surface of the substrate, and a signal processing layer disposed on the signal transmission layer; the signal transmission layer includes: at least one first electrical chip, the first electrical chip having a first surface and a second surface, the first surface being disposed facing the substrate, and the second surface being disposed facing the signal processing layer; the signal processing layer includes: a signal conversion region and a data storage region; at least one optical chip is correspondingly disposed in the signal conversion region, the optical chip including: N*M photonic computing units, the photonic computing unit including: an optical waveguide layer, a modulation layer located on the optical waveguide layer, the modulation layer being a phase change material layer or the modulation layer including a phase change material layer; the optical chip is used to receive the modulation signal input by the first electrical chip, at least one group of the photonic computing units responding to the modulation signal modulates the corresponding phase change material layer to a specific state, and the photonic computing unit completes the corresponding calculation task in the specific state and outputs the corresponding calculation data.

[0005] This solution adopts a structure that carries multiple small chips on a large chip (such as a "one-on-many" packaging scheme). For this type of packaging structure with optimized position and function (or distributed chip setup structure), the invention also provides a multi-level task allocation rule to coordinate and maintain the power consumption and operational stability of this distributed chip setup structure, thereby simplifying the packaging structure and improving its stability.

[0006] However, the core architecture of the above solution is still a stacked structure of optical and electrical chips. Furthermore, the applicant discovered during actual use that it still suffers from at least the following problems: significantly limited data processing efficiency and insufficient heat dissipation. Summary of the Invention

[0007] The purpose of this invention is to provide a 3D packaging structure for optoelectronic encapsulation, so as to partially alleviate or solve the above-mentioned problems, thereby improving data processing efficiency and heat dissipation.

[0008] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution:

[0009] A 3D packaging structure for optoelectronic co-encapsulation includes:

[0010] A substrate, wherein a first adapter plate is disposed on a first surface of the substrate, at least one second adapter plate and at least one optical chip are disposed on the first surface of the first adapter plate, an electrical chip is disposed on the first surface of the second adapter plate and the optical chip, a first gap is provided between the second adapter plate and the optical chip, and the electrical chip is connected to the second adapter plate and the optical chip respectively across the first gap;

[0011] A first interconnection structure is provided between the first adapter board and the substrate, a second interconnection structure is provided between the second adapter board and the first adapter board, a third interconnection structure is provided between the electrical chip and the second adapter board, and a fourth interconnection structure is provided between the electrical chip and the optical chip. The first to fourth interconnection structures are all configured to enable signal conduction, so that a first signal transmission path is formed between the substrate, the first interconnection structure, the first adapter board, the second interconnection structure, the second adapter board, the third interconnection structure, the electrical chip, the fourth interconnection structure, and the optical chip.

[0012] As an improvement, a fifth interconnection structure is provided between the first adapter board and the optical chip. The fifth interconnection structure is configured to enable signal conduction, and a second signal transmission path is formed between the substrate, the first interconnection structure, the first adapter board, the fifth interconnection structure, and the optical chip.

[0013] As an improvement, the electrical chip is provided with a first functional area and a second functional area. The first functional area integrates a receiver, a transmitter, a transimpedance amplifier, and a digital interface. The second functional area integrates a power supply, a clock, a driver, a ground terminal, a digital-to-analog converter, and an analog-to-digital converter. The first functional area is located close to the optical chip, and the second functional area is located close to the second adapter board.

[0014] As an improvement, the first surface of the optical chip is divided into a first region and a second region, the electrical chip is located above the first region, and the second region is provided with an optical fiber array interface.

[0015] As an improvement, at least two second adapter boards are provided, with the at least two second adapter boards located on the first side and the third side of the optical chip respectively, and the first side and the third side being arranged opposite to each other; correspondingly, at least two electrical chips are provided, with a second gap between two adjacent electrical chips.

[0016] As an improvement, both the first and second adapter boards are silicon adapter boards.

[0017] As an improvement, a connection layer is provided between the optical chip and the first adapter board, and the connection layer is filled with dielectric adhesive material.

[0018] As an improvement, the first to fifth interconnect structures are selected from at least one of bumps, through-silicon vias, bonding wires, solder balls, or hybrid bonding structures.

[0019] As an improvement, the electrical chip is selected from at least one of wDAC chip, xADC chip, xDAC chip, ASCII chip, and I / O chip.

[0020] As an improvement, the dielectric adhesive material is a DAF film.

[0021] The principle and beneficial technical effects of this invention are as follows:

[0022] Unlike the stacked structures mentioned above, this application provides a cross-connect structure for chip packaging structures with more complex functions or larger data processing volumes. While improving heat dissipation performance, it enables the system to dynamically optimize signal transmission according to task requirements, thereby comprehensively improving the performance, reliability and flexibility of the packaging structure.

[0023] Specifically, this solution achieves cross-connection by using an electrical chip to bridge the first gap and partially overlap the second adapter board with the optical chip, providing sufficient heat dissipation space for components (especially the optical chip, which is the core component of the computing unit).

[0024] Furthermore, the aforementioned structure creates signal transmission paths of varying lengths. For tasks requiring high data processing speeds, a shorter second signal transmission path can be selected; conversely, for tasks requiring slower data processing speeds, a shorter first signal transmission path can be chosen. In addition, this solution partitions the internal structure of the electronic chip, matching different signal transmission paths to different functions. In other words, a distribution scheme with different path lengths is also provided within the electronic chip. Specifically, components with higher speed requirements (such as receivers, transmitters, transimpedance amplifiers, and digital interfaces) are placed in the shorter first region, while components with lower processing speed requirements (such as power supplies, clocks, drivers, grounding terminals, digital-to-analog converters, and analog-to-digital converters) are placed in the longer second region. This solution provides a dual-path selection scheme, preventing heat buildup at the source while ensuring efficient data transmission and processing. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0026] Figure 1 This is a side view of a 3D packaging structure in an exemplary embodiment of the present invention;

[0027] Figure 2 This is a side view of the 3D packaging structure in another exemplary embodiment of the present invention;

[0028] Figure 3 This is a top view of the 3D packaging structure in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the partition structure of the electrical chip in an embodiment of the present invention;

[0030] Figure 5 This is a flowchart illustrating the working method of the 3D packaging structure in an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the modular structure of the working system of the 3D packaging structure in an embodiment of the present invention.

[0032] In the diagram, the markings are as follows: 100, substrate; 200, first adapter board; 300, second adapter board; 400, optical chip; 410, first region; 420, second region; 500, electrical chip; 510, first functional area; 520, second functional area; 610, first interconnect structure; 620, second interconnect structure; 630, third interconnect structure; 640, fourth interconnect structure; 650, fifth interconnect structure; 700, optical fiber; 800, first gap; 900, second gap. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0034] In this document, suffixes such as "module," "component," or "unit" used to denote elements are used solely for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "component," or "unit" may be used interchangeably. In this document, terms such as "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," and "connected," etc., should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. In this document, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0036] In this article, the first surface is also the upper surface, and the second surface is also the lower surface.

[0037] Example 1

[0038] This embodiment is basically as shown in the appendix. Figure 1-4 As shown:

[0039] See Figure 1 This embodiment provides a 3D packaging structure for optoelectronic bonding, including a substrate 100 as a support structure. A first adapter plate 200 is disposed on a first surface of the substrate 100. At least one second adapter plate 300 and at least one optical chip 400 are disposed on the first surface of the first adapter plate 200. An electrical chip 500 is disposed on the first surface of the second adapter plate 300 and the optical chip 400. A first gap 800 is provided between the second adapter plate 300 and the optical chip 400. The electrical chip 500 spans the first gap 800 and is connected to both the second adapter plate 300 and the optical chip 400. That is, the optical chip 400 and the electrical chip 500 are directly interconnected. Through the above-mentioned spanning gap connection method, heat dissipation space is provided for this packaging structure.

[0040] A first interconnection structure 610 is provided between the first adapter board 200 and the substrate 100; a second interconnection structure 620 is provided between the second adapter board 300 and the first adapter board 200; a third interconnection structure 630 is provided between the electrical chip 500 and the second adapter board 300; and a fourth interconnection structure 640 is provided between the electrical chip 500 and the optical chip 400. All four interconnection structures 640 are configured to enable signal conduction, thereby forming a first signal transmission path among the substrate 100, the first interconnection structure 610, the first adapter board 200, the second interconnection structure 620, the second adapter board 300, the third interconnection structure 630, the electrical chip 500, the fourth interconnection structure 640, and the optical chip 400 (see [link to documentation]). Figure 1 and Figure 2 Path a in the middle.

[0041] In other words, unlike the stacked structure in existing technologies, this invention provides a cross-connection structure. Through the cooperation between the second adapter board and the optical chip, and the direct bridging of electrical chips on top of it, on the one hand, the first gap formed between the second adapter board and the optical chip, and the second gap formed between multiple electrical chips (if any), serve as channels for heat convection and radiation, which can improve the heat dissipation performance of the packaging structure. On the other hand, with the rapid development of modern computer networks, higher requirements are placed on chip performance. The above-mentioned cross-connection solution enables multiple electrical chips to be integrated with the optical chip at the same time. That is, even if the size of the optical chip is limited or the packaging capability is limited, and it is not possible to manufacture larger-sized optical chips, the need for efficient heat dissipation under the requirements of large data transmission and processing can still be met.

[0042] In some embodiments, see Figure 2A fifth interconnect structure 650 is provided between the first adapter board 200 and the optical chip 400. The fifth interconnect structure 650 is configured to enable signal conduction. A second signal transmission path is formed between the substrate 100, the first interconnect structure 610, the first adapter board 200, the fifth interconnect structure 650, and the optical chip 400 (see...). Figure 2 Path b in the text.

[0043] In this process, an external controller or the logic circuit inside the chip can guide the signal to select a shorter second signal transmission path or a longer first signal transmission path, based on the signal type (such as high-speed data signal / low-speed control signal) or task load, by controlling the switching circuit or pre-designed wiring rules.

[0044] In other words, this application also provides a dual-path scheme, which forms signal transmission paths of different lengths through the above structure. For task types with high data processing speed requirements, a second signal transmission path with a shorter signal transmission path can be selected. Correspondingly, for task types with low data processing speed requirements, a first signal transmission path with a shorter signal transmission path can be selected, thereby optimizing the flexibility of data processing and alleviating the serious heat generation problem caused by excessive concentration of data transmission pressure to a certain extent.

[0045] In some embodiments, the electrical chip 500 has internal functional partitions, such as... Figure 4 As shown, the electrical chip 500 is provided with a first functional area 510 and a second functional area 520. The first functional area 510 integrates a receiver, a transmitter, a transimpedance amplifier, and a digital interface. The second functional area 520 integrates a power supply, a clock, a driver, a ground terminal, a digital-to-analog converter, and an analog-to-digital converter. The first functional area 510 is located near the optical chip 400, and the second functional area 520 is located near the second adapter board 300. In other words, the electrical chip is divided into a first functional area 510 and a second functional area 520. The optical chip is connected to the first functional area through a fourth interconnection structure, and the second adapter board is connected to the second functional area through a third interconnection structure.

[0046] Specifically, signals from the second adapter board 300 that require high-speed interaction with the optical chip 400 can be processed directly in the first functional area 510 within the electrical chip 500 with the shortest wiring distance, and then quickly output to the optical chip 400 through the fourth interconnect structure 640 below it. For signals that need to be processed in the second functional area 520 (such as power distribution and clock driving), the signals need to be transmitted from the entry point within the electrical chip 500 to the second functional area 520, which is relatively far from the optical chip 400, for processing. After processing, they can then be routed to the first functional area or directly managed via a potentially longer internal path, as needed.

[0047] Therefore, this application creates a dual-path system within the electronic chip by partitioning low-speed and high-speed components. Specifically, components with higher speed requirements (such as receivers, transmitters, transimpedance amplifiers, and digital interfaces) are placed in the first region with a shorter path, while components with lower processing speed requirements (such as power supplies, clocks, drivers, grounding terminals, digital-to-analog converters, and analog-to-digital converters) are placed in the second region with a longer path. In other words, this application further optimizes the flexibility of data processing by providing a dual-path selection scheme.

[0048] In some embodiments, the first surface of the optical chip 400 is divided into a first region 410 and a second region 420. The electrical chip 500 is located above the first region 410. The second region 420 is provided with an exposed fiber optic array interface with its entrance facing upwards, for connection to an external optical fiber 700 to realize the input and output of optical signals. By partitioning the optical chip, heat dissipation is improved while facilitating the access of external optical fibers. Preferably, the external optical fiber is vertically connected to the fiber optic array interface.

[0049] In some embodiments, at least two second adapter boards 300 are provided, and the at least two second adapter boards 300 are respectively located on the first side and the third side of the optical chip 400, with the first side and the third side being disposed opposite to each other; correspondingly, at least two electrical chips 500 are provided, and a second gap 900 is provided between two adjacent electrical chips 500.

[0050] In some embodiments, both the first adapter plate 200 and the second adapter plate 300 are silicon adapter plates. Of course, in other embodiments, the adapter plates may also be made of other materials, such as glass adapter plates.

[0051] In some embodiments, a connection layer is provided between the optical chip 400 and the first adapter plate 200, the connection layer being filled with a dielectric adhesive material (preferably a DAF film, i.e., Die Attach Film; other materials may also be used). This provides adhesion and insulation between the optical chip 400 and the first adapter plate 200, while also providing mechanical stability.

[0052] In some embodiments, the electrical chip 500 is selected from at least one of a wDAC chip, an xADC chip, an xDAC chip, an ASIC chip, and an I / O chip. When multiple electrical chips are available, these chips can be combined to adapt to different application scenarios. Specifically, a wDAC chip refers to a weighted digital-to-analog converter chip; an xADC chip refers to an arbitrary or programmable analog-to-digital converter chip; an xDAC chip refers to an arbitrary or programmable digital-to-analog converter chip; an ASIC chip refers to an application-specific integrated circuit chip; and an I / O chip refers to an input / output interface chip.

[0053] In some embodiments, the first to fifth interconnect structures 650 are selected from at least one of bumps, through-silicon vias, bonding wires, solder balls, or hybrid bonding structures, and can be selected according to specific needs to achieve reliable electrical connections.

[0054] In some embodiments, the 3D packaging structure for optoelectronic encapsulation in this embodiment also includes the various modules of the working system in Embodiment 3.

[0055] In summary, the optoelectronic 3D packaging structure of this embodiment bridges the second adapter board 300 and the optical chip 400 across the first gap 800 using the electrical chip 500, achieving a bridging interconnect. This not only provides ample heat dissipation space for the optical chip 400 but also achieves dynamic optimization of signal transmission through dual signal transmission paths (the first signal transmission path and the second signal transmission path). The functional partitioning of the electrical chip 500 further matches components with different speed requirements, preventing heat accumulation from the source and improving data processing efficiency and system reliability. The aforementioned "bridging" is achieved through the structural strength of the electrical chip itself and the support of the interconnect structures at both ends. This layout avoids setting up complex vertical interconnects directly below the gap, thereby simplifying the process and creating a heat dissipation channel.

[0056] Example 2

[0057] See Figure 5 This embodiment provides a working method for a 3D packaging structure for optoelectronic encapsulation, based on the 3D packaging structure for optoelectronic encapsulation in Embodiment 1, including the following steps:

[0058] S100, obtain the task processing volume in the current work task; wherein, the task processing volume may be the number of data packets to be processed, the total data size, or the number of calculation operations, etc.

[0059] S200: Determine whether the task processing volume exceeds the preset data processing volume. If so, it indicates that the system is facing a high-load task, and the first signal transmission path and the second signal transmission path are simultaneously activated. Otherwise, proceed to step S300. The preset data processing volume can be pre-set by the user or system designer based on the theoretical maximum throughput of the encapsulation structure, historical operating data statistics, or the performance requirements of a specific application scenario. For example, this threshold can be set to 60%-80% of the system's saturated processing capacity to ensure that the dual-path parallel mode is activated in advance before a high load occurs, avoiding a sudden performance drop.

[0060] S300, obtain the number of Category 1 and Category 2 tasks in the current work tasks, wherein the processing speed requirement of Category 1 tasks is greater than that of Category 2 tasks; wherein, Category 1 tasks may be artificial intelligence model calculation, real-time data stream processing, etc.; and Category 2 tasks may be system status recording, data storage management, device control command execution, etc.

[0061] S400, determine whether the number of the first type of task is greater than the number of the second type of task. If so, open the second signal transmission path and close the first signal transmission path; otherwise, open the first signal transmission path and close the second signal transmission path.

[0062] In other words, this application provides a dual-path selection scheme. First, it performs an initial screening based on the workload. When the workload is large, both channels (the first and second signal transmission paths) are activated simultaneously to meet operational requirements while mitigating heat concentration to some extent. Furthermore, when only one channel needs to be activated, the task is divided according to its type. The second signal transmission path (via the optical chip) provides a more direct and lower-latency channel for high-speed signals. Prioritizing this path for high-speed tasks fully leverages the advantages of optical transmission, meeting stringent processing speed requirements and optimizing the system's response performance to high-priority tasks. For tasks with moderate speed requirements, the first signal transmission path (electrical interconnect path) is sufficient. Disabling the second signal transmission path related to the optical chip allows the optical chip to enter a low-power state, directly reducing overall system power consumption and operating heat, extending the optical chip's lifespan, and improving heat dissipation within the packaging structure.

[0063] In some embodiments, the steps further include:

[0064] S500, obtain the operating temperature of the optical chip; wherein, the operating temperature can be obtained in real time by a temperature sensor integrated near or inside the optical chip.

[0065] S510, determine whether the operating temperature exceeds a preset temperature threshold (e.g., 85°C). If so, close the second signal transmission path and open the first signal transmission path. When the operating temperature is detected to return to below the preset temperature threshold again, switch the signal transmission path from the first signal transmission path back to the second signal transmission path. The preset temperature threshold is mainly determined by the reliable operating temperature range of the optical chip, material properties, and the heat dissipation capacity of the package. It can be set by the user after obtaining the maximum junction temperature (Tjmax) from the optical chip's product specifications and reserving a certain safety margin (e.g., 10°C to 15°C below Tjmax).

[0066] In other words, this application also provides an active thermal management strategy. When the optical chip overheats due to continuous high-load operation, the system can promptly switch it out of the working circuit, allowing it to "rest" and cool down, while the first signal transmission path takes over the data transmission task. This effectively prevents the optical chip from being damaged by overheating, greatly improves the reliability and stability of the system under high-temperature environments or long-term high-load operation, and achieves a dynamic balance between performance and heat dissipation.

[0067] In some embodiments, the working method further includes the step of:

[0068] S600, periodically sends detection signals to the first signal transmission path and / or the second signal transmission path. For example, a detection signal such as a heartbeat packet or test sequence is sent every 2 seconds.

[0069] S610, determine whether a response signal corresponding to the detection signal is received within a preset time; if yes, maintain the current working state; otherwise, mark the path as a fault path, mark the other paths as normal paths, close the fault path, and open the normal path.

[0070] In other words, this application also provides a fault self-checking mechanism. Even if a signal path fails due to physical damage, aging or other reasons, the system can automatically detect it and quickly switch to a healthy backup path, ensuring the continuity of data transmission and the availability of system services, reducing dependence on external intervention, and is particularly suitable for application scenarios that require high reliability.

[0071] In some embodiments, after S610, the following step is further included:

[0072] If both the first and second signal transmission paths are determined to be in a closed state (or both marked as faulty paths), the user is prompted to inspect or replace them (e.g., through indicator lights or management software interface). Otherwise, the current operating mode is maintained. When both paths fail, the user is promptly notified to prevent the system from operating silently in a completely failed state, facilitating rapid problem location and maintenance.

[0073] In some embodiments, the electrical chip is provided with a first functional area and a second functional area. The first functional area integrates a receiver, a transmitter, a transimpedance amplifier, and a digital interface. The second functional area integrates a power supply, a clock, a driver, a ground terminal, a digital-to-analog converter, and an analog-to-digital converter. The optical chip is connected to the first functional area, and the second adapter board is connected to the second functional area. Accordingly, a first sub-path is formed between the substrate, the first adapter board, the second adapter board, the first functional area of ​​the electrical chip, and the optical chip. This path is a pure digital high-speed path, mainly designed for low latency and high bandwidth requirements. A second sub-path is formed between the substrate, the first adapter board, the second adapter board, the second functional area of ​​the electrical chip, and the optical chip. This path is mainly used to handle tasks that do not require high speed but require stable power supply or analog interaction. The working method further includes:

[0074] S700, determine whether the first signal transmission path is in an open state; if so, proceed to S710.

[0075] S710, acquire the data type that has passed through the first signal transmission path, the data type includes a first type of data and a second type of data; the processing speed requirement time for the first type of data is less than the processing speed requirement time for the second type of data, that is, the first type of data refers to data that requires high speed and low latency (such as core computing instructions and cache synchronization data), and the second type of data refers to data with relatively low speed requirements (such as device status control signals and analog-to-analog conversion data collected by sensors).

[0076] S720, Match the corresponding sub-channel according to the data type, wherein when the data type is a type 1 data, the type 1 data is assigned to the first sub-path for transmission, and when the data type is a type 2 data, the type 2 data is assigned to the second sub-path for transmission.

[0077] In other words, this application provides a multi-level signal routing and allocation mechanism. First, data is allocated from the packaging level to the first / second signal transmission path. Then, the data entering the first signal transmission path is allocated at the chip level inside the chip. Through multi-level path selection, the optimal distribution of data flow at the macro and micro levels is achieved, while providing high flexibility and scalability to cope with more complex and diverse computing tasks.

[0078] In summary, this application provides a multi-level path selection scheme for the 3D packaging structure of cross-type optoelectronic co-packaging, which controls temperature, faults, and other aspects. While improving heat dissipation performance, it enables the system to dynamically optimize signal transmission according to task requirements, thereby comprehensively improving the performance, reliability, and flexibility of the packaging structure.

[0079] Example 3

[0080] This embodiment provides a working system for a 3D packaging structure for optoelectronic encapsulation, based on the 3D packaging structure for optoelectronic encapsulation in Embodiment 1 or the working method in Embodiment 2, including:

[0081] The first data acquisition module is configured to acquire the amount of tasks processed in the current work task.

[0082] The first processing module is configured to determine whether the task processing volume is greater than the preset data processing volume; if so, the first signal transmission path and the second signal transmission path are opened simultaneously.

[0083] The second data acquisition module is configured to acquire the number of type I and type II tasks in the current work task when the task processing volume is less than or equal to a preset data processing volume, wherein the processing speed requirement of type I tasks is greater than the processing speed requirement of type II tasks.

[0084] The second processing module is configured to determine whether the number of the first type of tasks is greater than the number of the second type of tasks. If so, the second signal transmission path is opened and the first signal transmission path is closed; otherwise, the first signal transmission path is opened and the second signal transmission path is closed.

[0085] In some embodiments, it also includes:

[0086] Temperature monitoring module: configured to acquire the operating temperature of the optical chip.

[0087] The third processing module is configured to determine whether the operating temperature exceeds a preset temperature threshold. If so, it closes the second signal transmission path and opens the first signal transmission path.

[0088] In some embodiments, it also includes:

[0089] The detection module is configured to periodically send detection signals to the first signal transmission path and / or the second signal transmission path; and determine whether a response signal corresponding to the detection signal is received within a preset time; if so, maintain the current working state; otherwise, mark the path as a fault path, mark the other paths as normal paths, close the fault path, and open the normal path.

[0090] In some embodiments, it also includes:

[0091] The prompting module is configured to determine whether both the first signal transmission path and the second signal transmission path are in a closed state. If so, it prompts the user to perform maintenance or replacement; otherwise, it maintains the current working mode.

[0092] In some embodiments, it also includes:

[0093] Line allocation module: configured to be used when the first signal transmission path is in the open state;

[0094] The data type transmitted through the first signal transmission path is obtained. This data type includes two categories: Category I data and Category II data. The processing speed requirement for Category I data is shorter than that for Category II data. Specifically, Category I data refers to data requiring high speed and low latency (such as core computing instructions and cache synchronization data), while Category II data refers to data with relatively lower speed requirements (such as device status control signals and analog-to-digital conversion data collected by sensors). A corresponding sub-channel is matched based on the data type. When the data type is Category I data, it is assigned to the first sub-path for transmission; when the data type is Category II data, it is assigned to the second sub-path for transmission.

[0095] In summary, this application provides a multi-level path selection scheme for the 3D packaging structure of cross-type optoelectronic co-packaging, which controls temperature, faults, and other aspects. While improving heat dissipation performance, it enables the system to dynamically optimize signal transmission according to task requirements, thereby comprehensively improving the performance, reliability, and flexibility of the packaging structure.

[0096] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0097] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A 3D packaging structure for optoelectronic bonding, characterized in that, include: A substrate (100) has a first adapter plate (200) disposed on its first surface. The first adapter plate (200) has at least one second adapter plate (300) and at least one optical chip (400) disposed on its first surface. An electrical chip (500) is disposed on the first surfaces of the second adapter plate (300) and the optical chip (400). A first gap (800) is provided between the second adapter plate (300) and the optical chip (400). The electrical chip (500) crosses the first gap (800) and is connected to the second adapter plate (300) and the optical chip (400) respectively. A first interconnection structure (610) is provided between the first adapter board (200) and the substrate (100), a second interconnection structure (620) is provided between the second adapter board (300) and the first adapter board (200), a third interconnection structure (630) is provided between the electrical chip (500) and the second adapter board (300), and a fourth interconnection structure (640) is provided between the electrical chip (500) and the optical chip (400). The first to fourth interconnection structures (640) are all configured to enable signal conduction, so that a first signal transmission path is formed between the substrate (100), the first interconnection structure (610), the first adapter board (200), the second interconnection structure (620), the second adapter board (300), the third interconnection structure (630), the electrical chip (500), the fourth interconnection structure (640), and the optical chip (400). A fifth interconnection structure (650) is provided between the first adapter board (200) and the optical chip (400). The fifth interconnection structure (650) is configured to enable signal conduction. A second signal transmission path is formed between the substrate (100), the first interconnection structure (610), the first adapter board (200), the fifth interconnection structure (650), and the optical chip (400).

2. The 3D packaging structure for optoelectronic bonding according to claim 1, characterized in that, The electrical chip (500) is provided with a first functional area (510) and a second functional area (520). The first functional area (510) integrates a receiver, a transmitter, a transimpedance amplifier and a digital interface. The second functional area (520) integrates a power supply, a clock, a driver, a ground terminal, a digital-to-analog converter and an analog-to-digital converter. The first functional area (510) is located close to the optical chip (400) and the second functional area (520) is located close to the second adapter board (300).

3. The 3D packaging structure for optoelectronic bonding according to claim 1, characterized in that, The first surface of the optical chip (400) is divided into a first region (410) and a second region (420), the electrical chip (500) is located above the first region (410), and the second region (420) is provided with an optical fiber array interface.

4. The 3D packaging structure for optoelectronic bonding according to claim 1, characterized in that, At least two second adapter boards (300) are provided, and the at least two second adapter boards (300) are respectively located on the first side and the third side of the optical chip (400), with the first side and the third side being arranged opposite to each other; correspondingly, at least two electrical chips (500) are provided, and there is a second gap (900) between two adjacent electrical chips (500).

5. The 3D packaging structure for optoelectronic bonding according to claim 1, characterized in that, Both the first adapter board (200) and the second adapter board (300) are silicon adapter boards.

6. The 3D packaging structure for optoelectronic bonding according to claim 1, characterized in that, A connection layer is provided between the optical chip (400) and the first adapter board (200), and the connection layer is filled with dielectric adhesive material.

7. The 3D packaging structure for optoelectronic bonding according to claim 1, characterized in that, The first to fifth interconnect structures are selected from at least one of bumps, through-silicon vias, bonding wires, solder balls, or hybrid bonding structures.

8. The 3D packaging structure for optoelectronic bonding according to claim 1, characterized in that, The electrical chip (500) is selected from at least one of the following: wDAC chip, xADC chip, xDAC chip, ASIC chip, and I / O chip.

9. The 3D packaging structure for optoelectronic bonding according to claim 6, characterized in that, The dielectric adhesive material is a DAF film.

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