Diode chip, light emitting diode, device and method of manufacturing a diode chip

Abstract

The application provides a diode chip, a light emitting diode, an apparatus and a manufacturing method of the diode chip, and applies to the technical field of semiconductors. The diode chip comprises a support layer, an active layer, a p-type contact layer, an electron blocking layer and an n-type contact layer, the active layer is arranged at a first region of one side of the support layer along a first direction, the p-type contact layer is arranged at a second region of one side of the support layer along the first direction, the p-type contact layer is in contact with the active layer, the electron blocking layer is arranged at one side of the active layer away from the support layer, and the n-type contact layer is arranged at one side of the electron blocking layer away from the active layer. The diode chip provided by the application can not only increase the number of p-type carriers entering the active layer, but also reduce the number of n-type carriers entering the active layer, so that the symmetry of the p-type carriers and the n-type carriers in the active layer is improved, and the light emitting efficiency of the diode chip is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a diode chip, a light-emitting diode, a device, and a method for manufacturing a diode chip. Background Technology

[0002] Currently, light-emitting diodes (LEDs) are widely used in air purification, sterilization, biochemical detection, and optical communication. The diode chip in an LED mainly consists of an n-type contact layer, an active layer, and a p-type contact layer. The n-type and p-type contact layers provide n-type and p-type charge carriers to the active layer, respectively. The n-type and p-type charge carriers recombine in the active layer to emit light.

[0003] With the continuous advancement of technology, the wavelength of light emitted by light-emitting diodes (LEDs) is getting shorter and shorter. As the wavelength becomes shorter, the asymmetry between p-type and n-type charge carriers in the active layer becomes more and more significant, resulting in lower luminous efficiency of LEDs. Summary of the Invention

[0004] This application provides a diode chip, a light-emitting diode, a device, and a method for manufacturing a diode chip, which can improve the luminous efficiency of the light-emitting diode.

[0005] In a first aspect, a diode chip is provided, comprising: Support layer; An active layer is disposed in a first region on one side of the support layer along a first direction; A p-type contact layer is disposed in a second region on one side of the support layer along the first direction, and the p-type contact layer is in contact with the active layer. An electron blocking layer is disposed on the side of the active layer opposite to the support layer; An n-type contact layer is disposed on the side of the electron blocking layer opposite to the active layer.

[0006] Optionally, the p-type contact layer includes a first portion and a second portion, the first portion and the second portion being respectively disposed on both sides of the active layer along a second direction, the second direction being perpendicular to the first direction.

[0007] Optionally, the p-type contact layer is disposed around the periphery of the active layer.

[0008] Optionally, the p-type contact layer may be formed using gallium nitride.

[0009] Optionally, the forming material of the n-type contact layer includes aluminum gallium nitride, and the molar fraction of aluminum in the n-type contact layer is less than or equal to 50%.

[0010] Optionally, the electron blocking layer is formed of aluminum gallium nitride, wherein the molar fraction of aluminum in the electron blocking layer is greater than or equal to 70%.

[0011] Optionally, the support layer includes a base layer and a transition layer disposed sequentially along the first direction, and the active layer and the p-type contact layer are disposed on the side of the transition layer opposite to the base layer; The transition layer is formed of undoped aluminum gallium nitride, and the size of the transition layer along the first direction is less than or equal to 200 nanometers.

[0012] This application provides a diode chip in which a p-type contact layer is disposed on the side of the active layer, directly contacting the active layer. This allows p-type charge carriers to enter the active layer directly without passing through the electron blocking layer, thereby increasing the number of p-type charge carriers entering the active layer. Furthermore, the n-type contact layer in this diode chip is disposed on the side of the electron blocking layer away from the active layer. This blocking layer can prevent some n-type charge carriers from entering the active layer, reducing the number of n-type charge carriers entering the active layer.

[0013] In short, the diode chip provided in this application embodiment can not only increase the number of p-type carriers entering the active layer, but also reduce the number of n-type carriers entering the active layer. This reduces the quantity deviation between p-type and n-type carriers in the active layer, improves the symmetry of p-type and n-type carriers in the active layer, and further improves the recombination efficiency of p-type and n-type carriers in the active layer, thereby improving the luminous efficiency of the diode chip.

[0014] In a second aspect, a light-emitting diode is provided, comprising the diode chip described in the first aspect.

[0015] Thirdly, an apparatus is provided, comprising: a light-emitting diode as described in the second aspect.

[0016] Fourthly, a method for manufacturing a diode chip is provided, the method comprising: Form a support layer; An active layer is formed in a first region on one side of the support layer along the first direction; A p-type contact layer is formed in a second region on one side of the support layer along the first direction, and the p-type contact layer is in contact with the active layer; An electron blocking layer is formed on the side of the active layer opposite to the support layer; An n-type contact layer is formed on the side of the electron blocking layer opposite to the active layer.

[0017] Optionally, the second region is located at both ends of the first region along a second direction, the second direction being perpendicular to the first direction; The second region of the support layer along one side of the first direction forms a p-type contact layer, including: The pre-formed n-type contact layer and the electron blocking layer are etched to expose the first end and the second end of the active layer that are disposed opposite to each other along the second direction. The first end facing away from the second end is etched, and the second end facing away from the first end is etched to expose the second region; The p-type contact layer is formed in the exposed second region.

[0018] Optionally, the first region is located in the central region of the support layer, and the second region is located on the periphery of the first region; A p-type contact layer is formed in a second region on one side of the support layer along the first direction, comprising: The edges of the pre-formed n-type contact layer and the electron blocking layer are etched to expose the edges of the active layer. The edges of the active layer are etched to expose the second region; The p-type contact layer is formed in the exposed second region. Attached Figure Description

[0019] Figure 1 A schematic diagram of the epitaxial structure included in a diode chip in the related art is shown; Figure 2 This illustration shows a schematic diagram of an epitaxial structure included in a diode chip according to an embodiment of this application; Figure 3 It shows Figure 2 A partially enlarged schematic diagram of the area between the active layer and the p-type contact layer is shown. Figure 4 This illustration shows a schematic diagram of an epitaxial structure included in another diode chip provided in an embodiment of this application; Figure 5 A schematic diagram illustrating a method for manufacturing a diode chip according to an embodiment of this application; Figure 6-11 for Figure 2 The diagram shows the manufacturing process of a diode chip. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] It should be understood that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., in this specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge scope of those skilled in the art.

[0022] It should be understood that the terms “first,” “second,” etc., may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0023] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0024] Furthermore, the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means directly “on” something, but also includes “on” something with an intermediate feature or layer in between. Furthermore, “above” or “over” not only means “above” or “over” something, but can also include “above” or “over” something without an intermediate feature or layer in between (i.e., directly on) something.

[0025] Light-emitting diodes (LEDs) are commonly used components in various fields. Taking ultraviolet (UV) LEDs as an example, an LED mainly consists of a diode chip, a substrate, optical components, and a driving circuit. The substrate provides mechanical support for the diode chip; the optical components, including lenses and reflectors, are used to control and optimize the direction and distribution of the light emitted by the diode chip; the diode chip mainly includes an epitaxial structure for emitting deep ultraviolet light.

[0026] See Figure 1 , Figure 1 A schematic diagram of an epitaxial structure comprising a diode chip in the related art is shown. The epitaxial structure includes a substrate 11, a base layer 12, a transition layer 13, an n-contact layer 14, an active layer 15, an electron blocking layer (EBL) 16, and a p-contact layer 17 stacked sequentially along the Z direction (hereinafter referred to as the first direction), as well as an n-type contact 18 located above the n-type contact layer and a p-type contact 19 located above the p-type contact layer.

[0027] During the operation of the diode chip, the p-type contact 19 is connected to the positive terminal of the power supply, and the n-type contact 18 is connected to the negative terminal of the power supply. Under the action of the power supply voltage, the n-type carriers (i.e. electrons) in the n-type contact layer 14 enter the active layer 15, and the p-type carriers (i.e. holes) in the p-type contact layer 17 pass through the electron blocking layer 16 and enter the active layer 15. The n-type carriers and p-type carriers recombine and emit light in the active layer 15.

[0028] The closer the number of n-type carriers to the number of p-type carriers in the active layer 15 (i.e., the more symmetrical), the higher the recombination rate between n-type and p-type carriers, and the higher the luminous efficiency of the diode chip. Conversely, the greater the deviation between the number of n-type carriers and p-type carriers in the active layer 15 (i.e., the worse the symmetry), the lower the recombination rate between n-type and p-type carriers, and the lower the luminous efficiency of the diode chip.

[0029] In UV LEDs, the p-type contact layer is typically formed using aluminum gallium nitride (AlGaN). The shorter the wavelength of the deep ultraviolet light emitted by the diode chip, the higher the molar fraction of aluminum (Al) in the p-type contact layer. A higher molar fraction means a higher activation energy required to activate p-type carriers during the formation of the p-type contact layer, making activation more difficult. This may result in a lower number of activated p-type carriers in the p-type contact layer. When the number of activated p-type carriers in the p-type contact layer is low, fewer p-type carriers enter the active layer during the diode chip's light emission process.

[0030] like Figure 1 As shown, the p-type contact layer and electron blocking layer can also be formed using aluminum gallium nitride. The n-type contact layer is located below the active layer, and light emitted from the active layer is emitted through the n-type contact layer. For diode chips with wavelengths below 280 nm, the molar fraction of Al in the n-type contact layer must reach more than 70% to prevent light absorption. When the molar fraction of Al in the n-type contact layer is high (not less than 70%), in order to effectively block n-type charge carriers (i.e., electrons) from entering the p-type contact layer, the molar fraction of Al in the electron blocking layer is also relatively high, typically above 90%. Correspondingly, when the molar fraction of Al in the electron blocking layer is high, the potential barrier for p-type charge carriers to enter the active layer is larger, which reduces the number of p-type charge carriers entering the active layer.

[0031] Due to the aforementioned reasons, during the light emission process of a diode chip, the number of p-type carriers entering the active layer is significantly less than that of n-type carriers, resulting in poor symmetry between p-type and n-type carriers in the active layer. This asymmetry reduces the recombination rate of p-type and n-type carriers in the active layer, thereby reducing the light emission efficiency of the diode chip.

[0032] In related technologies, one approach is to control the molar fraction of Al in the p-type contact layer to be low (e.g., below 30%). This ensures that p-type carriers have a low activation energy during activation, thereby increasing the number of p-type carriers in the p-type contact layer. However, when the molar fraction of Al in the p-type contact layer is low, the difference between the molar fraction of Al in the p-type contact layer and the molar fraction of Al in the electron blocking layer becomes large. This increases the difficulty for p-type carriers to enter the active layer, reducing the number of p-type carriers entering the active layer.

[0033] In related technologies, another approach is to control the molar fraction of Al in the p-type contact layer to be higher (e.g., above 50%), in order to increase the number of p-type charge carriers in the p-type contact layer. However, when the molar fraction of Al in the p-type contact layer is controlled to be high, the activation energy of the p-type charge carriers will rise sharply, leading to a significant decrease in the number of p-type charge carriers in the p-type contact layer, which will reduce the number of p-type charge carriers entering the active layer. Obviously, neither of the above two approaches in related technologies can solve the aforementioned problem.

[0034] To address the aforementioned technical problems, this application provides a diode chip in which a p-type contact layer is disposed on the side of the active layer, directly contacting the active layer. This allows p-type charge carriers to enter the active layer directly without passing through the electron blocking layer, thereby increasing the number of p-type charge carriers entering the active layer. Furthermore, the n-type contact layer in this diode chip is disposed on the side of the electron blocking layer away from the active layer. This blocking layer can prevent some n-type charge carriers from entering the active layer, reducing the number of n-type charge carriers entering the active layer.

[0035] In short, the diode chip provided in this application embodiment can not only increase the number of p-type carriers entering the active layer, but also reduce the number of n-type carriers entering the active layer. This reduces the quantity deviation between p-type and n-type carriers in the active layer, improves the symmetry of p-type and n-type carriers in the active layer, and further improves the recombination efficiency of p-type and n-type carriers in the active layer, thereby improving the luminous efficiency of the diode chip.

[0036] The diode chip provided in this application mainly includes a support layer, an active layer, a p-type contact layer, an electron blocking layer, and an n-type contact layer. The active layer is disposed in a first region on one side of the support layer along a first direction, the p-type contact layer is disposed in a second region on the same side of the support layer along the first direction, the p-type contact layer is in contact with the active layer, the electron blocking layer is disposed on the side of the active layer away from the support layer, and the n-type contact layer is disposed on the side of the electron blocking layer away from the active layer.

[0037] See Figure 2 , Figure 2 The diagram shows an epitaxial structure included in a diode chip according to an embodiment of this application. The diode chip 20 includes a support layer 21, an active layer 22, a p-type contact layer 23, an electron blocking layer 24, and an n-type contact layer 25.

[0038] like Figure 2 As shown, the support layer 21 may include a substrate 211, a base layer 212 and a transition layer 213 stacked sequentially along the Z direction. The base layer 212 is located on one side of the substrate 211 along the Z direction and is in contact with the substrate 211. The transition layer 213 is located on the side of the base layer 212 away from the substrate 211 and is in contact with the base layer 212.

[0039] The substrate 211 provides support for the entire epitaxial structure, while the base layer 212 and transition layer 213 alleviate the lattice mismatch between the active layer 22 (and the p-type contact layer) and the substrate 211, thereby reducing dislocation defects caused by lattice mismatch. The substrate 211 can be formed of sapphire (Al2O3) or aluminum nitride, or other materials that can be used as a substrate; the base layer 212 can be formed of aluminum nitride (AlN), or other materials that can be used as a base layer; the transition layer 213 can be formed of aluminum nitride or aluminum gallium nitride, or other materials that can be used as a base layer.

[0040] The active layer 22, also known as multiple quantum wells (MQWs), comprises alternating quantum well layers and barrier layers arranged along the Z-direction. The quantum well layers are formed of a material with a smaller bandgap, such as indium gallium nitride (InGaN), while the barrier layers are formed of a material with a larger bandgap, such as gallium nitride (GaN). For example, the active layer 22 may include 5 to 10 pairs of quantum well layers and barrier layers, specifically 5, 6, 7, and 10 pairs. When there are 10 pairs, the 10 quantum well layers and 10 barrier layers are arranged alternately along the Z-direction.

[0041] The p-type contact layer 23 can be formed of aluminum gallium nitride or gallium nitride (GaN), or other materials that can form the p-type contact layer 23.

[0042] In this embodiment, the active layer 22 and the p-type contact layer 23 are both located on the side of the transition layer 213 (i.e., the support layer) away from the substrate 211, and are in contact with the transition layer 213 respectively. It can be understood that the active layer 22 and the p-type contact layer 23 are disposed in the same layer of the epitaxial structure, and their shapes match to form one layer of the entire epitaxial structure.

[0043] like Figure 2 As shown, the p-type contact layer 23 includes a first portion 231 and a second portion 232. The first portion 231 and the second portion 232 are respectively disposed on both sides of the active layer 22 along the X direction (i.e., the second direction), and the second direction is perpendicular to the first direction. The first region refers to the region where the active layer 22 is located, and the second region refers to the region where the p-type contact layer 23 is located, including the region where the first portion 231 is located and the region where the second portion 232 is located.

[0044] like Figure 2As shown, the first portion 231 and the second portion 232 can be elongated strips extending along the Y direction (hereinafter referred to as the third direction), and the active layer 22 is a plate extending along the Y direction. The dimensions of the first portion 231, the active layer 22, and the second portion 232 along the Z direction are close to or equal to those of the first portion 231, the active layer 22, and the second portion 232 along the Y direction are close to or equal to those of the transition layer 213 along the Y direction. The sum of the dimensions of the first portion 231, the active layer 22, and the second portion 232 along the X direction is close to or equal to the dimension of the transition layer 213 along the X direction.

[0045] The first part 231, the active layer 22, and the second part 232 are arranged sequentially along the X direction. The active layer 22 is located at the center of the transition layer 213 along the X direction. The first part 231 and the second part 232 are located at both ends of the active layer 22 along the X direction. Along the X direction, the first part 231 is in contact with the active layer 22, and the second part 232 is also in contact with the active layer 222.

[0046] See Figure 3 , Figure 3 It shows Figure 2 This is a magnified schematic diagram showing a portion of the area between the active layer and the p-type contact layer. (See diagram below.) Figure 3 As shown, the active layer 22 includes a barrier layer 221 and a quantum well layer 222 arranged alternately along the Z direction. The side of the active layer 22 along the X direction is in contact with the side of the p-type contact layer 23 along the X direction. In this way, during the operation of the diode chip, p-type carriers can directly enter the active layer 22 from the side.

[0047] like Figure 2 As shown, the electron blocking layer 24 is disposed on the side of the active layer 22 away from the transition layer 213, and the electron blocking layer 24 is in contact with the active layer 22. Both the electron blocking layer 24 and the active layer 22 are rectangular plate-like structures extending along the Y direction. The dimension of the electron blocking layer 24 along the Y direction is close to or equal to the dimension of the active layer 22 along the Y direction, and the dimension of the electron blocking layer 24 along the X direction is smaller than the dimension of the active layer 22 along the X direction. The electron blocking layer 24 is located in the central region of the active layer 22 along the X direction. This allows the first portion 231 and the second portion 232 to be separated from the resistive blocking layer 24 by a certain distance, achieving a non-contact state.

[0048] The n-type contact layer 25 is disposed on the side of the electron blocking layer 24 away from the active layer 22. The n-type contact layer 25 is in contact with the electron blocking layer 24. The size of the n-type contact layer 25 along the X direction is close to or equal to the size of the electron blocking layer 24 along the X direction, or it can be smaller than the size of the electron blocking layer 24 along the X direction. The size of the n-type contact layer 25 along the Y direction is close to or equal to the size of the electron blocking layer 24 along the Y direction.

[0049] The materials used to form the n-type contact layer and the electron blocking layer can be aluminum gallium nitride as exemplified above, or other usable materials. This embodiment does not limit the use of such materials.

[0050] Optionally, a p-type contact layer is disposed around the periphery of the active layer.

[0051] See Figure 4 , Figure 4 This illustration shows a schematic diagram of an epitaxial structure included in another diode chip according to an embodiment of this application. In this epitaxial structure, the active layer 22 is a square plate-like structure, stacked in the central region (i.e., the first region) of the transition layer 213 on the side facing away from the substrate 211. The p-type contact layer 23 is a square ring-like structure, stacked in the peripheral region (i.e., the second region) of the transition layer 213 on the side facing away from the substrate 211, and the p-type contact layer 23 surrounds the periphery of the active layer 22.

[0052] like Figure 4 As shown, the electron blocking layer 24 is also a plate-like structure in the positive direction. The size of the electron blocking layer 24 in the X direction is smaller than that of the active layer 22 in the X direction, and the size of the electron blocking layer 24 in the Y direction is also smaller than that of the active layer 22 in the Y direction. The electron blocking layer 24 is located in the central region of the active layer 22 on the side away from the transition layer 213. This allows the p-type contact layer 23 and the electron blocking layer 24 to be spaced apart, achieving a non-contact state.

[0053] Similarly, the n-type contact layer 25 is also a plate-like structure in the positive direction. The size of the n-type contact layer 25 along the X direction is close to or equal to the size of the electron blocking layer 24 along the X direction, and the size of the n-type contact layer 2 along the Y direction is also close to or equal to the size of the electron blocking layer 24 along the Y direction.

[0054] Combination Figure 3 As shown, the p-type contact layer 23 is in contact with the active layer 22 in both the X and Y directions. In practical applications, when the p-type contact layer 23 surrounds the active layer 22, the contact area between the p-type contact layer 23 and the active layer 22 is larger, which can increase the number of p-type charge carriers flowing into the active layer 22.

[0055] in, Figure 2-4 The diode chip shown may also include n-type contacts and p-type contacts (not shown in the figure). The p-type contact is located on the side of the p-type contact layer away from the transition layer 213, and the n-type contact is located on the side of the n-type contact layer away from the electron blocking layer. Both the n-type and p-type contacts can be ohmic contacts and can be made of conductive metal materials. The n-type contact is used to connect the n-type contact layer to the negative terminal of the power supply, and the p-type contact is used to connect the p-type contact layer to the positive terminal of the power supply.

[0056] like Figure 2-4As shown, during the operation of diode chip 20, p-type contact layer 22 is connected to the positive terminal of the power supply, n-type contact layer 25 is connected to the negative terminal of the power supply, p-type carriers in p-type contact layer 23 enter the active layer 22 from the side of the active layer 22 along the X and / or Y directions, n-type carriers in n-type contact layer 25 enter the active layer 22 after passing through electron blocking layer 24, and n-type carriers and p-type carriers recombine in the active layer 22 to emit light.

[0057] Since the p-type contact layer 23 is disposed on the side of the active layer 22 and is in direct contact with it, p-type carriers do not need to cross the electron blocking layer when entering the active layer 22, thereby increasing the number of p-type carriers entering the active layer 22. Simultaneously, the n-type contact layer 25 is disposed on the side of the electron blocking layer 24 away from the active layer 22. The electron blocking layer 25 can block some n-type carriers from entering the active layer, thus reducing the number of n-type carriers entering the active layer 22. The increase in p-type carriers and the decrease in n-type carriers improve the symmetry between n-type and p-type carriers in the active layer, thereby increasing the recombination efficiency of p-type and n-type carriers in the active layer, and consequently improving the luminous efficiency of the diode chip.

[0058] like Figure 1 As shown, in related technologies, an n-type contact layer is disposed below the active layer. In order to reduce the lateral transmission resistance of the n-type contact layer, the size of the n-type contact layer along the first direction is generally large, which will generate large penetrating dislocations. The penetrating dislocations will extend into the active layer, resulting in an increase in non-radiative recombination in the active layer, thereby reducing the recombination efficiency of p-type carriers and n-type carriers in the active layer.

[0059] like Figure 2-4 As shown, in the diode chip provided in this application, the n-type contact layer is disposed on the side of the electron blocking layer away from the active layer. The through-hole dislocations generated by the n-type contact layer will not extend to the active layer, which can solve the problem of reduced recombination rate caused by through-hole dislocations generated by the n-type contact layer.

[0060] Furthermore, in the diode chip provided in this application, the n-type contact layer is disposed on the side of the electron blocking layer away from the active layer. Light emitted from the active layer can bypass the n-type contact layer, eliminating the need to prevent light absorption by the n-type contact layer. Therefore, the mole fraction of Al in the n-type contact layer can be controlled to be low, thereby reducing the number of n-type charge carriers in the n-type contact layer and consequently reducing the number of n-type charge carriers entering the active layer. Simultaneously, the mole fraction of Al in the electron blocking layer can be controlled to be high, creating a larger difference between the mole fraction of Al in the electron blocking layer and the mole fraction of Al in the n-type contact layer. This enhances the blocking effect of the electron blocking layer on n-type charge carriers, further reducing the number of n-type charge carriers entering the active layer.

[0061] It should be noted that, Figure 2-4 For illustrative purposes only, the specific shapes of the active layer and the p-type contact layer include, but are not limited to, those shown below. Figure 2-4 As shown.

[0062] Alternatively, the p-type contact layer can be formed using gallium nitride.

[0063] Compared to aluminum gallium nitride (AlGaN), gallium nitride (GaN) has a lower activation energy for p-type carriers. When GaN is used to form the p-type contact layer, under the same conditions, more p-type carriers are activated in the p-type contact layer during diode chip manufacturing. This increases the number of p-type carriers entering the active layer during diode chip operation, thereby improving the symmetry between n-type and p-type carriers in the active layer. This, in turn, increases the recombination efficiency of p-type and n-type carriers in the active layer, ultimately improving the luminous efficiency of the diode chip.

[0064] Optionally, the forming material of the n-type contact layer includes aluminum gallium nitride, wherein the molar fraction of aluminum in the n-type contact layer is less than or equal to 50%.

[0065] In one embodiment, the material forming the n-type contact layer can be aluminum gallium nitride. During the formation of the n-type contact layer, the molar fraction of Al in the n-type contact layer can be controlled to be less than or equal to 50%. For example, the molar fraction of Al in the n-type contact layer can be 50%, 48%, 42%, 44%, 39%, 30%, etc., but is not limited thereto.

[0066] The size of the n-type contact layer along the first direction can be greater than or equal to 1000 nanometers and less than or equal to 2000 nanometers, for example, it can be 1000 nanometers, 1200 nanometers, 1400 nanometers, 1500 nanometers, 1800 nanometers, 1900 nanometers and 2000 nanometers.

[0067] When the molar fraction of Al in the n-type contact layer is less than or equal to 50%, the number of n-type charge carriers in the n-type contact layer is relatively small. Consequently, during the operation of the diode chip, the number of n-type charge carriers entering the active layer can be reduced, thereby improving the recombination efficiency of p-type and n-type charge carriers in the active layer and thus improving the luminous efficiency of the diode chip.

[0068] In practical applications, when the forming material of the n-type contact layer is aluminum gallium nitride, the molar fraction of Al in the n-type contact layer can be controlled to be greater than or equal to 30% during the formation of the n-type contact layer to prevent the problem of low n-type charge carrier quantity.

[0069] Optionally, the electron blocking layer is formed of aluminum gallium nitride, wherein the molar fraction of aluminum in the electron blocking layer is greater than or equal to 70%.

[0070] In one embodiment, the electron blocking layer can be formed using aluminum gallium nitride. During the formation of the electron blocking layer, the molar fraction of Al in the electron blocking layer can be controlled to be greater than or equal to 70%. For example, the molar fraction of Al in the electron blocking layer can be 70%, 77%, 80%, 86%, 96%, 100%, etc., but is not limited thereto.

[0071] When the molar fraction of Al in the electron blocking layer is greater than or equal to 70%, the electron blocking layer has a high potential barrier, which can reduce the number of n-type charge carriers entering the active layer. Furthermore, when the molar fraction of Al in the electron blocking layer is greater than or equal to 70%, and the molar fraction of Al in the n-type contact layer is less than or equal to 50%, the significant difference in the molar fractions of Al between the electron blocking layer and the n-type contact layer can effectively reduce the number of n-type charge carriers entering the active layer, thereby improving the symmetry between n-type and p-type charge carriers in the active layer.

[0072] Optionally, the support layer includes a base layer and a transition layer sequentially disposed along a first direction; an active layer and a p-type contact layer are disposed on the side of the transition layer away from the base layer. The transition layer is formed of undoped aluminum gallium nitride (i-AlGaN), and the size of the transition layer along the first direction is less than or equal to 200 nanometers.

[0073] like Figure 2-4 As shown, the support layer 21 includes a substrate 211, a base layer 212, and a transition layer 213 sequentially disposed along a first direction. The base layer 212 can be formed of aluminum nitride (AlN), and the transition layer 213 can be formed of undoped aluminum gallium nitride. Undoped aluminum gallium nitride refers to aluminum gallium nitride without the addition of p-type and n-type dopants.

[0074] For example, the size of the substrate layer 212 along the first direction can be controlled to be between 0.5 micrometers and 3 micrometers, such as 3 micrometers, 2.7 micrometers, 2 micrometers, 1 micrometer, 0.9 micrometers, 0.8 micrometers, 0.6 micrometers, and 0.5 micrometers. Furthermore, the size of the transition layer 213 along the first direction can be greater than or equal to 100 nanometers and less than or equal to 200 nanometers. For example, the size of the transition layer along the Z direction can be 100 nanometers, 112 nanometers, 134 nanometers, 156 nanometers, 145 nanometers, 165 nanometers, 199 nanometers, and 200 nanometers.

[0075] In this embodiment, the transition layer is made of undoped aluminum gallium nitride, which can control the size of the transition layer along the first direction to be less than 200 nanometers. This allows the transition layer to have a smaller size along the first direction, thereby preventing through dislocations from appearing in the transition layer due to increased thickness. This, in turn, prevents through dislocations from entering the active layer and affecting the recombination rate of the active layer.

[0076] In practical applications, when the substrate layer 212 can solve the lattice mismatch problem between the active layer 22 and the substrate 211, the transition layer 213 may not be provided in the support layer 21. When the transition layer 213 is not provided in the support layer 21, the active layer 22 and the p-type contact layer 23 can be directly provided on the side of the substrate layer 212 away from the substrate 211.

[0077] It should be understood that Figure 2-4 Only a portion of the components of the diode chip is shown. The diode chip also includes other components, which will not be described in detail in this embodiment.

[0078] This application also includes a light-emitting diode, also known as an LED chip, which includes the diode chip in the example above, as well as other components.

[0079] This application also includes a device, such as a DUV light source, a solar blind detector, and a high-voltage power supply, including but not limited to these. The device includes the light-emitting diodes mentioned in the above examples, as well as other components.

[0080] This application also provides a method for manufacturing a diode chip, which is used to manufacture the diode chip in the example above.

[0081] See Figure 5 , Figure 5 This is a schematic diagram of a method for manufacturing a diode chip according to an embodiment of this application. The method includes the following steps: Step 501: Form a support layer.

[0082] Step 502: An active layer is formed in the first region on one side of the support layer along the first direction.

[0083] Step 503: A p-type contact layer is formed in the second region on one side of the support layer along the first direction, and the p-type contact layer is in contact with the active layer.

[0084] Step 504: Form an electron blocking layer on the side of the active layer away from the support layer.

[0085] Step 505: Form an n-type contact layer on the side of the electron blocking layer away from the active layer.

[0086] The execution order of each step in steps 501-505 can be set according to specific requirements, and this embodiment does not impose any restrictions on this.

[0087] Optionally, step 503 may include: The pre-formed n-type contact layer and electron blocking layer are etched to expose the first and second ends of the active layer that are disposed opposite to each other along the second direction. The first end facing away from the second end is etched, and the second end facing away from the first end is etched to expose the second region; A p-type contact layer is formed in the exposed second region.

[0088] In one embodiment, a support layer, an active layer, an electron blocking layer, and an n-type contact layer can be formed sequentially along a first direction. Then, the active layer, the electron blocking layer, and the n-type contact layer are etched to expose a second region on the support layer where the p-type contact layer is located. The p-type contact layer is then formed in the second region.

[0089] See Figure 6-11 , Figure 6-11 for Figure 2 The diagram shows the manufacturing process of a diode chip.

[0090] like Figure 6 As shown, in the manufacturing process of a diode chip, a substrate 211 is first manufactured, and then an epitaxial growth process is used to sequentially form a base layer 212, a transition layer 213, an active layer 22, an electron blocking layer 24, and an n-type contact layer 25 on one side of the substrate 211 along the Z direction.

[0091] like Figure 7 As shown, after forming the electron blocking layer 24 and the n-type contact layer 25, the electron blocking layer 24 and the n-type contact layer 25 can be etched to expose the first end 221 and the second end 222 of the active layer 22 which are disposed opposite to each other in the X direction.

[0092] like Figure 8-9 As shown, after exposing the first end 221 and the second end 222 of the active layer 22, a mask 26 (which can be a silicon dioxide mask) can first be deposited on the side of the n-type contact layer 25 away from the electron blocking layer 24. Then, the end of the first end 221 away from the second end 222 and the end of the second end 222 away from the first end 221 are etched to expose both ends of the transition layer 213 along the first direction. The two ends of the transition layer 213 along the second direction away from the base layer 212 are the second region where the p-type contact layer is located.

[0093] like Figure 10-11 As shown, after the two ends of the transition layer 213 are exposed along the second direction, an epitaxial growth process can be used to form a first portion 231 and a second portion 232 at the two ends of the transition layer 213, respectively, to obtain a p-type contact layer composed of the first portion 231 and the second portion 232.

[0094] Subsequently, the mask 26 can be removed to form p-type contacts on the p-type contact layer, n-type contacts on the n-type contacts, and other components of the diode chip 20 on the epitaxial structure.

[0095] Optionally, step 503 may include: The edges of the pre-formed n-type contact layer and the electron blocking layer are etched to expose the edges of the active layer. The edges of the active layer are etched to expose the second region; The p-type contact layer is formed in the exposed second region.

[0096] like Figure 4 As shown, in the formation Figure 4 During the process of manufacturing the diode chip shown, the following methods can be used: Figure 6-11 Similarly, during the etching of the n-type contact layer and the electron blocking layer, etching is performed at both ends of the n-type contact layer and the electron blocking layer along the X direction, and at both ends of the n-type contact layer and the electron blocking layer along the Y direction, to remove the outer portions of the n-type contact layer and the electron blocking layer, exposing the edge of the active layer 22. Then, the edge of the active layer can be etched to expose the edge of the transition layer, with the exposed edge of the transition layer facing away from the substrate layer, i.e., the second region. Subsequently, a ring-shaped p-type contact layer can be formed at the edge of the transition layer.

[0097] In this embodiment, a support layer, an active layer, an electron blocking layer, and an n-type contact layer are first formed in sequence. Then, a first etching step is performed to etch the electron blocking layer and the n-type contact layer, exposing the active layer. A second etching step is then performed to etch the active layer, exposing the support layer and revealing a second region on the support layer containing the p-type contact layer. Finally, the p-type contact layer is formed in the exposed second region. Through these two etching steps, the dimensions of the electron blocking layer, the n-type contact layer, and the active layer along the X-direction can be controlled, as can the dimensions of the final p-type contact layer along the X-direction. This prevents the final p-type contact layer from contacting the etch blocking layer and the n-type contact layer, while ensuring effective contact between the p-type contact layer and the active layer. Simultaneously, the etching depth in the Z-direction can be accurately controlled to expose the support layer (i.e., the transition layer), allowing the final p-type contact layer to effectively contact the support layer (i.e., the transition layer).

[0098] It should be understood that the above are merely illustrative examples, and the specific manufacturing methods of the diode chips described above may include, but are not limited to, the examples above.

[0099] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A diode chip, characterized in that, include: Support layer; An active layer is disposed in a first region on one side of the support layer along a first direction; A p-type contact layer is disposed in a second region on one side of the support layer along the first direction, and the p-type contact layer is in contact with the active layer; An electron blocking layer is disposed on the side of the active layer away from the support layer, and the electron blocking layer is not in contact with the p-type contact layer. An n-type contact layer is disposed on the side of the electron blocking layer opposite to the active layer.

2. The diode chip as described in claim 1, characterized in that, The p-type contact layer includes a first portion and a second portion, which are respectively disposed on both sides of the active layer along a second direction, the second direction being perpendicular to the first direction.

3. The diode chip as described in claim 1, characterized in that, The p-type contact layer is disposed around the periphery of the active layer.

4. The diode chip as described in claim 1, characterized in that, The p-type contact layer is formed of gallium nitride.

5. The diode chip as described in claim 1, characterized in that, The forming material of the n-type contact layer includes aluminum gallium nitride, and the molar fraction of aluminum in the n-type contact layer is less than or equal to 50%.

6. The diode chip as described in claim 5, characterized in that, The electron blocking layer is formed of aluminum gallium nitride, and the molar fraction of aluminum in the electron blocking layer is greater than or equal to 70%.

7. The diode chip as described in any one of claims 1-6, characterized in that, The support layer includes a base layer and a transition layer arranged sequentially along the first direction, and the active layer and the p-type contact layer are disposed on the side of the transition layer away from the base layer. The transition layer is formed of undoped aluminum gallium nitride, and the size of the transition layer along the first direction is less than or equal to 200 nanometers.

8. A light-emitting diode, characterized in that, include: The diode chip as described in any one of claims 1 to 7.

9. A device, characterized in that, include: The light-emitting diode as described in claim 8.

10. A method for manufacturing a diode chip, characterized in that, The method includes: Form a support layer; An active layer is formed in a first region on one side of the support layer along the first direction; A p-type contact layer is formed in a second region on one side of the support layer along the first direction, and the p-type contact layer is in contact with the active layer; An electron blocking layer is formed on the side of the active layer away from the support layer, and the electron blocking layer is not in contact with the p-type contact layer. An n-type contact layer is formed on the side of the electron blocking layer opposite to the active layer.

11. The manufacturing method of claim 10, wherein forming a p-type contact layer in the second region on one side of the support layer along the first direction comprises: The pre-formed n-type contact layer and the electron blocking layer are etched to expose the first end and the second end of the active layer that are disposed opposite to each other along the second direction. The first end facing away from the second end is etched, and the second end facing away from the first end is etched to expose the second region; The p-type contact layer is formed in the exposed second region.

12. The manufacturing method as described in claim 10, characterized in that, The formation of a p-type contact layer in the second region on one side of the support layer along the first direction includes: The edges of the pre-formed n-type contact layer and the electron blocking layer are etched to expose the edges of the active layer. The edges of the active layer are etched to expose the second region; The p-type contact layer is formed in the exposed second region.

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