An optical lattice clock enhancement cavity automatic locking device and method

Abstract

The application discloses an automatic locking device for an optical lattice clock enhancement cavity, comprising a power supply unit, an input voltage setting unit, a state detection unit, a logic control unit and an automatic locking unit, wherein the state detection unit comprises an overrun detection circuit and a lock loss detection circuit, the logic control unit comprises a first OR gate circuit, a second OR gate circuit, a third OR gate circuit, an enabling switch, an AND gate circuit, a second NAND gate circuit and a monostable pulse generator, and the automatic locking unit comprises a sample-and-hold circuit, an adding circuit and an output voltage limiting circuit. The application further discloses an automatic locking method for the optical lattice clock enhancement cavity. The application can quickly establish initial locking for the enhancement cavity in an experiment, can monitor the locking state of the enhancement cavity in real time, can realize automatic relocking after the enhancement cavity loses locking, and effectively reduces manual intervention.

Description

Technical Field

[0001] This invention belongs to the field of time and frequency metering circuit technology, specifically relating to an automatic locking device for an optical lattice clock enhancement cavity, and also to an automatic locking method for an optical lattice clock enhancement cavity, which is suitable for automatically locking an optical lattice clock enhancement cavity. Background Technology

[0002] An enhancement cavity is an optical cavity based on the principle of optical resonance, primarily used to enhance the power or intensity of lattice light in an optical lattice clock. Its working principle utilizes the resonance enhancement effect; when the incident light matches the cavity's resonance mode, the optical power within the cavity will be much greater than the incident light power, thereby enhancing the interaction strength with atoms.

[0003] In atomic optical frequency standards, cavity-enhanced optical lattices, achieved using enhanced cavities, can amplify lattice optical power and increase potential well depth. Cavity-enhanced optical lattice technology can significantly reduce the required laser power, providing technical support for realizing optical lattices using small, low-power lasers, and is of great significance for advancing the miniaturization and low-power consumption of optical clocks.

[0004] Locking the enhancement cavity of an optical lattice clock is a key technology for ensuring its stable operation and achieving high-precision frequency control. The core of enhancement cavity locking is to precisely stabilize the cavity's resonant frequency at the target optical frequency, ensuring that the cavity resonant frequency is strictly consistent with the incident light (i.e., lattice light) frequency. In experiments, the Pound-Drever-Hall (PDH) frequency stabilization technique is typically used to lock the enhancement cavity. When initial locking of the cavity is required or if the cavity loses lock during operation, manual scanning is needed to locate the cavity transmission peak position. Activating the locking device near the transmission peak is necessary to correctly complete the locking. This locking method is highly dependent on manual intervention. On the one hand, the initial locking and relocking process after loss of lock is cumbersome; on the other hand, manual operation makes it difficult to detect the locking status of the enhancement cavity in a timely manner, which is detrimental to the long-term stable operation of the optical clock. Therefore, finding a device that can monitor the locking status of the enhancement cavity in real time and quickly and automatically lock it after loss of lock is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an automatic locking device for an optical lattice clock enhancement cavity, as well as an automatic locking method for an optical lattice clock enhancement cavity.

[0006] The above-mentioned objectives of the present invention are achieved by the following technical means:

[0007] An automatic locking device for an optical lattice clock enhancement cavity includes a logic control unit. The logic control unit includes a first OR gate circuit. A lockout signal and an over-limit signal are connected to input terminals A and B of the first OR gate circuit, respectively. The output terminal of the first OR gate circuit outputs an error signal. A programmable enable locking operation signal is connected to input terminals A of a second OR gate circuit and a third OR gate circuit, respectively. The error signal is connected to input terminals B of the second OR gate circuit and a second NAND gate circuit, respectively. The error signal is connected to electrical ground through an enable switch. The output terminal of the second OR gate circuit outputs a scan execution signal, which is connected to input terminal A of an AND gate circuit and a trigger signal input terminal of a monostable pulse generator, respectively. The output terminal of the monostable pulse generator outputs a hold signal, which is connected to input terminals B of the AND gate circuit and A of the second NAND gate circuit, respectively. The output terminal of the AND gate circuit outputs a sampling mode signal. The output terminal of the second NAND gate circuit is connected to input terminal B of the third OR gate circuit. The output terminal of the third OR gate circuit outputs a locking signal as a controller locking operation signal for a PID servo controller.

[0008] As described above, the input terminal A of the second OR gate is connected to electrical ground through a resistor, and the input terminal B of the AND gate is connected to a +5V power supply through a resistor.

[0009] An automatic locking device for an optical lattice clock enhancement cavity further includes an automatic locking unit. The automatic locking unit includes a first analog switch circuit. The input channels SA and SB of the first analog switch circuit are respectively connected to an external scanning signal and electrical ground. An error signal is input to the channel selection control terminal of the first analog switch circuit. The output terminal of the first analog switch circuit is connected to the analog signal input terminal of a monolithic sample-and-hold circuit. The logic signal input terminal of the monolithic sample-and-hold circuit is connected to a sampling mode signal. The output terminal of the monolithic sample-and-hold circuit is connected to the input terminal of a first follower circuit. The output terminal of the first follower circuit is input to the input channel SB of a second analog switch circuit. The input channel SA of the second analog switch circuit is connected to electrical ground through a resistor. A locking signal is input to the channel selection control terminal of the second analog switch circuit. The output terminal of the second analog switch circuit is connected to the input terminal of the second follower circuit. A PID servo controller feedback signal is input to the input terminal of a third follower circuit. The output terminals of the second and third follower circuits are respectively connected to the two input terminals of a non-inverting adder circuit.

[0010] As described above, the error signal is input to the channel selection control terminal of the first analog switch circuit through the first RC delay circuit, and the lock signal is input to the channel selection control terminal of the second analog switch circuit through the second RC delay circuit. A Schottky diode is connected in parallel across the resistor of the second delay circuit, and the cathode and anode of the Schottky diode are electrically connected to the lock signal and the channel selection control terminal of the second analog switch circuit, respectively.

[0011] An automatic locking device for an optical lattice clock enhancement cavity further includes an upper limit adjustment circuit for output voltage, a lower limit adjustment circuit for output voltage, and a fourth follower circuit. The upper limit adjustment circuit for output voltage includes a fourth potentiometer, a fifth follower circuit, and a first diode. The lower limit adjustment circuit for output voltage includes a fifth potentiometer, a sixth follower circuit, and a second diode.

[0012] The adjustable terminal of the fourth potentiometer is connected to the non-inverting input terminal of the fifth follower circuit. The output terminal of the fifth follower circuit is connected to the cathode of the first diode. The anode of the first diode is connected to the output terminal of the non-inverting adder circuit. The non-inverting input terminal of the fourth follower circuit is connected to the output terminal of the non-inverting adder circuit. The output terminal of the fourth follower circuit outputs the signal. The adjustable terminal of the fifth potentiometer is connected to the non-inverting input terminal of the sixth follower circuit. The output terminal of the sixth follower circuit is connected to the anode of the second diode. The cathode of the second diode is connected to the output terminal of the non-inverting adder circuit.

[0013] An automatic locking device for the enhancement cavity of an optical lattice clock further includes an over-limit detection circuit. The over-limit detection circuit includes a first comparator circuit, a second comparator circuit, a first NAND gate circuit, and a voltage over-limit status indicator. The inverting input terminal of the first comparator circuit is connected to the adjustable terminal of a second potentiometer. The non-inverting input terminal of the first comparator circuit is connected to the output signal. The output terminal of the first comparator circuit is connected to the input terminal A of the first NAND gate circuit. The inverting input terminal of the second comparator circuit is connected to the output signal. The non-inverting input terminal of the second comparator circuit is connected to the adjustable terminal of the first potentiometer. The output terminal of the second comparator circuit is connected to the input terminal B of the first NAND gate circuit. The output terminal of the first NAND gate circuit outputs an over-limit signal. The output terminal of the first NAND gate circuit is connected to the voltage over-limit status indicator.

[0014] An automatic locking device for an optical lattice clock enhancement cavity further includes a lock-out detection circuit. The lock-out detection circuit includes a third comparator circuit, a NOT gate circuit, and a lock-out status indicator. The inverting input of the third comparator circuit is connected to the adjustable input of a third potentiometer. The lock-out status identification signal is connected to the non-inverting input of the third comparator circuit through a third RC delay circuit. The output of the third comparator circuit is connected to the input of the NOT gate circuit. The output of the NOT gate circuit outputs a lock-out signal. The output of the NOT gate circuit is connected to the lock-out status indicator.

[0015] An automatic locking method for an optical lattice clock enhancement cavity includes the following steps:

[0016] State detection steps:

[0017] If the output signal is less than the upper limit of the input voltage but greater than the lower limit of the input voltage, the over-limit signal is low; if the output signal is greater than the upper limit of the input voltage or less than the lower limit of the input voltage, the over-limit signal is high.

[0018] If the lock status identification signal is greater than the comparison threshold, the unlock signal is low; if the lock status identification signal is less than the comparison threshold, the unlock signal is high.

[0019] Logic control steps:

[0020] An error signal is generated by performing an OR operation on the over-limit signal and the unlock signal. When the over-limit signal or the unlock signal is high, the error signal is high; when both the over-limit signal and the unlock signal are low, the error signal is low.

[0021] If the enable switch is closed, the scan execution signal is the same as the programmable enable lock operation signal;

[0022] If the enable switch is in the off state, the error signal and the programmable enable lock operation signal are ORed to generate the scan execution signal;

[0023] When the scan execution signal is high, the scan signal generator is controlled to perform scanning, the monostable pulse generator continuously outputs a high-level hold signal, and the sampling mode signal is high.

[0024] When the scan execution signal changes from high to low, the monostable pulse generator, triggered by the falling edge, holds the signal for a duration of T. set After the negative pulse, the signal returns to a high level, and during the duration of the negative pulse, the sampling mode signal is at a low level.

[0025] When the scan execution signal is low, the monostable pulse generator continuously outputs a high-level hold signal, and the sampling mode signal is low.

[0026] The hold signal and error signal are ANDed and NOTed, and the resulting signal is then ORed with the programmable enable lock operation signal to obtain the lock signal as the controller lock operation signal.

[0027] Automatic locking steps:

[0028] If the error signal is high, the sampling mode signal is high, and the lock signal is low, then the PID servo controller feedback signal and the scan signal are added together and limited to obtain the output signal.

[0029] If the error signal changes from high level to low level, the sampling mode signal switches from high level to negative pulse, and the lock signal switches from low level to high level, then the scan signal when the sampling mode signal switches from high level to negative pulse and the PID servo controller feedback signal are added together and limited, and then used as the output signal and the lock is executed. After the lock lasts for a set time, the PID servo controller feedback signal is directly limited and used as the output signal.

[0030] The output signal is input to the PZT controller.

[0031] When applied to existing PDH lock cavity technology, this invention has the following beneficial effects:

[0032] (1) As a supplement to the existing PDH cavity locking technology, this invention can quickly establish the initial locking of the reinforcing cavity in the experiment and monitor the locking status of the reinforcing cavity in real time. It can automatically relock after the reinforcing cavity is unlocked, effectively reducing manual intervention. (2) The reinforcing cavity locked by this invention has good robustness and strong anti-interference ability. It can not only quickly recover from the unlocking caused by random interference, but also relock after the voltage exceeds the set range, keeping the output voltage of the PZT controller within its pull range, thus ensuring the long-term stable and reliable operation of the optical clock. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the external structure of the automatic locking device for the optical lattice clock enhancement cavity of the present invention;

[0034] Figure 2 This is a schematic diagram of the front panel of the automatic locking device for the optical lattice clock enhancement cavity of the present invention;

[0035] Figure 3 This is a schematic diagram of the circuit structure of the automatic locking device for the optical lattice clock enhancement cavity of the present invention;

[0036] Figure 4 This is a schematic diagram of the connection of the locking cavity assembly of the present invention;

[0037] Figure 5 This is a schematic diagram of the locking steps of the present invention;

[0038] Figure 6 The diagram below is a control logic diagram of the present invention, wherein (a) is a control logic diagram of the state detection unit; (b) is a control logic diagram of the logic control unit; and (c) is a control logic diagram of the automatic locking unit.

[0039] A1 - pin; A3 - pin; A9 - pin; A11 - pin; C1 - pin; C3 - pin; C9 - pin; C11 - pin;

[0040] Laser; OI; EOM; BS; PD2; CM1; Cavity; CM2; PD1;

[0041] 1-Power supply unit; 2-Input voltage setting unit; 3-Status detection unit; 4-Logic control unit; 5-Automatic locking unit;

[0042] TTL In - Programmable controller enable lock operation signal; TTL Out - Controller lock operation signal; Signal - Lock status identification signal (cavity transmission signal in this invention example); Input - PID servo controller feedback signal; Output - Output signal, used to drive the external PZT controller; Loss of Lock - Unlock signal; Out of Range - Over-limit signal; Disable Relocking - Lock operation access signal; Error - Error signal; Enable - Enable switch; DoScanning - Scan execution signal; KeeppHolding - Hold signal; Scan SH - Sampling mode signal; Lock SH - Lock signal; Scan In - Scan signal;

[0043] U31 - First comparator circuit; U32 - Second comparator circuit; U33 - Third comparator circuit; U34 - First NAND gate circuit; U35 - NOT gate circuit;

[0044] U41 - First OR gate; U42 - Second OR gate; U43 - AND gate; U44 - Second NAND gate; U45 - Third OR gate; U46 - Monostable pulse generator;

[0045] U51 - First analog switch circuit; U52 - Second analog switch circuit; U53 - Monolithic sample-and-hold circuit; U54 - First follower circuit; U55 - Second follower circuit; U56 - Third follower circuit; U57 - Fourth follower circuit; U58 - Fifth follower circuit; U59 - Sixth follower circuit. Detailed Implementation

[0046] To facilitate understanding and implementation of the present invention by those skilled in the art, the present invention will be further described in detail below with reference to embodiments. The embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0047] Example 1:

[0048] An automatic locking device for an optical lattice clock enhancement cavity, the appearance and structure of which are as follows: Figure 1As shown. Includes internal circuit board, tail connector, and front panel.

[0049] An automatic locking device for an optical lattice clock enhancement cavity, the front panel of which is as follows: Figure 2 As shown. Power is the power switch, with two positions: On and Off. Enable is the enable switch, with two positions: On and Off. Vimax and Vimin are potentiometer knobs used to set the maximum and minimum input voltage values, i.e., setting the safe input voltage range. Signal threshold is a potentiometer knob used to set the comparison threshold voltage for the lockout state identification signal. Vomax and Vomin are potentiometer knobs used to set the maximum and minimum output voltage values, limiting the drive voltage range output to the PZT controller.

[0050] An automatic locking device for an optical lattice clock enhancement cavity, the circuitry of its internal circuit board is as follows: Figure 4 As shown, it includes a power supply unit 1, an input voltage setting unit 2, a status detection unit 3, a logic control unit 4, and an automatic locking unit 5. The input terminal of the power supply unit 1 is connected to an external power supply, and its output terminal is connected to the power supply terminals of other circuits. The input terminal of the input voltage setting unit 2 is connected to the power supply terminal, and its output terminal is connected to the status detection unit 3. The input terminal of the status detection unit 3 is connected to the input port (cavity transmission signal) of the input voltage setting unit 2, the automatic locking unit 5, and the lock status identification signal Signal, and its output terminal is connected to the logic control unit 4. The input terminal of the logic control unit 4 is connected to the input port of the status detection unit 3 and the programmable enable lock operation signal TTL In, and its output terminal is connected to the output port of the automatic locking unit 5 and the controller lock operation signal TTL Out. The input terminal of the automatic locking unit 5 is connected to the input port of the PID servo controller feedback signal Input output by the logic control unit 4 and the scan signal Scan In output by the external scan signal generator, and its output terminal is connected to the status detection unit 3 and the control signal output port.

[0051] As one possible implementation, the power supply unit 1 includes a power switch, a +12V power supply circuit, a -12V power supply circuit, a +5V power supply circuit, and a power indicator light.

[0052] One side of the power switch is connected to an external +15V power supply via pins A3 and C3 in the connector at the rear of the device, and to an external -15V power supply via pins A9 and C9. It is also connected to the 0-potential reference point (GND) of the external power supply via pins A1 and C1. The other side is connected to the voltage input terminals of the +12V and -12V power supply circuits, as well as the GND of other circuits. The power switch is used to control the external +15V and -15V voltage input circuitry.

[0053] The +12V power supply circuit uses a TPS7A4701 LDO voltage regulator chip. Its voltage input terminal is connected to the power switch side, and its voltage output terminal is connected to the voltage input terminal of the +5V power supply circuit and the +12V power supply terminal of other circuits.

[0054] The -12V power supply circuit uses a TPS7A3301 LDO voltage regulator chip. Its voltage input terminal is connected to the power switch side, and its voltage output terminal is connected to the -12V power supply terminal of other circuits.

[0055] The +5V power supply circuit uses an LM78L05 voltage regulator chip, whose voltage input terminal is connected to the voltage output terminal of the +12V power supply circuit, and whose voltage output terminal is connected to the +5V power supply terminal of other circuits.

[0056] One end of the power indicator light is connected to the voltage output terminal of the +12V power supply circuit through a current-limiting resistor, and the other end is grounded, used to indicate the power supply status of the device. The +12V power supply circuit, -12V power supply circuit, and +5V power supply circuit output stepped-down +12V, -12V, and +5V voltages respectively, used to provide clean and stable operating voltages for other circuits.

[0057] As one possible implementation, the input voltage setting unit 2 includes a voltage reference circuit and an input voltage range and threshold adjustment circuit.

[0058] The voltage reference circuit includes a reference voltage chip circuit, a non-inverting voltage amplifier circuit, and a non-inverting voltage amplifier circuit. The reference voltage chip circuit uses a REF01 chip, which can output a stable +10V reference voltage. Its power supply terminal is connected to the +12V voltage output by power supply unit 1, and its output terminal is connected to the input terminal of the non-inverting voltage amplifier circuit. Both the non-inverting and non-inverting voltage amplifier circuits use OPA2210 operational amplifier chips, and their power supply terminals are connected to the +12V and -12V voltages output by power supply unit 1, respectively. The input terminal of the non-inverting voltage amplifier circuit is connected to the output terminal of the reference voltage chip circuit, and its output terminal is connected to the input terminal of the non-inverting voltage amplifier circuit and the input voltage range and threshold adjustment circuit. The input terminal of the non-inverting voltage amplifier circuit is connected to the output terminal of the non-inverting voltage amplifier circuit, and its output terminal is connected to the input voltage range and threshold adjustment circuit. The non-inverting voltage amplifier circuit is configured to operate in a 1x non-inverting amplification mode via a resistor network. The feedback resistor network in the voltage inverting amplifier circuit uses a low-temperature drift resistor with a temperature coefficient of 10ppm / K, and is configured to operate in an inverting amplification mode of 1x. The output voltage of the voltage inverting amplifier circuit is -10V.

[0059] The input voltage range and threshold adjustment circuit includes a first potentiometer, a second potentiometer, and a third potentiometer. The first fixed terminals of the first, second, and third potentiometers are all connected to the +10V voltage output from the in-phase voltage amplifier circuit, and the second fixed terminals of the first, second, and third potentiometers are all connected to the -10V voltage output from the inverting voltage amplifier circuit. The adjustable terminals are all connected to the state detection unit 3, and the voltage adjustment range is -10V to +10V. The first and second potentiometers are used to set the upper and lower limits of the input voltage, respectively. The first and second potentiometers provide the upper input voltage limit Vimax and the lower input voltage limit Vimin, and the third potentiometer provides the comparison threshold voltage Vth for the lockout state identification signal.

[0060] Status detection unit 3 is used to execute the following logic:

[0061] If the output signal Output (input to the PZT controller) of the automatic locking unit 5 is less than the upper limit of the input voltage and greater than the lower limit of the input voltage, the out of range signal is low (indicating that no out of range has occurred); if the output signal Output is greater than the upper limit of the input voltage or less than the lower limit of the input voltage, the out of range signal is high (indicating that an out of range has occurred).

[0062] If the lock status identification signal Signal is greater than the comparison threshold, the Loss of Lock signal is low (indicating no lock loss); if the lock status identification signal Signal is less than the comparison threshold, the Loss of Lock signal is high (indicating a lock loss).

[0063] As one possible implementation, the state detection unit 3 includes an over-limit detection circuit and a lock-out detection circuit.

[0064] In one possible implementation, the over-limit detection circuit includes a first comparator circuit U31, a second comparator circuit U32, a first NAND gate circuit U34, and a voltage over-limit status indicator. Both the first comparator circuit U31 and the second comparator circuit U32 use LM2901 comparator chips, and their power supply terminals are connected to the +12V and -12V voltages output from power supply unit 1, respectively. The inverting input terminal of the first comparator circuit U31 is connected to the adjustable terminal of the second potentiometer (providing the lower limit of the input voltage), the non-inverting input terminal of the first comparator circuit U31 is connected to the output terminal (marked as Output signal) of the automatic locking unit 5, and the output terminal of the first comparator circuit U31 is connected to input terminal A of the first NAND gate circuit U34. The inverting input terminal of the second comparator circuit U32 is connected to the output terminal (Output signal) of the automatic locking unit 5, the non-inverting input terminal is connected to the adjustable terminal of the first potentiometer (providing the upper limit of the input voltage), and the output terminal is connected to input terminal B of the first NAND gate circuit U34. The first NAND gate circuit U34 uses the SN74LVC1G132 chip. Its power supply terminal is connected to the +5V voltage output from power supply unit 1. Its input terminal A is connected to the output terminal of the first comparator circuit U31, its input terminal B is connected to the output of the second comparator circuit U32, and its output terminal (the output signal is the out of range signal) is connected to the voltage out of range indicator light. The output voltage is 0V or +5V.

[0065] The effectiveness of the over-range detection circuit is explained here. Since the PZT controller can only withstand a certain range of input voltage (typically 0~10V), cavity drift is unavoidable during experiments. When the cavity drifts in one direction, causing the required control voltage to exceed the PZT controller's voltage range, it will lose lock. This loss-of-lock process can occur at any stage of the optical clock timing and is uncontrollable. When it occurs during lattice loading or atom probing, it will cause the optical clock to lose atomic signals or provide incorrect feedback. To address this, a smaller safe voltage range (e.g., 2V~8V) can be set through the input voltage range and threshold adjustment circuit. When this range is exceeded, the over-range detection circuit outputs an out-of-range signal at a high level. Subsequently, the device will actively relock if programmable, thus promptly pulling the PZT control voltage, which is about to exceed the boundary, back to the safe range. This active relocking process can be programmed to be set during the first-stage magneto-optical trap loading stage of the optical clock operation, thereby avoiding affecting the normal operation of the optical clock.

[0066] As one possible implementation, the unlock detection circuit includes a third comparator circuit U33, a NOT gate circuit U35, and an unlock status indicator. The inverting input of the third comparator circuit U33 is connected to the adjustable terminal (the threshold voltage setting terminal for locking) of the third potentiometer 3; the non-inverting input is connected to the first SMA interface via a third RC network, allowing an external lock status identification signal (a cavity transmission signal in this embodiment) to be input to the non-inverting input; the output is connected to the input of the NOT gate circuit U35. The non-inverting input of the third comparator circuit U33 uses a configurable RC network to filter out logic spikes caused by pulses with excessively narrow widths (<10µs). The NOT gate circuit U35 uses an SN74LVC1G14 chip, with its power supply connected to the +5V output of power supply unit 1, its input connected to the output of the third comparator circuit U33, and its output (marked here as the Loss of Lock signal) connected to the unlock status indicator. The output voltage is 0V or +5V. Since the first comparator circuit U31, the second comparator circuit U32, and the third comparator circuit U33 all use the LM2901 chip with an open-drain output, they cannot directly output a high level. In order to output the comparison result correctly, the output of the LM2901 must be pulled up to a high level (+5V) through a resistor. That is, the inputs of the first NAND gate circuit U35 and the NOT gate circuit U35 are both pulled up to a high level. Therefore, when no low level is detected from the comparator circuit output, the voltage over-limit status indicator and the unlock status indicator are both off.

[0067] As one possible implementation, the first comparator circuit U31, the second comparator circuit U32, and the third comparator circuit U33 all set a hysteresis voltage (approximately 400mV in this embodiment of the invention) for the comparator through the resistor connected to the non-inverting input terminal and the hysteresis resistor connected between the output terminal and the non-inverting input terminal. The trigger voltage window is set within a certain range by the hysteresis voltage to eliminate the comparator's erroneous output caused by input signal noise jitter.

[0068] The logic control unit 4 is used to execute the following logic (the logic of the first OR gate circuit U41): It performs an OR operation on the Out of Range signal and the Loss of Lock signal to generate an Error signal. When the Out of Range signal is high (representing an out-of-range condition) or the Loss of Lock signal is high (representing a loss of lock), the Error signal is high (representing either an out-of-range condition or a loss of lock). When the Out of Range signal is low and both the Loss of Lock signal are low (representing neither an out-of-range condition nor a loss of lock), the Error signal is low (representing neither an out-of-range condition nor a loss of lock).

[0069] Logic control unit 4 is also used to perform the following logic (the logic of the second OR gate U42):

[0070] The scan execution signal Do Scanning is generated based on the enable switch Enable, the error signal Error, and the programmable enable lock operation signal TTL In.

[0071] If the enable switch is closed (meaning the error signal does not participate in the generation and judgment of the scan execution signal DoScanning), then the scan execution signal DoScanning is the same as the lock operation access signal DisableRelocking (the lock operation access signal DisableRelocking is the programmable enable lock operation signal TTLIn, which can force the generation of the scan execution signal DoScanning).

[0072] If the enable switch is in the off state (i.e., the error signal Error participates in the generation and judgment of the scan execution signal Do Scanning), then the error signal Error and the programmable enable lock operation signal TTL In are ORed to generate the scan execution signal Do Scanning.

[0073] When the enable switch is off and the programmable enable lock operation signal TTL In is low, if a loss of lock or over-limit occurs, the error signal Error is high, and the scan execution signal Do Scanning is high (indicating that a scan needs to be performed); if no loss of lock or over-limit occurs, the scan execution signal Do Scanning is low (indicating that a scan does not need to be performed).

[0074] Logic control unit 4 is also used to perform the following logic (AND gate U43 and the logic of the monostable pulse generator):

[0075] When the scan execution signal Do Scanning is high (indicating that scanning is required), the scan signal generator is controlled to perform scanning. The monostable pulse generator continuously outputs a high-level hold signal KeeppHolding, and the sampling mode signal ScanSH is high (indicating that during the scan, the single-chip sample-and-hold circuit is in sampling mode).

[0076] When the scan execution signal Do Scanning changes from high to low (representing recovery from over-limit and unlock failure or a switch from high to low in the programmable enable lock operation signal), the monostable pulse generator, triggered by the falling edge, holds the signal KeepHolding for a duration of T. set After the negative pulse, the signal returns to a high level. During the duration of the negative pulse, the sampling mode signal Scan SH is low (meaning that after the scan is completed, the scanning single-chip sample-and-hold circuit is set to holding mode).

[0077] When the scan execution signal Do Scanning is low (meaning no scanning is required), the monostable pulse generator continuously outputs a high-level hold signal KeeppHolding, and the sampling mode signal Scan SH is low (meaning that during non-scanning periods, the scan monolithic sample-and-hold circuit is set to hold mode).

[0078] The logic control unit 4 is also used to execute the following logic (the logic of the second NAND gate U44 and the third OR gate U45): performing a NAND operation on the hold signal Keeping and the error signal Error, and then performing an OR operation on the lock operation input signal Disable Relocking to obtain the lock signal Lock SH as the controller lock operation signal TTL Out (the controller lock operation signal TTL Out is input to the PID servo controller, and the output of the PID servo controller is input to the PDH module).

[0079] The PID servo controller operates in a level-maintenance mode rather than a trigger-based mode. It operates continuously when the controller lock operation signal TTL Out is high and does not operate when the controller lock operation signal TTL Out is low.

[0080] When the lock is not lost and the limit is not exceeded, the Error signal is low, requiring the PID servo controller to continue operating. The Lock SH signal, as the controller lock operation signal TTL Out, is high. The high-level controller lock operation signal TTL Out is output to the PID servo controller to maintain the locked state.

[0081] If there is no loss of lock or exceeding of limits, the Error signal is high, requiring the PID servo controller to stop working and start scanning. The Lock SH signal, as the controller lock operation signal TTL Out, is low. The low-level controller lock operation signal TTL Out is output to the PID servo controller to disable PID servo controller feedback and start scanning. When the lock point is found, the controller lock operation signal TTL Out will be pulled high again, enabling the PID servo controller to perform locking.

[0082] It is important to distinguish between the following: (a) When the error signal Error is low due to the absence of over-limit or unlocking, the scan execution signal Do Scanning remains low without any level transition, thus not triggering the monostable pulse generator, and the hold signal KeeppHolding remains high. (b) When the lock point is found, causing the error signal Error to transition from high to low, the scan execution signal Do Scanning will generate a high-to-low level transition (falling edge), triggering the monostable pulse generator to make the hold signal KeeppHolding low (last T level). set (After returning to high), that is, a negative pulse is generated.

[0083] In one possible implementation, the logic control unit 4 includes a first OR gate U41, a second OR gate U42, a third OR gate U45, an enable switch, an AND gate U43, a second NAND gate U44, and a monostable pulse generator. All OR gates use the SN74LVC1G32 chip, and their power supply terminals are connected to the +5V output of the power supply unit 1. Input terminal A of the first OR gate U41 is connected to the Loss of Lock signal output by the state detection unit 3; input terminal B is connected to the Out of Range signal output by the state detection unit 3; and the output terminal outputs an Error signal to input terminal B of the second OR gate U42 and one end of the enable switch, with the other end of the enable switch connected to electrical ground. Input A (marked as Disable Relocking) of the second OR gate U42 is connected to the second SMA interface, allowing selective input of the external programmable lock-up enable signal TTL In to input A, thereby enabling programmable lock-up shutdown. Input B (marked as Error) is connected to the output of the first OR gate U41 and one end of the enable switch. The output outputs the scan execution signal Do Scanning to input A of the AND gate U43 and the trigger signal input of the monostable pulse generator. Input A of the second OR gate U42 is pulled down to a low level (0V) through a resistor, ensuring that input A (Disable Relocking) remains low when there is no external TTL level input. When the programmable lock-up enable signal TTL In is high, the automatic lock-up device is disabled. The enable switch is a two-position switch, with one end connected to the output of the first OR gate U41 and input B (Error) of the second OR gate U42, and the other end connected to electrical ground. When the enable switch is closed (set to the Off position), the Error signal is forced to a low level, thereby enabling manual disabling of the automatic locking operation. The monostable pulse generator uses an LTC6993-3 chip, with its power supply terminal connected to the +5V output of power supply unit 1. The trigger signal input terminal is connected to the output terminal of the second OR gate circuit U42, and its output terminal (marked here as the hold signal KeepHolding) is connected to the input terminal B of the AND gate circuit U43 and the input terminal A of the second NAND gate circuit U44.The AND gate U43 uses an SN74LVC1G08 chip. Its power supply is connected to the +5V output of power supply unit 1. Input A is connected to the output of the second OR gate U42 (Do Scanning signal) and the trigger signal input of the monostable pulse generator. Input B is connected to the output of the monostable pulse generator (KeepHolding signal). The output (i.e., output A of logic control unit 4, here labeled as the sampling mode signal Scan SH) is connected to the sample-and-hold circuit. Input B of the AND gate U43 is pulled up to a high level (+5V) through a resistor. The second NAND gate U44 uses an SN74LVC1G132 chip. Its power supply is connected to the +5V output of power supply unit 1. Input A is connected to the output of the monostable pulse generator (KeepHolding signal). Input B is connected to the output of the first OR gate U41 (Error signal). The output is connected to input B of the third OR gate U45. The input terminal A of the third OR gate circuit U45 is connected to the second SMA interface and the input terminal A (Disable Relocking) of the second OR gate circuit U42. It can selectively input a programmable enable lock operation signal (programmable enable lock operation signal TTL In) from the outside to the input terminal A. The input terminal B is connected to the output terminal of the second NAND gate circuit U44. The output terminal (i.e. the output terminal B of the logic control unit 4, here the signal is marked as the lock signal Lock SH) is connected to the third SMA interface, and is used to output the lock signal Lock SH as the controller lock operation signal TTL Out of the PID servo controller.

[0084] As one possible implementation, the LTC6993-3 chip in the monostable pulse generator is triggered by a falling edge. This invention selects the LTC6993-3 with a falling edge triggering mode based on requirements. Its output pulse is triggered by a level change (falling edge) at the trigger signal input terminal (TRIG). Without external triggering, the pulse output terminal (KeepHolding) remains high. When the scan execution signal Do Scanning is high (in non-programmable mode, the error signal is high), the external scan signal, when finding a lock point (at which point the transmission signal reaches the set threshold), will cause the error signal to change from high to low (generating a falling edge). At this time, the monostable pulse generator is triggered to produce a T pulse. set A negative pulse of width, at T setThe PID servo controller is allowed to perform a lock once within a certain time period. Its peripheral circuit configuration is as follows: Pin 1 is the trigger signal input pin (TRIG). Pins 2 (GND) and 5 (V+) are power supply pins, connected to ground and +5V respectively. Pin 3 (SET) is the pulse width setting input pin, connected to resistor R. set Ground. Pin 4 (DIV) is the programmable divider and polarity input setting pin. The voltage (V) on the DIV pin... DIV Internally, it is converted to a 4-bit result (DIVCODE). DIV This voltage can be generated by a resistor divider between V+ and GND. The most significant bit (POL) of the DIVCODE determines the polarity of the signal output pin (OUT). When POL = 0, a positive pulse is generated; when POL = 1, a negative pulse is generated. In this embodiment of the invention, three resistors are connected in series between V+ and GND: resistor R... dta Resistance R dtb and resistance R db The fourth pin (DIV) uses resistor R. db The voltage drop across (i.e., V) DIV ), making V DIV / V+≈0.6566, corresponding to a frequency division ratio N DIV = 32768, POL = 1. The output pulse duration is calculated using the following formula: (The duration of the low level in TTL In is ≤ T) set ≤ TTLIn period). The sixth pin (OUT) is the pulse output pin. The negative pulse generated by the monostable pulse generator causes the locking device to be in the set T... set (Approximately 500ms in this invention example) Only one response is made within the time interval.

[0085] The logic control unit is designed with a timing control section. When the error signal transitions from high to low (meaning that both the unlocking and over-limit conditions have disappeared), it can generate a timing control function with a time width of T. set The negative pulse ensures that within the time width T set When the internal controller lock operation signal TTL out is high, the PID servo controller will only attempt a lock operation once (if the lock fails, it will be interrupted on T...). set The feature of automatically relocking after a certain time ensures that the PID has enough time to establish a stable and reliable lock, effectively avoiding the back-and-forth switching between the locking and scanning processes caused by jitter during the lock establishment process, thus improving the success rate of locking and the stability of the system.

[0086] Automatic locking unit 5 is used to execute the following logic:

[0087] If the Error signal is high (indicating an over-limit or loss of lock, requiring a scan), the Scan SH sampling mode signal is high (indicating a need to switch to scan mode), and the Lock SH lock signal is low (indicating a need for the PID servo controller to stop working), then the PID servo controller feedback signal Input and the Scan In signal are added together and limited to produce the Output signal.

[0088] If the error signal changes from high to low (indicating over-limit or loss of lock recovery, requiring hold), the sampling mode signal Scan SH switches from high to negative pulse (indicating switch to hold mode), and the lock signal Lock SH switches from low to high (indicating the PID servo controller needs to start working), then the scan signal when the sampling mode signal Scan SH switches from high to negative pulse and the PID servo controller feedback signal Input are added together and limited, and then used as the output signal Output (during this period, lock is performed). After the lock is performed for a set duration (10ms in this embodiment), the PID servo controller feedback signal Input is directly limited and used as the output signal Output.

[0089] The output signal is input to the PZT controller.

[0090] As one possible implementation, the automatic locking unit 5 includes a sample-and-hold circuit, an adder circuit, and an output voltage limiting circuit.

[0091] The sample-and-hold circuit includes a first analog switch circuit U51, a second analog switch circuit U52, a monolithic sample-and-hold circuit U53, a first follower circuit U54, and a second follower circuit U55. All analog switch circuits use the TMUX6136 chip and include a power supply terminal, an output terminal, input channels SA and SB. The power supply terminal is connected to the +12V and -12V voltages output from power supply unit 1. The truth table of the TMUX6136 chip states: when the channel selection control terminal (SEL) is low (logic 0), input channels SA and the output terminal are disconnected, and input channels SB and the output terminal are connected; when the channel selection control terminal (SEL) is high (logic 1), input channels SA and the output terminal are connected, and input channels SB and the output terminal are disconnected.

[0092] The input channel SA of the first analog switch circuit U51 is connected to the external scan signal Scan In (from pin A11 or C11 of the connector at the rear of the device), the input channel SB is connected to electrical ground, and the channel selection control terminal (SEL) is connected to the output terminal (error signal) of the first OR gate circuit U41. When the error signal Error is high (i.e., when an over-limit or below-threshold occurs), the external scan signal Scan In of the input channel SA is input to the monolithic sample-and-hold circuit, and the output terminal is connected to the analog signal input terminal of the monolithic sample-and-hold circuit U53. The monolithic sample-and-hold circuit U53 uses an LF298 chip. The power supply terminal is connected to the +12V and -12V voltages output by the power supply unit 1. The analog signal input terminal (first pin) is connected to the output terminal of the first analog switch circuit U51, the logic signal input terminal (eleventh pin) is connected to the output terminal (sampling mode signal Scan SH) of the AND gate circuit U43 of the logic control unit 4, and the output terminal is connected to the input terminal of the first follower circuit U54. The channel selection control terminal (SEL) of the first analog switch circuit U51 delays the error signal Error by approximately 10µs through a first RC delay circuit, ensuring that the sampling mode signal Scan SH, input to the logic signal input terminal of the monolithic sample-and-hold circuit U53, takes effect first. The first follower circuit U54 uses an OPA192 operational amplifier chip, with its power supply terminal connected to the +12V and -12V voltages output from power supply unit 1, its input terminal connected to the output terminal of the monolithic sample-and-hold circuit U53, and its output terminal connected to the input channel 2 of the second analog switch circuit U52.

[0093] The input channel SA of the second analog switch circuit U52 is connected to resistor R. rd The input channel SB is grounded and connected to the output of the first follower circuit U54. The channel selection control terminal (SEL) is connected to the output (Lock SH) of the third OR gate circuit U45, and the output terminal is connected to the input of the second follower circuit U55. The channel selection control terminal (SEL) of the second analog switch circuit U52 is connected to an optional second RC delay circuit, and a Schottky diode is connected in parallel across the resistor of the second delay circuit (the cathode and anode of the Schottky diode are electrically connected to the signal Lock SH and the channel selection control terminal (SEL) of the second analog switch circuit U52, respectively). This allows for selective delay of the lock signal Lock SH: delaying the high-level signal by approximately 10ms (i.e., when the error signal Error transitions from high to low after a scan), while allowing the low-level signal to pass through the diode immediately. A capacitor C is connected in series between the output of the second analog switch circuit U52 and electrical ground. rdDuring the scanning process (during which the scan signal generated by the scan signal generator passes sequentially through the first analog switch circuit U51, the monolithic sample-and-hold circuit, the first follower circuit U54, the second analog switch circuit U52, and the second follower before being input to one of the input terminals of the in-phase adder circuit; the output signal of the PID servo controller passes through the third follower before being input to the other input terminal of the in-phase adder circuit; the summed signal output by the adder is input to the output voltage limiting circuit; and the output voltage limiting circuit outputs the final output signal Output), capacitor C... rd The voltage across both ends will remain consistent with the scanning voltage. Approximately 10ms after the PID servo controller begins the locking operation (i.e., the controller locking operation signal TTL Out controls the PID servo controller to begin the locking operation), the capacitor C... rd Discharge begins, discharge time constant = R rd ×C rd The second follower circuit U55 uses an OPA210 operational amplifier chip. Its power supply terminal is connected to the +12V and -12V voltages output from power supply unit 1, its input terminal is connected to the output terminal of the second analog switch circuit U52, and its output terminal is connected to the input terminal of the non-inverting adder circuit. As one possible implementation, the operating mode of the monolithic sample-and-hold circuit U53 depends on the level of its logic signal input terminal. When the logic signal input terminal is high (+5V), it is in sampling mode; when the logic signal input terminal is low (0V), it is in holding mode. A holding capacitor C is connected between the eighth pin of the LF298 chip in the monolithic sample-and-hold circuit U53 and GND. h .

[0094] As one possible implementation, the two holding capacitors C in the sample-and-hold circuit h C rd PP (Polypropylene Capacitor) capacitors are used in all cases. These capacitors have extremely low dielectric absorption, which can reduce voltage spikes from scan to hold.

[0095] As one possible implementation, a more robust holding capacitor release circuit is designed in the sample-and-hold circuit. In terms of timing, the PID servo controller is activated first, and then the holding capacitor releases its voltage (during the scanning process, the voltage across the holding capacitor always follows the scanning voltage without delay), ensuring the reliability of cavity locking during capacitor release.

[0096] The adder circuit includes a fourth SMA interface and a non-inverting adder circuit. The third follower circuit U56 uses an OPA210 operational amplifier chip. Its power supply terminal is connected to the +12V and -12V voltages output from power supply unit 1. Its non-inverting input terminal is connected to the fourth SMA interface, allowing external input of PID servo controller feedback signals. Its output terminal is connected to the input terminal of the non-inverting adder circuit. The non-inverting adder circuit also uses an OPA210 operational amplifier chip. Its power supply terminal is connected to the +12V and -12V voltages output from power supply unit 1. Its input terminal is connected to the output terminal of the third follower circuit U56, the output terminal of the sample-and-hold circuit (the output terminal of the second follower circuit U55), and the input terminal of the output voltage limiting circuit. The non-inverting adder circuit is configured in a summing mode with a 1x inverting amplification through a resistor network, summing the externally input PID servo controller feedback signal and the sample-and-hold circuit output signal.

[0097] The output voltage limiting circuit includes an upper limit adjustment circuit, a lower limit adjustment circuit, and a fourth follower circuit U57. The upper limit adjustment circuit includes a fourth potentiometer, a fifth follower circuit U58, and a first diode. The lower limit adjustment circuit includes a fifth potentiometer, a sixth follower circuit U59, and a second diode. Both the fifth follower circuit U58 and the sixth follower circuit U59 use OPA2210 operational amplifier chips, and their power supply terminals are connected to the +12V and -12V voltages output from power supply unit 1, respectively. Both the first and second diodes are high-voltage switching diodes of model SMMSD103T1G. The first fixed terminal of the fourth potentiometer is connected to +12V, the second fixed terminal is connected to the output terminal of the sixth follower circuit U59 (marked as signal Vomin), and the adjustable terminal is connected to the non-inverting input terminal of the fifth follower circuit U58, used to set the upper limit value of the output voltage. The non-inverting input of the fifth follower circuit U58 is connected to the adjustable terminal of the fourth potentiometer, and its output (marked here as signal Vomin) is connected to the cathode of the first diode. The anode of the first diode is connected to the output of the non-inverting adder circuit and the non-inverting input of the fourth follower circuit U57, and its cathode is connected to the output of the fifth follower circuit U58. The first fixed terminal of the fifth potentiometer is connected to +12V, the second fixed terminal is connected to -12V, and its adjustable terminal is connected to the non-inverting input of the sixth follower circuit U59, used to set the lower limit of the output voltage. The non-inverting input of the sixth follower circuit U59 is connected to the adjustable terminal of the fifth potentiometer, and its output (marked here as signal Vomin) is connected to the anode of the second diode. The anode of the second diode is connected to the output of the sixth follower circuit U59, and its cathode is connected to the output of the adder circuit, the anode of the first diode, and the non-inverting input of the fourth follower circuit U57. The fourth follower circuit U57 uses an OPA210 operational amplifier chip. Its power supply terminal is connected to the +12V and -12V voltages output from power supply unit 1. Its non-inverting input terminal is connected to the output terminal of the adder circuit, the anode of the first diode, and the cathode of the second diode. Its output terminal is connected to the fifth SMA interface (Output, i.e., the output terminal of the automatic locking unit 5), used to output a control voltage signal to the PZT driver. Since the PZT driver can only withstand a certain range of positive voltages (typically 0~10V), the output voltage limiting circuit is used to output the drive voltage and protect the PZT driver.

[0098] Example 2:

[0099] An automatic locking method for the enhancement cavity of an optical lattice clock is disclosed. This method utilizes the automatic locking device for the enhancement cavity of an optical lattice clock as described in Example 1, along with necessary external components such as a scanning signal generator, a PZT controller, a PID servo controller, a locking cavity optical path, a photodetector, and a PDH module to complete the locking process. A schematic diagram of the connection of the locking cavity components is shown below. Figure 4 As shown. The 759nm lattice light generated by the laser is coupled into the 759nm enhancement cavity after passing through the isolator OI, the electro-optic phase modulator EOM, and the beam splitter prism BS. The cavity transmission signal (i.e., the lock-up state identification signal) output by the first photodetector PD1 is connected to the input terminal of the unlock detection circuit (the input terminal of the comparator circuit 3). The enhanced cavity reflected light is reflected by the beam splitter prism BS and collected by the second photodetector PD2 before being input to the PDH module. The error signal output terminal of the PDH module is connected to the PID servo controller, and the modulation signal output terminal is connected to the electro-optic phase modulator EOM. The optical lattice clock enhancement cavity automatic locking device is connected to an external scanning signal generator through pin A11 or C11 in its tail connector. The input terminal of the PZT controller is connected to the output terminal (output signal Output) of the output voltage limiting circuit of the automatic locking unit 5, and the output terminal is connected to the piezoelectric ceramic PZT on the enhancement cavity mirror. The enable signal input terminal of the PID servo controller is connected to the controller lock operation signal TTL Out output by the logic control unit 4, and the feedback signal output terminal is connected to the input terminal of the adder circuit of the automatic locking unit 5.

[0100] The piezoelectric ceramic PZT is fixed on the back of the first cavity mirror CM1 and the second cavity mirror CM2 of the enhancement cavity. By changing the voltage on the piezoelectric ceramic, the advance and retreat of the cavity mirrors can be changed to control the cavity length of the enhancement cavity.

[0101] The PZT controller can amplify the control voltage signal output by the automatic locking device and drive the piezoelectric ceramic to change the cavity length.

[0102] An automatic locking method for an optical lattice clock enhancement cavity includes the following steps:

[0103] State detection steps:

[0104] If the output signal Output (input to the PZT controller) of the automatic locking unit 5 is less than the upper limit of the input voltage and greater than the lower limit of the input voltage, the out of range signal is low (indicating that no out of range has occurred); if the output signal Output is greater than the upper limit of the input voltage or less than the lower limit of the input voltage, the out of range signal is high (indicating that an out of range has occurred).

[0105] If the lock status identification signal Signal is greater than the comparison threshold, the Loss of Lock signal is low (indicating no lock loss); if the lock status identification signal Signal is less than the comparison threshold, the Loss of Lock signal is high (indicating a lock loss).

[0106] Logic control steps:

[0107] An error signal, Error, is generated by performing an OR operation on the Out of Range signal and the Loss of Lock signal. When the Out of Range signal is high (indicating an out-of-range condition) or the Loss of Lock signal is high (indicating a loss of lock), the Error signal is high (indicating either an out-of-range condition or a loss of lock). When both the Out of Range signal and the Loss of Lock signal are low (indicating neither an out-of-range condition nor a loss of lock has occurred), the Error signal is low (indicating neither an out-of-range condition nor a loss of lock has occurred).

[0108] If the enable switch is closed (meaning the error signal does not participate in the generation and judgment of the scan execution signal DoScanning), then the scan execution signal DoScanning is the same as the lock operation access signal DisableRelocking (the lock operation access signal DisableRelocking is the programmable enable lock operation signal TTLIn, which can force the generation of the scan execution signal DoScanning).

[0109] If the enable switch is off (i.e., the error signal Error is involved in the generation and judgment of the scan execution signal Do Scanning), then the error signal Error and the programmable enable lock operation signal TTL In are ORed to generate the scan execution signal Do Scanning.

[0110] When the scan execution signal Do Scanning is high (indicating that scanning is required), the scan signal generator is controlled to perform scanning. The monostable pulse generator continuously outputs a high-level hold signal KeeppHolding, and the sampling mode signal ScanSH is high (indicating that during the scan, the single-chip sample-and-hold circuit is in sampling mode).

[0111] When the scan execution signal Do Scanning changes from high to low (representing recovery from over-limit and unlock failure or a switch from high to low in the programmable enable lock operation signal), the monostable pulse generator, triggered by the falling edge, holds the signal KeepHolding for a duration of T. set After the negative pulse, the signal returns to a high level. During the duration of the negative pulse, the sampling mode signal Scan SH is low (meaning that after the scan is completed, the scanning single-chip sample-and-hold circuit is set to holding mode).

[0112] When the scan execution signal Do Scanning is low (meaning no scanning is required), the monostable pulse generator continuously outputs a high-level hold signal KeeppHolding, and the sampling mode signal Scan SH is low (meaning that during non-scanning periods, the scan monolithic sample-and-hold circuit is set to hold mode).

[0113] The Keep signal (KeepHolding) and the Error signal (Error) are ANDed together. The resulting signal is then ORed with the Lock operation input signal (Disable Relocking) to obtain the Lock SH signal, which is used as the controller lock operation signal (TTL Out). The controller lock operation signal (TTL Out) is input to the PID servo controller, and the output of the PID servo controller is input to the PDH module.

[0114] Automatic locking steps:

[0115] If the Error signal is high (indicating an over-limit or loss of lock, requiring a scan), the Scan SH sampling mode signal is high (indicating a need to switch to scan mode), and the Lock SH lock signal is low (indicating a need for the PID servo controller to stop working), then the PID servo controller feedback signal Input and the Scan In signal are added together and limited to produce the Output signal.

[0116] If the error signal changes from high to low (indicating over-limit or loss of lock recovery, requiring hold), the sampling mode signal Scan SH switches from high to negative pulse (indicating switch to hold mode), and the lock signal Lock SH switches from low to high (indicating the PID servo controller needs to start working), then the scan signal when the sampling mode signal Scan SH switches from high to negative pulse and the PID servo controller feedback signal Input are added and limited, and then used as the output signal Output (during this period, lock is performed). After the lock lasts for a set time (10ms in this embodiment), the PID servo controller feedback signal Input is directly limited and used as the output signal Output.

[0117] The output signal is input to the PZT controller.

[0118] As one possible implementation method, a schematic diagram of the locking steps of an automatic locking method for an optical lattice clock enhancement cavity is shown below. Figure 5 As shown. With the enable switch in the "On" position, the system will determine a fault state when any of the following conditions are detected: 1) An output out of range signal is detected; 2) A loss of lock signal is detected.

[0119] As one possible implementation, the locking steps of an automatic locking method for an optical lattice clock enhancement cavity are as follows: First, set the output voltage range of the output voltage limiting voltage and the comparison threshold voltage of the lock-out detection circuit's lock-out status identification signal (Signal). Set the enable switch to the On position. During operation, the voltage value of the output signal (Output) and the cavity transmission signal will be continuously monitored. When the output signal (Output) voltage exceeds the limit or / and the lock-out status identification signal (Signal) indicates cavity lock-out, the over-limit indicator light and / or the lock-out status indicator light will illuminate respectively. The system determines this as a fault state. At this time, the feedback of the PID servo controller is temporarily disabled, the PID servo controller stops working, and the scanning mode is activated. The scanning signal generator outputs a scanning signal (usually a triangular wave) while simultaneously monitoring the lock-out status identification signal (Signal). When a suitable locking point is found, scanning stops, and the sample-and-hold circuit holds the instantaneous value of the scanning voltage at this time. Then, the PID servo controller is enabled to perform locking. Specifically, the instantaneous value of the scanning voltage when the locking point is found is added to the PID feedback signal (correction signal) and used as the output of the device. This output controls the PZT on the cavity mirror to change the cavity length, thereby locking the cavity length. After locking is executed, the sample-and-hold circuit releases all the held voltage to prepare for the next locking process.

[0120] As one possible implementation method, a schematic diagram of the control logic for an automatic locking method of an optical lattice clock enhancement cavity is shown below. Figure 6 As shown below, the effects of each signal state of the state detection unit 3, logic control unit 4 and automatic locking unit 5 during the locking process will be explained in detail.

[0121] As one possible implementation method, it should be noted that in the example of the present invention: high level = logic 1, low level = logic 0.

[0122] As one possible implementation, when an output voltage over-limit or / and cavity lockout is detected, Out of Range = 1 or / and Loss of Lock = 1, thus causing Error = 1, and the system determines it to be in a fault state. Error can be forcibly set to 0 using the enable switch on the front panel. When Error = 1, the Scan In signal (from pin A11 or C11) is fed to the LF298; otherwise, the input of the LF298 is connected to GND.

[0123] As one possible implementation, with the enable switch in the On position, the locking operation is enabled when the external input signal TTL In = 0 (default is 0 if there is no external input), and disabled when TTL In = 1. This function allows for programmable switching of the locking process. In conjunction with the timing of the optical clock operation, the locking process can be scheduled to execute within a suitable timeframe (such as the first-stage magneto-optical trap loading stage), avoiding interference with optical lattice loading or clock probing.

[0124] As one possible implementation, the transition of the Do Scanning signal from high to low level will occur under any of the following circumstances: Circumstance 1) When TTL In remains low (i.e., no external programmable enable lock operation signal input), Error changes from high to low (i.e., a lock point is found during scanning); Circumstance 2) When Error remains low, TTL In changes from high to low (i.e., no output voltage over-limit or / and cavity lockout is detected, only the DisableRelocking level changes).

[0125] As one possible implementation, when Scan SH = 1 or Scan SH = 0, the LF298 will enter either sampling mode or holding mode, respectively.

[0126] As one possible implementation, with TTL In enabled for latch-up operation (TTL In = 0), the width of the monostable pulse generator output is T. set The negative pulse signal KeepHolding passes through the AND gate circuit U43, causing the input sample-and-hold circuit signal Scan SH to also remain T. setThe low level of time. If at T set If a lock is successfully established within the specified time period, Scan SH will remain low until Error = 1, at which point a relocking process will be initiated; if T set Unable to lock within the specified time period (rare case), Scan SH in T set After the process ends, the signal goes high, and the system will restart the scan to find the lock point and perform the relocking process again.

[0127] As one possible implementation, when Scan SH = 0, the LF298 will enter holding mode. The LTC6993-3 will detect the falling edge and output a negative pulse, maintaining Scan SH = 0 for a period of time through the AND gate U43 (i.e., the duration T of the negative pulse output by the monostable pulse generator). set During this period, the LF298 will either maintain the instantaneous value of the Scan In signal when Error goes low (corresponding to case 1 above) or simply maintain a level of 0 (corresponding to case 2 above).

[0128] As one possible implementation, it should be noted that scenario 1 above is typical, but scenario 2 is more special. To illustrate the effectiveness of scenario 2, consider the following situation: when TTL In changes from high to low, the system is in a normal locking state. However, in the final stage of TTL In's low level, the output control voltage exceeds the safe range, causing Error = 1. If Scan SH is not held low, the system will begin the scanning process, and TTL In may become high (disabling relocking) before the locking point is found, leading to relocking failure. Scenario 2 ensures that the relocking process will not be initiated without sufficient relocking time, improving system stability.

[0129] As one possible implementation, Lock SH is used for: 1) internal control to apply the scan signal to the output of the automatic locking device (logic 0 → apply the scan signal to the output of the automatic locking device, logic 1 → disconnect the scan signal and force C through analog switch 2). rd 1) Discharge); 2) Output as an enable signal to an external PID servo controller to enable it to perform locking or disable locking (logic 1 → perform locking, logic 0 → disable locking).

[0130] As one possible implementation, a delay circuit consisting of a Schottky diode and an RC circuit is used to delay the high level of the internal Lock SH by approximately 10ms, ensuring that the PID servo controller operates within the specified range. rd Sufficient time is allowed to perform the enhancement cavity locking operation before discharge, thus enabling the PID servo controller to operate at capacitor C. rd Establish a lock before discharging.

[0131] As one possible implementation, Lock SH = 1 when any of the following conditions are met: 1) DisableRelocking = 1; 2) Error = 0; 3) Keeping = 0.

[0132] As one possible implementation, it should be noted that the example of this invention is only a typical application case of the automatic locking device for the optical lattice clock enhancement cavity. For applications of this invention in other scenarios, the type of locking state identification signal can be changed, and the comparison threshold voltage of the locking state identification signal can be adjusted accordingly for automatic locking of other types of optical cavities or lasers, demonstrating strong application scalability.

[0133] It should be noted that the embodiments described in this invention are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains can make various modifications or additions to the described embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.

Claims

1. An automatic locking device for an optical lattice clock enhancement cavity, comprising a logic control unit, characterized in that, The logic control unit includes a first OR gate (U41). A loss of lock signal and an out of range signal are connected to input terminals A and B of the first OR gate (U41), respectively. The output terminal of the first OR gate (U41) outputs an error signal. A programmable enable lock operation signal (TTL In) is connected to input terminals A of the second OR gate (U42) and the third OR gate (U45), respectively. The error signal is connected to input terminals B of the second OR gate (U42) and the second NAND gate (U44), respectively. The error signal is connected to electrical ground via an enable switch. The output terminal of the second OR gate (U42) outputs a scan execution signal (Do Scanning). The Scanning signal is connected to the input terminal A of the AND gate (U43) and the trigger signal input terminal of the monostable pulse generator. The output terminal of the monostable pulse generator outputs a hold signal (KeepHolding). The hold signal (KeepHolding) is connected to the input terminal B of the AND gate (U43) and the input terminal A of the second NAND gate (U44). The output terminal of the AND gate (U43) outputs a sampling mode signal (Scan SH). The output terminal of the second NAND gate (U44) is connected to the input terminal B of the third OR gate (U45). The output terminal of the third OR gate (U45) outputs a lock signal (Lock SH) as the controller lock operation signal (TTL Out) of the PID servo controller.

2. The automatic locking device for the optical lattice clock enhancement cavity according to claim 1, characterized in that, The input terminal A of the second OR gate (U42) is connected to electrical ground through a resistor, and the input terminal B of the AND gate (U43) is connected to a +5V power supply through a resistor.

3. The automatic locking device for the optical lattice clock enhancement cavity according to claim 1, characterized in that, It also includes an automatic locking unit, which comprises a first analog switch circuit (U51). The input channels SA and SB of the first analog switch circuit (U51) are connected to an external scan signal (Scan In) and electrical ground, respectively. An error signal (Error) is input to the channel selection control terminal of the first analog switch circuit (U51). The output terminal of the first analog switch circuit (U51) is connected to the analog signal input terminal of a monolithic sample-and-hold circuit (U53). The logic signal input terminal of the monolithic sample-and-hold circuit (U53) is connected to the sampling mode signal (Scan SH). The output terminal of the monolithic sample-and-hold circuit (U53) is connected to the input terminal of a first follower circuit (U54). The output terminal of the first follower circuit (U54) is input to the input channel SB of a second analog switch circuit (U52). The input channel SA of the second analog switch circuit (U52) is connected to electrical ground through a resistor. A lock signal (Lock) is input to the input channel SB. The input signal (SH) is fed to the channel selection control terminal of the second analog switch circuit (U52). The output terminal of the second analog switch circuit (U52) is connected to the input terminal of the second follower circuit (U55). The feedback signal (Input) of the PID servo controller is fed to the input terminal of the third follower circuit (U56). The output terminals of the second follower circuit (U55) and the third follower circuit (U56) are respectively connected to the two input terminals of the in-phase adder circuit.

4. The automatic locking device for the optical lattice clock enhancement cavity according to claim 3, characterized in that, The error signal (Error) is input to the channel selection control terminal of the first analog switch circuit (U51) through the first RC delay circuit, and the lock signal (Lock SH) is input to the channel selection control terminal of the second analog switch circuit (U52) through the second RC delay circuit. A Schottky diode is connected in parallel across the resistor of the second RC delay circuit, and the cathode and anode of the Schottky diode are electrically connected to the lock signal (Lock SH) and the channel selection control terminal of the second analog switch circuit (U52), respectively.

5. The automatic locking device for the optical lattice clock enhancement cavity according to claim 3, characterized in that, It also includes an upper limit output voltage adjustment circuit, a lower limit output voltage adjustment circuit, and a fourth follower circuit (U57). The upper limit output voltage adjustment circuit includes a fourth potentiometer, a fifth follower circuit (U58), and a first diode. The lower limit output voltage adjustment circuit includes a fifth potentiometer, a sixth follower circuit (U59), and a second diode. The adjustable terminal of the fourth potentiometer is connected to the non-inverting input terminal of the fifth follower circuit (U58). The output terminal of the fifth follower circuit (U58) is connected to the cathode of the first diode. The anode of the first diode is connected to the output terminal of the non-inverting adder circuit. The non-inverting input terminal of the fourth follower circuit (U57) is connected to the output terminal of the non-inverting adder circuit. The output terminal of the fourth follower circuit (U57) outputs an output signal. The adjustable terminal of the fifth potentiometer is connected to the non-inverting input terminal of the sixth follower circuit (U59). The output terminal of the sixth follower circuit (U59) is connected to the anode of the second diode. The cathode of the second diode is connected to the output terminal of the non-inverting adder circuit.

6. The automatic locking device for the optical lattice clock enhancement cavity according to claim 5, characterized in that, It also includes an over-range detection circuit, which comprises a first comparator circuit (U31), a second comparator circuit (U32), a first NAND gate circuit (U34), and a voltage over-range status indicator. The inverting input of the first comparator circuit (U31) is connected to the adjustable terminal of the second potentiometer, the non-inverting input of the first comparator circuit (U31) is connected to the output signal, the output of the first comparator circuit (U31) is connected to the input terminal A of the first NAND gate circuit (U34), the inverting input of the second comparator circuit (U32) is connected to the output signal, the non-inverting input of the second comparator circuit (U32) is connected to the adjustable terminal of the first potentiometer, the output of the second comparator circuit (U32) is connected to the input terminal B of the first NAND gate circuit (U34), the output of the first NAND gate circuit (U34) outputs an out-of-range signal, and the output of the first NAND gate circuit (U34) is connected to the voltage over-range status indicator.

7. The automatic locking device for the optical lattice clock enhancement cavity according to claim 5, characterized in that, It also includes a loss-of-lock detection circuit, which includes a third comparator circuit (U33), a NOT gate circuit (U35), and a loss-of-lock status indicator. The inverting input of the third comparator circuit (U33) is connected to the adjustable input of the third potentiometer. The lock status identification signal is connected to the non-inverting input of the third comparator circuit (U33) through the third RC delay circuit. The output of the third comparator circuit (U33) is connected to the input of the NOT gate circuit (U35). The output of the NOT gate circuit (U35) outputs a loss-of-lock signal. The output of the NOT gate circuit (U35) is connected to the loss-of-lock status indicator.

8. A method for automatically locking an optical lattice clock enhancement cavity, utilizing the automatic locking device for an optical lattice clock enhancement cavity as described in any one of claims 1-7, characterized in that, Includes the following steps: State detection steps: If the output signal is less than the upper limit of the input voltage and greater than the lower limit of the input voltage, the out-of-range signal is low; if the output signal is greater than the upper limit of the input voltage or less than the lower limit of the input voltage, the out-of-range signal is high. If the lock status identification signal is greater than the comparison threshold, the loss of lock signal is low; if the lock status identification signal is less than the comparison threshold, the loss of lock signal is high. Logic control steps: An error signal is generated by performing an OR operation on the Out of Range and Loss of Lock signals. The error signal is high when either the Out of Range or Loss of Lock signal is high, and low when both signals are low. If the enable switch is closed, the scan execution signal (Do Scanning) is the same as the lock operation access signal (Disable Relocking); If the enable switch is off, the error signal and the programmable enable lock operation signal (TTLIn) are ORed to generate the scan execution signal (Do Scanning). When the scan execution signal (Do Scanning) is high, the scan signal generator is controlled to perform scanning, the monostable pulse generator continuously outputs a high-level hold signal (KeepHolding), and the sampling mode signal (Scan SH) is high. When the scan execution signal (Do Scanning) changes from high to low, the monostable pulse generator, triggered by the falling edge, holds the signal (KeepHolding) for a duration of T. set After the negative pulse, the signal returns to a high level, and during the duration of the negative pulse, the sampling mode signal (Scan SH) is at a low level. When the scan execution signal (Do Scanning) is low, the monostable pulse generator continuously outputs a high-level hold signal (KeepHolding), and the sampling mode signal (Scan SH) is low; The Keep signal and Error signal are ANDed together, and the resulting signal is then ORed with the Disable Relocking signal to obtain the Lock SH signal, which is used as the controller's lock operation signal (TTL Out). Automatic locking steps: If the error signal (Error) is high, the sampling mode signal (Scan SH) is high, and the lock signal (Lock SH) is low, then the PID servo controller feedback signal (Input) and the scan signal (Scan In) are added together and limited to obtain the output signal (Output). If the error signal changes from high to low, the sampling mode signal (Scan SH) switches from high to negative pulse, and the lock signal (Lock SH) switches from low to high, then the scan signal when the sampling mode signal (Scan SH) switches from high to negative pulse and the PID servo controller feedback signal (Input) are added together and limited, and then used as the output signal (Output) to perform locking. After the locking lasts for a set time, the PID servo controller feedback signal (Input) is directly limited and used as the output signal (Output). The output signal is input to the PZT controller.

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