Data cache optimization method, device and equipment of automotive MCU and storage medium

Abstract

The application provides a data cache optimization method, device and equipment of a vehicle-grade MCU and a storage medium, the method comprising: constructing a multi-target cache decision by predicting a future data access probability distribution, taking into account real-time performance and memory utilization. By dividing the cache into different priority logical partitions and dynamically adjusting the partition size, an adaptive cache layout is formed. In combination with the access probability distribution and the partition strategy, a dynamic prefetch threshold is set and data prefetching is performed, while elimination and update are performed within the task execution period, thereby improving the cache efficiency and stability of the vehicle-grade MCU in a high-temperature and strong-vibration environment, and the application is suitable for vehicle-mounted control systems with strict requirements for safety and performance.

Description

Technical Field

[0001] This invention relates to the field of caching technology, and in particular to a data caching optimization method, apparatus, device, and storage medium for automotive-grade MCUs. Background Technology

[0002] In automotive-grade microcontroller (MCU) systems, data caching strategies directly impact the real-time performance and stability of the vehicle's electronic control unit (ECU). Traditional data caching methods are mostly based on fixed-size or static partitions, which cannot flexibly adapt to different types of data access needs, making it difficult to balance system response speed with memory utilization and power consumption. With the popularization of autonomous driving and vehicle networking technologies, the requirements for data throughput and real-time response of automotive-grade MCUs are constantly increasing, and the complexity of information interaction between different sensors and subsystems is also increasing. The limitations of traditional caching strategies in areas such as cache space allocation, data prefetching, and eviction mechanisms are becoming increasingly apparent.

[0003] Furthermore, automotive-grade MCU systems operate in harsh environments characterized by high temperatures and strong vibrations, necessitating strict control over hardware resources and power consumption. Conventional approaches like "large cache" or "high bandwidth" are not suitable. Failure to dynamically adjust the caching strategy based on real-time data access patterns can easily lead to wasted cache space or frequent cache replacements, impacting the efficiency of the entire control system. Especially at high speeds, a large amount of sensor data needs to be processed and analyzed within a very short time; if the caching strategy lacks specificity, the safety and stability of the vehicle system will be potentially threatened. Summary of the Invention

[0004] The main objective of this invention is to solve the technical problem that the fixed caching strategy in existing automotive-grade MCU systems cannot flexibly adapt to the changing data access requirements, thus making it difficult to balance system response speed, memory utilization and power consumption. The first aspect of this invention provides a data cache optimization method for automotive-grade MCUs, the data cache optimization method for automotive-grade MCUs comprising: Data access operations in the automotive-grade MCU system are recorded and statistically analyzed, and the data access operations are predicted using a preset long short-term memory network to obtain the data access probability distribution within a future time window. A multi-objective optimization problem is constructed and solved based on the data access probability distribution to obtain a set of cache decisions. Based on the cache decision set, the cache space is divided into multiple logical partitions with different priorities, and the size of each logical partition is dynamically adjusted according to the real-time monitored cache performance indicators to obtain an adaptive partitioned cache space. Based on the data access probability distribution and the cache space, a dynamic prefetch threshold is set and a data prefetch operation is performed. At the same time, cached data is evicted within the task execution cycle to obtain optimized cached content.

[0005] Optionally, in a first implementation of the first aspect of the present invention, the step of recording and statistically analyzing data access operations in the automotive-grade MCU system, and using a preset long short-term memory network to predict the data access operations to obtain the data access probability distribution within a future time window includes: Record the data access operations in the automotive-grade MCU system to obtain raw access data including access frequency, access order and data size; The original access data is segmented into time series to obtain multiple data segments with fixed lengths; The data fragments are input into a preset long short-term memory network to obtain the data access probability distribution of each data item within a future time window.

[0006] Optionally, in a second implementation of the first aspect of the present invention, the step of constructing and solving a multi-objective optimization problem based on the data access probability distribution to obtain a set of cache decisions includes: Based on the data access probability distribution, calculate the expected access frequency and importance weight of each data item, and construct a multi-objective optimization problem based on the expected access frequency and importance weight. The multi-objective optimization problem is transformed into the state space and action space of a deep Q-network, where the state space contains the current cached content and the expected access frequency of data items, and the action space contains the caching decision for each data item. The transformed multi-objective optimization problem is solved iteratively using a pre-defined deep Q-network algorithm to obtain the state-action value function; Based on the state-action value function, different combinations of caching decisions are evaluated, and based on the evaluation results, a set of caching decisions that are balanced across multiple objectives is selected to form a caching decision set that is approximately Pareto optimal.

[0007] Optionally, in a third implementation of the first aspect of the present invention, the step of dividing the cache space into multiple logical partitions with different priorities based on the cache decision set, and dynamically adjusting the size of each logical partition according to real-time monitored cache performance indicators to obtain an adaptive partitioned cache space includes: Based on the decision priorities in the cache decision set, the cache space is divided into multiple logical partitions, and an initial size and priority are assigned to each logical partition to form an initial partition state; Real-time monitoring of cache performance metrics for each logical partition yields current cache performance data. This cache performance data is then combined with the initial partition state to construct the state input for reinforcement learning. The state input is fed into a preset reinforcement learning model, and the policy network is used by the reinforcement learning model to generate an action probability distribution. Based on the action probability distribution, the adjustment action of each logical partition size is sampled. The adjustment action is performed to update the size of each logical partition, obtain the cache space of the adaptive partition, and calculate the reward value after the adjustment action is performed. The reward value is obtained based on the degree of improvement in cache performance after the adjustment, and the reward value is used to update the policy network of the reinforcement learning model.

[0008] Optionally, in a fourth implementation of the first aspect of the present invention, the step of dividing the cache space into multiple logical partitions according to the decision priority in the cache decision set, allocating an initial size to each logical partition, and forming an initial partition state includes: Calculate a priority score for each cache decision in the cache decision set to obtain a decision priority score set, and perform cluster analysis on the cache decisions based on the decision priority score set to obtain the decision priority of each cache decision; Based on the decision priority, the number and type of logical partitions are determined, and the cache space is divided and memory is allocated according to the number and type of logical partitions to obtain multiple non-contiguous memory regions, forming logical partitions. Assign a unique identifier and access control attributes to each logical partition, establish a partition index table, and generate the initial partition state by combining the initial size of the logical partition and the partition index table.

[0009] Optionally, in a fifth implementation of the first aspect of the present invention, the step of setting a dynamic prefetch threshold and performing a data prefetch operation based on the data access probability distribution and the cache space, while simultaneously evicting cached data within the task execution cycle to obtain optimized cached content includes: Based on the data access probability distribution and the cache space, calculate the current cache utilization rate, and based on the current cache utilization rate and the data access probability distribution, dynamically calculate the probability threshold for prefetching trigger; Based on the prefetch trigger probability threshold, determine the data items that need to be prefetched, perform a prefetch operation on the data items that need to be prefetched, and load the data items that need to be prefetched into the cache; For periodic tasks, the task execution cycle and data lifecycle of each task are recorded, and based on the task execution cycle and data lifecycle, it is determined whether the data items in the cache have expired. Data items deemed expired are evicted from the cache, resulting in optimized cached content.

[0010] Optionally, in a sixth implementation of the first aspect of the present invention, the step of calculating the current cache utilization rate based on the data access probability distribution and the cache space, and dynamically calculating the probability threshold for prefetching triggering based on the current cache utilization rate and the data access probability distribution, includes: The cache usage statistics of each logical partition in the cache space of the adaptive partition are performed to obtain a set of partition usage rates, and the overall cache usage rate is calculated based on the set of partition usage rates. The cumulative probability is calculated on the data access probability distribution to obtain the cumulative probability distribution curve, and an initial prefetch probability threshold is determined on the cumulative probability distribution curve based on the overall cache utilization rate. Based on the initial prefetch probability threshold and the current system load, a dynamic adjustment function is applied to obtain the prefetch trigger probability threshold.

[0011] A second aspect of the present invention provides a data cache optimization device for automotive-grade MCUs, the data cache optimization device for automotive-grade MCUs comprising: The access prediction module is used to record and count the data access operations in the automotive-grade MCU system, and use a preset long short-term memory network to predict the data access operations to obtain the data access probability distribution within the future time window. The multi-objective optimization module is used to construct and solve a multi-objective optimization problem based on the data access probability distribution, and obtain a set of cache decision sets. The partition adjustment module is used to divide the cache space into multiple logical partitions with different priorities based on the cache decision set, and dynamically adjust the size of each logical partition according to the real-time monitored cache performance indicators to obtain an adaptive partition cache space. The prefetch eviction module is used to set a dynamic prefetch threshold and perform data prefetching operations based on the data access probability distribution and the cache space, and at the same time evict cached data based on the task execution cycle to obtain optimized cached content.

[0012] A third aspect of the present invention provides a data cache optimization device for automotive-grade MCUs, comprising: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a circuit; the at least one processor invokes the instructions in the memory to cause the data cache optimization device for automotive-grade MCUs to perform the steps of the above-described data cache optimization method for automotive-grade MCUs.

[0013] A fourth aspect of the present invention provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the steps of the above-described data cache optimization method for automotive-grade MCUs.

[0014] The aforementioned data caching optimization method, apparatus, device, and storage medium for automotive-grade MCUs construct multi-objective caching decisions by predicting future data access probability distributions, balancing real-time performance and memory utilization. By dividing the cache into logical partitions of different priorities and dynamically adjusting the partition sizes, an adaptive cache layout is formed. Combining access probability distributions and partitioning strategies, a dynamic prefetch threshold is set and data prefetching is performed, while replacement and updates are conducted within the task execution cycle. This improves the caching efficiency and stability of automotive-grade MCUs in high-temperature and high-vibration environments, making it suitable for automotive control systems with stringent safety and performance requirements.

[0015] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the first embodiment of the data caching optimization method for automotive-grade MCUs in this invention; Figure 2 This is a schematic diagram of one embodiment of the data cache optimization device for automotive-grade MCUs in this invention; Figure 3 This is a schematic diagram of an embodiment of the data caching optimization device for automotive-grade MCUs in this invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0020] To facilitate understanding of this embodiment, a data cache optimization method for automotive-grade MCUs disclosed in this embodiment will first be described in detail. For example... Figure 1 As shown, this method includes the following steps: 101. Record and statistically analyze the data access operations in the automotive-grade MCU system, and use a preset long short-term memory network to predict the data access operations to obtain the data access probability distribution within the future time window; In one embodiment of the present invention, the step of recording and statistically analyzing data access operations in the automotive-grade MCU system and predicting the data access operations using a preset long short-term memory network to obtain the data access probability distribution within a future time window includes: recording data access operations in the automotive-grade MCU system to obtain raw access data containing access frequency, access order, and data size; performing time series segmentation on the raw access data to obtain multiple data segments with fixed lengths; and inputting the data segments into the preset long short-term memory network to obtain the data access probability distribution of each data item being accessed within a future time window.

[0021] Specifically, the process of recording and statistically analyzing data access operations in an automotive-grade MCU system requires real-time or near-real-time interception of data access requests at the file I / O level of the underlying communication bus or embedded operating system. Upon receiving the access command, the module synchronizes relevant information such as access frequency, access order, and data size to the recording module. This recording module continuously writes data access logs to the MCU's internal non-volatile storage area or a dedicated circular buffer, ensuring complete retention of access trajectories even under complex conditions such as high system load or vehicle acceleration. The log structure includes multiple fields such as timestamp, source address, target file identifier, data byte length, and current task type. Efficient query capabilities are maintained through appropriately configured data headers and indexing methods. In parallel, the recording module, in conjunction with the MCU's task scheduling and interrupt management mechanisms, monitors access conflicts arising from priority differences, ensuring that access from different tasks is correctly distinguished and included in the statistical process. This recording method relies on a lightweight queue or event-driven model, decoupling the access logs from background and foreground tasks to avoid blocking the main control program. After the above recording operation is completed, a set of raw access data containing dimensions such as access frequency, access order and data size will be obtained. These elements constitute the raw material for subsequent data mining and pattern prediction. They can be stored in the MCU or external storage in the form of two-dimensional or multi-dimensional arrays to support the time series segmentation operation in the next stage.

[0022] Specifically, when performing time-series segmentation on the raw access data, the multi-dimensional access logs obtained in the previous stage need to be pruned according to a fixed time step or an equal number of requests. To adapt to the significant time-varying characteristics of data access in automotive-grade environments, the segmentation process tends to use a fixed-length window, aggregating the timestamps, access frequencies, and task context contained in each log segment, and calculating the access amplitude, access peak, and corresponding context label for each subsequence. Using a fixed-length window helps to form uniform training units, thereby maintaining stable gradient flow in subsequent model training. To present more nuanced temporal features, the mean and variance of each segment can be calculated after segmentation, or a smoother time-series curve can be generated using the moving average method. Some implementations also introduce exponential smoothing and other processing techniques to reduce data jitter caused by state transitions such as vehicle start-up or emergency braking. After segmentation, each time segment is usually packaged into a sample, which contains a serialized access feature vector and a fixed-dimensional context description, facilitating batch processing under the same format when inputting into the model. Storing multiple segmented time segments in a queue or tensor structure helps the Long Short-Term Memory network receive parallel or sequential inputs, thereby improving efficiency during both training and inference phases through hardware acceleration or software optimization.

[0023] Specifically, when inputting the segmented time segments into the pre-defined Long Short-Term Memory (LSTM) network, the access vectors from each sample need to be sequentially fed into the LSTM unit, with the parameters of the forget gate, input gate, and output gate continuously updated during the iteration process, thereby learning the temporal dependencies of the access sequence. Through backpropagation and gradient descent, the network can converge to suitable parameters after several rounds of training, enabling it to learn long-term dependencies and short-term dynamic changes. During the testing phase, a new access sequence is input into the trained LSTM model, which outputs a prediction vector representing the probability of each data item being accessed within a future time window. This prediction result is typically presented as a probability distribution, yielding the likelihood of each data block being requested. Subsequent steps can incorporate this probability distribution to implement caching strategies and adaptively update model parameters during actual operation, ensuring high prediction accuracy and efficiency in the hardware-constrained environment of automotive-grade MCUs.

[0024] 102. Construct and solve a multi-objective optimization problem based on the data access probability distribution to obtain a set of cache decision sets; In one embodiment of the present invention, the step of constructing and solving a multi-objective optimization problem based on the data access probability distribution to obtain a set of cache decisions includes: calculating the expected access frequency and importance weight of each data item according to the data access probability distribution, and constructing a multi-objective optimization problem based on the expected access frequency and importance weight; transforming the multi-objective optimization problem into the state space and action space of a deep Q-network, wherein the state space contains the current cached content and the expected access frequency of the data item, and the action space contains the cache decision for each data item; iteratively solving the transformed multi-objective optimization problem using a preset deep Q-network algorithm to obtain a state-action value function; evaluating different combinations of cache decisions based on the state-action value function, and selecting a set of cache decisions that are balanced across multiple objectives based on the evaluation results to form an approximately Pareto optimal set of cache decisions.

[0025] Specifically, based on the data access probability distribution, the expected access frequency and importance weight of each data item are calculated. The process of constructing a multi-objective optimization problem based on these expected access frequencies and importance weights first requires reading the probability distribution matrix output by the prediction model in the automotive-grade MCU environment and assigning an access probability value to each data item. Subsequently, a quantitative analysis of the importance of the data based on key vehicle components or real-time control tasks is needed to form a set of weight coefficients reflecting the access criticality. To improve calculation accuracy, a common practice is to establish a comprehensive weight function for each data item, mapping its access probability and criticality to several measurable indicators, such as letting... ,in Representing the The probability of accessing each data item. This represents the importance of the corresponding data. and These are coefficients used to adjust the contribution of access probability and security importance. Next, based on these combined weights, multi-dimensional objectives need to be evaluated simultaneously, such as improving hit rate, reducing access latency, and controlling cache power consumption, forming a multi-objective optimization function. If... Indicates the first The retention policy of each data item in the cache (1 for retention, 0 for removal) can be used to write several constraints on performance and energy consumption into the cost function, and the trade-offs between multiple objectives can be represented in vector form, for example, by constructing a vector. ,in Measure average access latency, Measure cache space usage or power consumption. The system measures the support for automotive-grade critical tasks. By assigning different roles to the access probability and importance weights of data items in the vector function, the optimization process can be made more targeted. After setting up the multi-objectives, the system encapsulates the function objectives to be minimized or maximized, along with various constraints, into the problem description to be solved, preparing for the subsequent mapping of the problem to the state and action space of a deep Q-network. This process needs to consider the real-time requirements of automotive-grade MCUs; therefore, simple matrix or tensor operations should be used to complete the entire process of weight calculation and objective construction to reduce the computational load on the embedded platform. When transforming the multi-objective optimization problem into the state and action space of a deep Q-network, the state vector needs to be defined using the current cached content and the expected access frequency of each data item as core information. Typically, the state vector can be represented as... ,in Indicates time The system's cached resource configuration, cached capacity, or specific data residency status. The cache space can be a set of access probabilities or a normalized array of weights, allowing the network to evaluate the access frequency and criticality of each data item during decision-making. The action space contains caching decisions for each data item, indicating how to handle it in the next time slice: whether to retain it in the cache, replace it with slower storage, or perform prefetching or other expansion operations. Since the input to a deep Q-network is typically a fixed-dimensional tensor, the cache configuration information in each state needs to be serialized or vectorized so that the network's feedforward computation layer can receive this information smoothly. In implementation, a common approach is to represent whether a data item is in the cache using binary mapping or sparse coding, combining it with its corresponding access probability to form a merged vector, which is then used as part of the state space. The action space can be quantized using multi-dimensional discrete actions or a discrete-continuous hybrid action approach. If the system tends to make binary retention or removal decisions, the number of actions will be relatively small; if adaptive partitioning or multi-level caching strategies need to be incorporated, more dimensions will be included in the actions. After transformation, the current state is selected in each network iteration. With a certain action Furthermore, in the environmental feedback stage, a comprehensive benefit or cost for multiple objectives is obtained, which is used to update the parameters of the deep Q network, enabling the network to continuously improve its ability to accommodate different objectives during repeated iterations.

[0026] Specifically, when iteratively solving the transformed multi-objective optimization problem using a pre-defined deep Q-network algorithm, the state, actions, and immediate rewards of the multiple objectives need to be combined into the core elements of the deep reinforcement learning loop. This is typically achieved by constructing an experience-based replay mechanism to randomly extract several experiences from historical decision samples. Used for batch training to ensure the stability of network convergence.

[0027] In each iteration, an ε-greedy or soft policy approach is first selected, and the optimal action is chosen based on the output value of the Q-network. Then, the environment state and cache configuration are updated according to the selected action. The new state and the feedback gains or costs are then stored in the replay pool to train the deep Q-network. Through multiple iterations, the Q-network gradually learns to assign higher Q values ​​to data items with higher access frequency or more prominent weights, and to reduce Q values ​​for combinations that are detrimental to power consumption or cache utilization. In automotive-grade MCU environments, this process needs to consider hardware limitations to simplify the network structure or reduce model computational overhead through techniques such as pruning and quantization, thereby ensuring efficient iteration of multi-objective optimization problems under limited computing resources. The process of evaluating different cache decision combinations based on the state-action value function and selecting a set of cache decisions that are balanced across multiple objectives based on the evaluation results, forming a near Pareto optimal cache decision set, can be achieved by collecting several high Q-value action sequences after each iteration. In implementation, several state-action pairs that successfully balance various objectives can be selected from the replay pool or online decision trajectory. Further testing is then performed based on their corresponding Q-values ​​to determine if they are within acceptable ranges for metrics such as access latency, power consumption, and cache usage. If several records demonstrate irreplaceable advantages across different metrics, these action combinations will be incorporated into the Pareto front set and executed in diverse forms during subsequent decision-making stages. Multi-objective evaluation requires establishing a set of rules that can compare and filter across N dimensions, for example, if vectors... and Belonging to different decision combinations, it can be determined in a Pareto sense if there is a dimension. Make And it does not have any dimensions. Make ,but Dominate Through this kind of judgment, multiple non-dominant caching strategies can be selected in the decision space, forming a Pareto front, reflecting a trade-off between system performance and energy consumption. For automotive-grade MCUs, if certain combinations are found to achieve a relative balance between the hit rate of local priority data and energy consumption during the final evaluation, they will be considered feasible strategies and directly applied to the cache management module in subsequent stages. In this way, under the guidance of the state-action value function, the optimal or near-optimal decision set can be encapsulated into a set of specific execution schemes, providing multiple feasible paths for data cache management in automotive environments.

[0028] 103. Based on the cache decision set, the cache space is divided into multiple logical partitions with different priorities, and the size of each logical partition is dynamically adjusted according to the real-time monitored cache performance indicators to obtain an adaptive partitioned cache space. In one embodiment of the present invention, the step of dividing the cache space into multiple logical partitions with different priorities based on the cache decision set, and dynamically adjusting the size of each logical partition according to the real-time monitored cache performance indicators to obtain an adaptive partition cache space includes: dividing the cache space into multiple logical partitions according to the decision priorities in the cache decision set, assigning an initial size and priority to each logical partition to form an initial partition state; monitoring the cache performance indicators of each logical partition in real time to obtain the current cache performance data, and combining the cache performance data and the initial partition state to construct the state input for reinforcement learning; feeding the state input into a preset reinforcement learning model, generating an action probability distribution through the policy network of the reinforcement learning model, and sampling the adjustment action of each logical partition size according to the action probability distribution; executing the adjustment action to update the size of each logical partition to obtain the adaptive partition cache space, and calculating the reward value after executing the adjustment action, wherein the reward value is obtained based on the degree of improvement in cache performance after adjustment, and the reward value is used to update the policy network of the reinforcement learning model.

[0029] Specifically, based on the decision priorities in the cache decision set, the cache space is divided into multiple logical partitions. An initial size and priority are allocated to each logical partition. The process of forming the initial partition state typically requires implementing dynamic partitioning functionality in the underlying storage management module or the memory allocator in the embedded operating system. In implementation, the priority information already marked in the cache decision set can be read first, and this priority information can be mapped to a multi-dimensional vector. Each logical partition occupies a coordinate dimension in this vector to record key information such as partition size limit, access permissions, and data residency policies. Subsequently, a continuous or non-contiguous address range is pre-allocated for each partition in the main storage space or on-chip SRAM / DRAM, and the starting address, maximum capacity, and priority level of this range are registered in the index table or partition table for subsequent dynamic adjustments. Meanwhile, the initial partition state can be constructed by assigning an identifier to each partition. Let its initial capacity be . The priority is taken from the priority score of the cache decision set. and maintain it in the record structure. The set of triples. The number of logical partitions often varies based on different application scenarios and data types. If certain critical data requires larger cache space or stricter access control, a higher value can be assigned to the priority field of that partition. To facilitate fast runtime retrieval, each partition is combined with one or more flag bits to indicate its data type or access permissions, thus enabling partitions to be associated with different access strategies at the address mapping level. The initial partition state is usually stored internally in a sparse mapping or segmented mapping manner and can be scheduled and queried through a lightweight kernel module to ensure low management overhead for resource-constrained automotive-grade MCUs. After this stage is completed, several logical partitions appear in the system, each with different initial capacities and priorities, forming a partition layout for various vehicle real-time tasks or data types. Real-time monitoring of the cache performance indicators of each logical partition to obtain the current cache performance data, and combining the cache performance data with the initial partition state to construct the state input for reinforcement learning can be accomplished by relying on hardware counters or customized monitoring components. A performance sampling interface can be configured in the cache controller or system bus protocol stack to acquire metrics such as the hit rate, average access latency, current resident data volume, and replacement count due to data overflow for each partition via periodic interrupts or event triggers. Energy-related statistics, such as the cumulative power consumption of partition read / write operations within a given time window, can also be collected when necessary. The monitoring component generates a state vector after collecting partition metrics. ,in Corresponding to the Each partition at time Observations such as the current hit rate or number of visits. Combined with the initial partition state, we can... Expand to The performance monitoring values ​​of each partition, along with initial priority and capacity information, constitute the input for reinforcement learning. In practice, the monitoring module packages these continuous or discrete performance metrics into a tensor or matrix that can be processed by the neural network or reinforcement learning algorithm. This tensor is then fed into the reinforcement learning agent during clock interrupts or frame period scheduling, enabling the agent to output more targeted decisions based on a thorough observation of the partition's dynamic changes. In this way, the real-time monitoring system synchronizes the reinforcement learning's state input with the cache operation status of the automotive-grade MCU, ensuring timely and accurate partition performance data even under sudden changes in the vehicle environment or a surge in task load.

[0030] The state input is fed into a preset reinforcement learning model. The model uses a policy network to generate an action probability distribution. Based on this distribution, actions to adjust the size of each logical partition are sampled. Before this, the state input needs to be vectorized or tensorized to adapt to the policy network's input format. A common approach is to construct a multilayer perceptron or a convolutional network to extract the correlation features between performance metrics and priorities of each partition. Then, depending on the algorithm type chosen in the reinforcement learning framework (e.g., PPO, DDPG, or A2C), forward propagation is performed on the input to obtain the network's evaluation value or corresponding probability distribution for each possible action. Here, the action space is often defined as the increase, decrease, or relative proportional adjustment of the size of each partition. For example, in discrete action settings, the size can be increased, decreased, or kept unchanged. If the system requires finer control, a continuous action space can be chosen, allowing the network to output the fluctuation amount of the partition size. Sampling within the probability distribution relies on the policy network's output; for example, the network can output a set of parameters for each partition size increment. and variance Then from Gaussian distribution Sampling is performed during the process, or action labels are selected from the probabilities after Softmax in discrete scenarios. The size adjustment actions of each logical partition obtained from the sampling will be formally executed in subsequent steps. This process is usually accompanied by a batch processing method, that is, multiple sets of states are collected in a time batch, then uniformly pushed into the policy network and multiple samplings are performed simultaneously, thereby reducing the latency caused by the execution frequency and improving the sample utilization rate of the overall reinforcement learning process. Executing the adjustment action updates the size of each logical partition, obtains the cache space of the adaptive partition, and calculates the reward value after the adjustment action. The reward value is obtained based on the degree of improvement in cache performance after the adjustment. The process of using the reward value to update the policy network of the reinforcement learning model depends on the system's feedback monitoring mechanism after the action takes effect. After the action is sampled, it is passed to the underlying partition management module, which modifies the size parameter of each partition to the new value in real time and updates it in the address mapping table or partition index table to ensure that subsequent data requests or writes can follow the new partition configuration. After the update is completed, it is necessary to re-collect performance indicators such as partition hit rate, latency, and energy consumption in the next monitoring cycle to form new performance data for comparison with the previous state and to calculate the reward value. .

[0031] If adjusting the action improves the hit rate and reduces latency and energy consumption, the reward value will be positive, encouraging such behavior in reinforcement learning; if adjusting the action leads to a performance degradation in some aspect, the reward value will be negative, inhibiting the related action in subsequent iterations. This reward value is then used to update the policy network parameters of the reinforcement learning model. Specifically, gradients are propagated back to the forward computation network via backpropagation, enabling the network to more accurately output partition size adjustment actions in the next state input. In an automotive-grade MCU operating environment, the above process can be integrated into a periodic or event-driven cache management flow, allowing the logical partition size to dynamically converge to a configuration suitable for automotive-grade requirements, maintaining flexibility even under complex operating conditions.

[0032] Furthermore, the step of dividing the cache space into multiple logical partitions according to the decision priorities in the cache decision set, allocating an initial size to each logical partition, and forming an initial partition state includes: calculating a priority score for each cache decision in the cache decision set to obtain a decision priority score set; performing cluster analysis on the cache decisions based on the decision priority score set to obtain the decision priority of each cache decision; determining the number and type of logical partitions based on the decision priorities, and dividing and allocating memory in the cache space according to the number and type of logical partitions to obtain multiple non-contiguous memory regions, forming logical partitions; assigning a unique identifier and access control attributes to each logical partition, establishing a partition index table, and generating an initial partition state by combining the initial size of the logical partitions and the partition index table.

[0033] Specifically, the process of calculating a priority score for each cache decision in the cache decision set to obtain a decision priority score set, and then performing cluster analysis on the cache decisions based on the decision priority score set to obtain the decision priority of each cache decision, typically relies on quantifying and comprehensively evaluating the important indicators of each decision in the automotive-grade MCU environment. In implementation, information such as data type, access frequency, real-time requirements, and data security level involved in each cache decision can be extracted first, and this information can be mapped into numerical feature vectors. For example, access frequency can be mapped to... Map security levels to Mapping real-time requirements to Then, a priority scoring function is defined based on the feature vectors, for example... ; in It is an adjustable coefficient used to balance the influence range of different indicators; The priority of data will change logarithmically with access frequency, ensuring that extremely high-frequency data is given higher priority. This is used to highlight data with high real-time requirements. After calculation, a set of data in the form of... The priority score set is used to further distinguish the aggregation relationships between decisions. Subsequent steps combine this set of scores with other additional attributes into a multi-dimensional vector, and then group the cache decisions using clustering analysis algorithms (such as k-means, DBSCAN, or hierarchical clustering). In implementation, the priority scores are first regularized to ensure they fall into a relatively consistent magnitude. Then, the features of all decisions are input into the clustering model, allowing the model to automatically divide the data into several classes, each corresponding to a certain priority range or a set of decisions with similar data features. If using K-means, the number of clusters k needs to be selected first, and then iterated continuously in Euclidean space to minimize the sum of squared errors within each cluster. If using DBSCAN, a density threshold can be used to adaptively find tightly distributed priority clusters. Regardless of the clustering algorithm used, the output will provide a priority label for each cache decision, or form a multi-level priority division in hierarchical clustering. Based on the clustering results, each cluster's label needs to be mapped to an executable priority number according to actual needs. For example, the highest priority decision cluster is mapped to "critical" or "P1", and ordinary priority decision clusters are mapped to "medium" or "P2", forming the final decision priority. After this process, a mapping table is generated for subsequent steps in logical partitioning and resource allocation. Based on the decision priorities, the number and type of logical partitions are determined, and the cache space is divided and memory allocated according to the number and type of logical partitions, resulting in multiple non-contiguous memory regions. The process of forming logical partitions requires flexible setting of partition boundaries at the memory management level or hardware abstraction layer. First, based on the priority labels obtained in the previous step, a corresponding number of logical partitions are allocated or reserved for different levels of decisions. If some high-priority categories contain a large amount of critical data, the number of partitions for that category is appropriately increased. Subsequently, segmentation operations need to be performed on the actual SRAM or DRAM address space. Several address blocks are retained through segmentation or page table remapping, allowing these address blocks to be non-contiguous but maintaining a unified identifier at the logical level. To accommodate data with varying priorities, the entire cache space can be divided into several large partitions, and each large partition can be further subdivided into sub-partitions. This allows high-priority data to be stored in an isolated or semi-isolated manner from medium- and low-priority data. During implementation, a segment description table can be constructed, containing the starting address of each partition. and end address Allocable capacity and priority field This will be recorded in the underlying mapping layer or page table management module, linking it with the addressing mechanism. If non-contiguous address regions are used for the special needs of automotive-grade MCUs, these address blocks need to be written into the partition management structure along with the partition identifier, and located through hashing or tree indexing. When the system initializes or the cache management module is reloaded, the partition management structure will be called to establish access policies and protection methods for each logical partition, ensuring that high-priority partitions can be scheduled first and maintain low latency when memory contention occurs. If the data types or access methods corresponding to some partitions are very special, multi-channel access policies can be considered, such as implementing differentiated priority scheduling for write and read operations at the hardware level, in order to improve overall access efficiency in combination with partition priority. After this process is completed, multiple non-overlapping or partially interleaved memory regions will appear, each region undertaking the task of residing data of different priorities, forming the basic layout of logical partitions; the process of assigning a unique identifier and access control attributes to each logical partition, establishing a partition index table, and generating the initial partition state by combining the initial size of the logical partition and the partition index table includes operations for partition identity management and permission management. In implementation, a partition index data structure can be created at the system level to map each logical partition to its unique identifier ID. The partition table records parameters such as the start and end addresses, size configuration, and priority level of each partition. Simultaneously, based on the access attributes of different data, read / write permissions, encryption levels, and DMA support attributes are added to the partitions to ensure the supervision of real-time control or safety data in automotive-grade scenarios. If access protection is required for a partition, access passwords, hardware sandbox settings, or interrupt priority register information can be added to the partition table, enabling high-priority partitions to receive a rapid response after an interrupt is triggered. This process often adopts a hierarchical design approach. For example, global partitions are identified in the root partition table, and then data types or access levels are further distinguished in sub-tables, using multi-level index jumps to locate the final physical address range. In some designs, clock statistics or access counts are introduced for partitions to support subsequent adaptive scaling decisions. After writing the initial size of each partition into the index table, an initial partition state can be obtained based on the global capacity and priority allocation strategy of the cache space, indicating the number of logical partitions currently existing in the system, the capacity of each partition, and its access attributes. To invoke this partition configuration in an interrupt service routine or driver layer, this index table can be loaded during the system boot phase, and the core partition can be locked to prevent interference from other processes. When the automotive-grade MCU starts running, the scheduler will assign corresponding CPU or storage bandwidth to each partition according to the initial partition state, so that data of different priorities have their own space protection and access permissions. Once the partition content or capacity needs to be dynamically adjusted, it can be updated based on this index table and memory remapping or cache replacement logic can be triggered.

[0034] 104. Based on the data access probability distribution and the cache space, set a dynamic prefetch threshold and perform data prefetching operations. At the same time, based on the task execution cycle, cached data is evicted to obtain optimized cached content.

[0035] In one embodiment of the present invention, the step of setting a dynamic prefetch threshold and performing a data prefetch operation based on the data access probability distribution and the cache space, while simultaneously evicting cached data within the task execution cycle to obtain optimized cached content includes: calculating the current cache utilization rate based on the data access probability distribution and the cache space, and dynamically calculating the prefetch trigger probability threshold based on the current cache utilization rate and the data access probability distribution; determining the data items that need to be prefetched based on the prefetch trigger probability threshold, and performing a prefetch operation on the data items that need to be prefetched to load the data items that need to be prefetched into the cache; for periodic tasks, recording the task execution cycle of each task and the data lifecycle of related data, and determining whether the data items in the cache have expired based on the task execution cycle and data lifecycle; and evicting the data items determined to be expired from the cache to obtain optimized cached content.

[0036] Specifically, the process of calculating the current cache utilization rate based on the data access probability distribution and the cache space, and dynamically calculating the prefetch trigger probability threshold based on the current cache utilization rate and the data access probability distribution, can be achieved by first collecting partition monitoring information and the access probability output by the model in the cache management module, and then accumulating the current occupancy of each partition to obtain the overall cache utilization rate. To obtain a more flexible threshold setting in the computing environment of automotive-grade MCUs, this utilization rate and the access probability distribution can be substituted into a function for solution, for example, letting... ; in This represents a logical function or the Sigmoid function. Indicates the current cache utilization rate. Indicates the first The predicted probability that a data item will be accessed. and It's about adjusting parameters. By adjusting... Setting appropriate upper and lower limit ranges can increase the trigger threshold in cache-intensive scenarios, avoiding excessive occupancy caused by blind prefetching, and can also appropriately relax the prefetch threshold when the cache is relatively idle. This calculation process can be implemented using hardware performance counters and a pre-trained probability prediction matrix. The occupancy information of each adaptive partition is packaged into a vector, and input along with the access probability distribution into the above formula for calculation, generating a trigger value that can be used for prefetching at the current moment. This trigger value is then applied during kernel interrupts or periodic task scheduling. The prefetch decision logic is then passed to the next stage. Based on the prefetch trigger probability threshold, the data items to be prefetched are determined, and a prefetch operation is performed on these items. Loading these data items into the cache requires first filtering data items with probability values ​​greater than θ from the distribution output by the access prediction model. This filtering can be done by sorting or traversing a "data-probability" mapping table, marking data items with access probabilities higher than θ as to be prefetched. Subsequently, the prefetch control module executes read requests for these data items according to the access permissions of the logical partition and the current capacity. If a hierarchical caching structure is used, it first determines whether the target data exists in low-speed storage or flash memory, then calls DMA or direct transfer mechanisms to load the target data block into the high-speed cache. If necessary, during the loading process, encrypted transmission or independent channel transmission can be performed for more critical data based on the priority field. To improve the efficiency of the prefetch operation, this operation needs to be performed during system interruptions or background task execution to prevent the main control flow of the automotive-grade MCU from being blocked by a large number of I / O operations. If a conflict is encountered during loading, the internal management module will invoke a replacement strategy to remove data with lower priority or lower hit rate, freeing up space for prefetched objects. This way, after loading is complete, the marked data items will be written to the designated partition or page table mapping area in real time, allowing subsequent access to this data to be completed directly from the cache, improving read speed and reducing bus usage.

[0037] For periodic tasks, recording the task execution cycle and related data lifecycle for each task, and determining whether cached data items have expired based on these task execution cycles and data lifecycles, requires constructing a "task-to-data-item" mapping table in the task manager or real-time operating system kernel layer of the automotive-grade MCU. This table must include the task's execution cycle and triggering method, as well as the effective lifespan or update frequency of the data block within a typical execution cycle. In practice, each task can register its usage cycle and expiration time for certain data at startup, thereby establishing a timer or event triggering mechanism in the cache monitoring module. When the partition access count or the current system clock exceeds the time threshold marked by the data lifecycle, the module will determine that the corresponding data item has expired. If some data is only valid within the task execution window, an expiration check will be triggered immediately once the task is completed or enters a dormant state. In some scenarios, if the periodic tasks are relatively fixed, the lifecycle of each data item can be defined in advance using a table-driven approach. When reading, simply comparing whether the "current time" and the "effective interval" overlap can quickly determine the data status. To more precisely identify expired items, you can combine access timestamps or modify flags to set them to "obsolete" after the expiration conditions are met, allowing for subsequent eviction or overwriting.

[0038] The process of evicting expired data items from the cache and obtaining optimized cached content is triggered immediately after the expiration identification process. Data items marked "obsolete" or invalid blocks are released from the partition, and the index table is updated. Specifically, the address mapping corresponding to the data item can be unregistered in the cache controller or page table management module first, and then the corresponding storage block can be marked as "reallocatable," allowing future prefetching or writing operations to utilize this space. If certain high-priority partitions need to remain relatively independent and not automatically overwrite each other, a secondary eviction logic within the partition can be adopted, moving expired data to a bypass area and completely overwriting it when new data is needed by the system. After eviction, the cache management module synchronously updates the cache utilization and effective hit rate metrics and completes the statistics of the new state when task scheduling or data access scenarios switch. The resulting cached content will better match the prediction model's preference for high-probability access items, providing more targeted cache support for subsequent real-time vehicle control and sensor data processing. Throughout the process, a lightweight event-driven framework can be used to trigger the prefetching and eviction process, and to minimize interference with real-time task scheduling during the identification and removal of expired data, thereby maintaining good system stability even in an environment where automotive-grade MCU resources are limited.

[0039] Furthermore, the step of calculating the current cache utilization rate based on the data access probability distribution and the cache space, and dynamically calculating the prefetch trigger probability threshold based on the current cache utilization rate and the data access probability distribution, includes: performing cache utilization statistics on each logical partition in the cache space of the adaptive partition to obtain a partition utilization rate set, and calculating the overall cache utilization rate based on the partition utilization rate set; performing cumulative probability calculation on the data access probability distribution to obtain a cumulative probability distribution curve, and determining an initial prefetch probability threshold on the cumulative probability distribution curve based on the overall cache utilization rate; and applying a dynamic adjustment function based on the initial prefetch probability threshold and the current system load to obtain the prefetch trigger probability threshold.

[0040] Specifically, the process of statistically analyzing the cache usage of each logical partition in the adaptive partition's cache space to obtain a partition usage rate set, and then calculating the overall cache usage rate based on this set, firstly requires maintaining a real-time or near real-time monitoring mechanism in the cache management module. This mechanism periodically samples the storage capacity of each logical partition, the number of currently loaded data blocks, and the available free space. This can be implemented using hardware performance counters or statistical interfaces in the underlying driver to collect information such as the number of read / write operations, data residency time, and used bytes for each partition into a partition status table. This monitoring mechanism will obtain the results at the end of a time slice. This is a set of partition usage rates. Next, we need to combine the usage rates of all partitions to calculate the overall cache utilization rate. Weighted averaging or simple averaging can be used. This approach can accurately reflect the true occupancy level of the entire cache space even when partition sizes are inconsistent. In embedded scenarios, to reduce the overhead of statistical cycles, the partition status table is generally updated only at fixed time intervals or on specific trigger events, while the count of write or replace operations is continuously accumulated in memory management or interrupt service routines. Overall cache utilization and partition usage set In subsequent steps, this will be used as input to drive decision-making, determining the system's current workload and remaining space margin, and assisting in subsequent prefetching judgments and eviction policy execution. After the statistics are completed, a timestamp and [other data] can be retained in the cache controller or log module. The mapping relationship is used for tracing and debugging during subsequent analysis. The process of calculating the cumulative probability of the data access probability distribution to obtain the cumulative probability distribution curve, and determining the initial prefetch probability threshold based on the overall cache utilization rate on the cumulative probability distribution curve, requires first obtaining the access probability vector of each data item from the access prediction module. ,in This represents the size of the potential data set that is of interest during the current time period. This vector can be sorted in ascending or descending order, and the probability values ​​can be accumulated in ascending order to obtain a monotonically increasing cumulative probability distribution curve. For example, after sorting in descending order, the following can be defined sequentially... This allows for the construction of stepped or continuous cumulative curves. In implementation, prefix sum operations can be performed on the inward curve within a microcontroller or edge processing chip. Alternatively, additional mathematical libraries can be used to plot approximate function interpolations, resulting in smoother results. This is then combined with overall cache utilization. Establish an initial prefetch probability threshold on the cumulative curve. If a segmented mapping method is used, it can be... Map the value to the interval [0,1], and then find the probability point corresponding to U on the cumulative distribution curve. If the overall cache utilization is high, then The value will be relatively close to 1, and the threshold point on the curve will increase accordingly, thus making the initial prefetching threshold higher; conversely, if the cache idle time is large, then... At a lower level, this provides more opportunities for prefetching data items. In a multi-threaded or multi-tasking environment, this process can be integrated into a unified cache management schedule, allowing the controller to update the threshold immediately after sampling, and subsequently only need to adjust the cache based on the data being processed. Determining which data should be marked as priority prefetching objects involves applying a dynamic adjustment function based on the initial prefetch probability threshold and the current system load. This process requires comprehensive consideration of CPU utilization, task queue length, and potential high-priority real-time task scheduling windows within the prefetch control module or scheduler. If the system load is low, the initial threshold can be used... Fine-tune the threshold to expand the prefetch range; if the system load becomes heavy or there are upcoming high-priority tasks, the threshold needs to be increased to reduce additional I / O overhead. A feasible dynamic adjustment scheme is to use the existing threshold... The above applies a nonlinear function. For example, let... ; in This indicates the current system load metric (such as CPU utilization or ready queue length). As a baseline load line, and To adjust the parameters, The function approximates 1 for large positive values ​​and -1 for large negative values, thus providing a dynamically adjustable offset for the threshold. When the load increases sharply... The output approaches positive saturation. The value can be increased; when the load decreases, this function will... To the initial threshold Pull back. This process can be placed in a timer or interrupt callback, refreshed every few seconds or a task cycle, to adjust the threshold. It evolves dynamically with the system status. If there are multi-dimensional load measurement metrics, a weighted approach can be used to combine factors such as CPU utilization and memory bandwidth utilization. An internal linear function. After calculation, the prefetch trigger probability threshold is obtained. This will become a crucial basis for prefetching decisions. Once the probability of a certain data item in the new access probability distribution exceeds this threshold, the prefetching process will be initiated, thereby improving data reading speed and reducing sudden latency in real-time vehicle scenarios. The entire adjustment process can be implemented at the underlying level using table-driven interpolation or hardware acceleration instructions to maintain low computational overhead on resource-constrained automotive-grade MCUs while ensuring real-time scheduling response.

[0041] In this embodiment, a multi-objective caching decision is constructed by predicting the future data access probability distribution, balancing real-time performance and memory utilization. The cache is divided into logical partitions of different priorities, and the partition sizes are dynamically adjusted to form an adaptive cache layout. Combining the access probability distribution and partitioning strategy, a dynamic prefetch threshold is set and data prefetching is performed, while replacement and updates are conducted within the task execution cycle. This improves the caching efficiency and stability of automotive-grade MCUs in high-temperature and high-vibration environments, making it suitable for vehicle control systems with stringent safety and performance requirements.

[0042] The data cache optimization method for automotive-grade MCUs in this embodiment of the invention has been described above. The data cache optimization device for automotive-grade MCUs in this embodiment of the invention is described below. Please refer to [link to relevant documentation] for details on this data cache optimization device for automotive-grade MCUs. Figure 2 One embodiment of the data caching optimization device for automotive-grade MCUs in this invention includes: Access prediction module 201 is used to record and count data access operations in automotive-grade MCU system, and use a preset long short-term memory network to predict the data access operations to obtain the data access probability distribution within a future time window. The multi-objective optimization module 202 is used to construct and solve a multi-objective optimization problem based on the data access probability distribution to obtain a set of cache decisions; The partition adjustment module 203 is used to divide the cache space into multiple logical partitions with different priorities based on the cache decision set, and dynamically adjust the size of each logical partition according to the real-time monitored cache performance indicators to obtain an adaptive partition cache space. The prefetch eviction module 204 is used to set a dynamic prefetch threshold and perform data prefetching operations based on the data access probability distribution and the cache space, and at the same time evict cached data based on the task execution cycle to obtain optimized cached content.

[0043] In this embodiment of the invention, the data cache optimization device for automotive-grade MCUs operates the aforementioned data cache optimization method for automotive-grade MCUs. This device constructs a multi-objective cache decision by predicting future data access probability distributions, balancing real-time performance and memory utilization. By dividing the cache into logical partitions of different priorities and dynamically adjusting the partition sizes, an adaptive cache layout is formed. Combining the access probability distribution and partitioning strategy, a dynamic prefetch threshold is set and data prefetching is performed. Simultaneously, replacement and updates are performed within the task execution cycle, thereby improving the cache efficiency and stability of automotive-grade MCUs in high-temperature and high-vibration environments. This method is suitable for vehicle control systems with stringent safety and performance requirements.

[0044] above Figure 2The data caching optimization device for automotive-grade MCUs in this embodiment of the invention is described in detail from the perspective of modular functional entities. The data caching optimization device for automotive-grade MCUs in this embodiment of the invention is described in detail from the perspective of hardware processing.

[0045] Figure 3 This is a schematic diagram of a data cache optimization device for automotive-grade MCUs provided in an embodiment of the present invention. The data cache optimization device 300 for automotive-grade MCUs can vary significantly due to different configurations or performance characteristics. It may include one or more central processing units (CPUs) 310 (e.g., one or more processors) and a memory 320, and one or more storage media 330 (e.g., one or more mass storage devices) for storing application programs 333 or data 332. The memory 320 and storage media 330 can be temporary or persistent storage. The program stored in the storage media 330 may include one or more modules (not shown in the diagram), each module including a series of instruction operations on the data cache optimization device 300 for automotive-grade MCUs. Furthermore, the processor 310 may be configured to communicate with the storage media 330 and execute the series of instruction operations in the storage media 330 on the data cache optimization device 300 for automotive-grade MCUs to implement the steps of the aforementioned data cache optimization method for automotive-grade MCUs.

[0046] The automotive-grade MCU data cache optimization device 300 may also include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input / output interfaces 360, and / or one or more operating systems 331, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. Those skilled in the art will understand that... Figure 3 The illustrated data cache optimization device structure for automotive-grade MCUs does not constitute a limitation on the data cache optimization device for automotive-grade MCUs provided by this invention. It may include more or fewer components than illustrated, or combine certain components, or have different component arrangements.

[0047] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when the instructions are executed on a computer, cause the computer to perform the steps of the data caching optimization method for the automotive-grade MCU.

[0048] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system, device, or unit described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0049] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0050] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data caching optimization method for automotive-grade MCUs, characterized in that, The data caching optimization method for automotive-grade MCUs includes: Data access operations in the automotive-grade MCU system are recorded and statistically analyzed, and the data access operations are predicted using a preset long short-term memory network to obtain the data access probability distribution within a future time window. A multi-objective optimization problem is constructed and solved based on the data access probability distribution to obtain a set of cache decisions. For each cache decision in the cache decision set, a priority score is calculated to obtain a decision priority score set. Based on this set, cluster analysis is performed on the cache decisions to determine their respective priorities. Based on these priorities, the number and type of logical partitions are determined. The cache space is then divided and memory is allocated according to these priorities, resulting in multiple non-contiguous memory regions, forming multiple logical partitions with different priorities. Each logical partition is assigned a unique identifier and access control attributes, a partition index table is established, and an initial partition state is generated by combining the initial size of the logical partition with the partition index table. Real-time monitoring is also performed. The cache performance metrics of each logical partition are calculated to obtain the current cache performance data. This cache performance data is then combined with the initial partition state to construct the state input for reinforcement learning. The state input is fed into a preset reinforcement learning model. The model uses a policy network to generate an action probability distribution. Based on this distribution, adjustment actions for the size of each logical partition are sampled. These adjustment actions are executed to update the size of each logical partition, resulting in the cache space of the adaptive partition. The reward value after the adjustment action is calculated, whereby the reward value is based on the degree of improvement in cache performance after the adjustment and is used to update the policy network of the reinforcement learning model. Based on the data access probability distribution and the cache space, a dynamic prefetch threshold is set and a data prefetch operation is performed. At the same time, cached data is evicted within the task execution cycle to obtain optimized cached content.

2. The data caching optimization method for automotive-grade MCUs according to claim 1, characterized in that, The process of recording and statistically analyzing data access operations in the automotive-grade MCU system, and using a pre-defined long short-term memory network to predict these data access operations to obtain the data access probability distribution within a future time window, includes: Record the data access operations in the automotive-grade MCU system to obtain raw access data including access frequency, access order and data size; The original access data is segmented into time series to obtain multiple data segments with fixed lengths; The data fragments are input into a preset long short-term memory network to obtain the data access probability distribution of each data item within a future time window.

3. The data caching optimization method for automotive-grade MCUs according to claim 1, characterized in that, The process of constructing and solving a multi-objective optimization problem based on the data access probability distribution yields a set of cache decisions, including: Based on the data access probability distribution, calculate the expected access frequency and importance weight of each data item, and construct a multi-objective optimization problem based on the expected access frequency and importance weight. The multi-objective optimization problem is transformed into the state space and action space of a deep Q-network, where the state space contains the current cached content and the expected access frequency of data items, and the action space contains the caching decision for each data item. The transformed multi-objective optimization problem is solved iteratively using a pre-defined deep Q-network algorithm to obtain the state-action value function; Based on the state-action value function, different combinations of caching decisions are evaluated, and based on the evaluation results, a set of caching decisions that are balanced across multiple objectives is selected to form a caching decision set that is approximately Pareto optimal.

4. The data caching optimization method for automotive-grade MCUs according to claim 1, characterized in that, The process involves setting a dynamic prefetch threshold and performing a data prefetch operation based on the data access probability distribution and the cache space, while simultaneously evicting cached data within the task execution cycle to obtain optimized cached content, including: Based on the data access probability distribution and the cache space, calculate the current cache utilization rate, and based on the current cache utilization rate and the data access probability distribution, dynamically calculate the probability threshold for prefetching trigger; Based on the probability threshold of the prefetch trigger, determine the data items that need to be prefetched, perform a prefetch operation on the data items that need to be prefetched, and load the data items that need to be prefetched into the cache; For periodic tasks, the task execution cycle and data lifecycle of each task are recorded, and based on the task execution cycle and data lifecycle, it is determined whether the data items in the cache have expired. Data items deemed expired are evicted from the cache, resulting in optimized cached content.

5. The data caching optimization method for automotive-grade MCUs according to claim 4, characterized in that, The step of calculating the current cache utilization rate based on the data access probability distribution and the cache space, and dynamically calculating the probability threshold for prefetching triggering based on the current cache utilization rate and the data access probability distribution, includes: The cache usage statistics of each logical partition in the cache space of the adaptive partition are performed to obtain a set of partition usage rates, and the overall cache usage rate is calculated based on the set of partition usage rates. The cumulative probability is calculated on the data access probability distribution to obtain the cumulative probability distribution curve, and an initial prefetch probability threshold is determined on the cumulative probability distribution curve based on the overall cache utilization rate. Based on the initial prefetch probability threshold and the current system load, a dynamic adjustment function is applied to obtain the prefetch trigger probability threshold.

6. A data cache optimization device for automotive-grade MCUs, characterized in that, The data cache optimization device for the automotive-grade MCU includes: The access prediction module is used to record and count the data access operations in the automotive-grade MCU system, and use a preset long short-term memory network to predict the data access operations to obtain the data access probability distribution within the future time window. The multi-objective optimization module is used to construct and solve a multi-objective optimization problem based on the data access probability distribution, and obtain a set of cache decisions. The partitioning adjustment module is used to calculate a priority score for each cache decision in the cache decision set, obtain a decision priority score set, and perform cluster analysis on the cache decisions based on the decision priority score set to obtain the decision priority of each cache decision; based on the decision priority, determine the number and type of logical partitions, and divide and allocate memory according to the number and type of logical partitions to obtain multiple non-contiguous memory regions, forming multiple logical partitions with different priorities; assign a unique identifier and access control attributes to each logical partition, establish a partition index table, and generate an initial partition state by combining the initial size of the logical partition and the partition index table; The cache performance metrics of each logical partition are monitored in real time to obtain the current cache performance data. The cache performance data and the initial partition state are combined to construct the state input for reinforcement learning. The state input is fed into a preset reinforcement learning model. The policy network of the reinforcement learning model generates an action probability distribution. Based on the action probability distribution, the adjustment actions for the size of each logical partition are sampled. The adjustment actions are executed to update the size of each logical partition, thereby obtaining the cache space of the adaptive partition. The reward value after executing the adjustment action is calculated. The reward value is based on the degree of improvement in cache performance after the adjustment and is used to update the policy network of the reinforcement learning model. The prefetch eviction module is used to set a dynamic prefetch threshold and perform data prefetching operations based on the data access probability distribution and the cache space, and at the same time evict cached data based on the task execution cycle to obtain optimized cached content.

7. A data cache optimization device for automotive-grade MCUs, characterized in that, The data caching optimization device for the automotive-grade MCU includes: a memory and at least one processor, wherein the memory stores instructions; The at least one processor invokes the instructions in the memory to cause the data cache optimization device of the automotive-grade MCU to perform the steps of the data cache optimization method for the automotive-grade MCU as described in any one of claims 1-5.

8. A computer-readable storage medium storing instructions thereon, characterized in that, When the instruction is executed by the processor, it implements the steps of the data cache optimization method for automotive-grade MCUs as described in any one of claims 1-5.

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