A BMS master control board and data storage method

Abstract

The application discloses a BMS master control board, comprising a microcontroller; and a storage circuit unit comprising a first nonvolatile memory and a second nonvolatile memory; wherein the first nonvolatile memory and the second nonvolatile memory are respectively independently connected to the microcontroller, and the microcontroller and the first nonvolatile memory are respectively independently connected with a first crystal oscillator and a second crystal oscillator. The BMS master control board, by configuring an independent crystal oscillator in the first nonvolatile memory, realizes time continuity under power failure, guarantees that historical data have complete time marks, and can be compared with data in the first nonvolatile memory, so that the coherence between data is enhanced, the traceability of system operation data is further enhanced, and the data consistency and coherence between the first nonvolatile memory and the second nonvolatile memory are guaranteed after power recovery.

Description

Technical Field

[0001] This invention relates to the technical field of BMS (Browser Management System), and more particularly to a BMS main control board and data storage method. Background Technology

[0002] In recent years, with the rapid development of electric vehicles, energy storage power stations and distributed energy systems, battery management systems (BMS) are used. By monitoring parameters such as battery voltage, current and temperature in real time, and combining storage and communication functions, BMS enables balanced management of battery packs, health status assessment and interaction with the vehicle or host computer, thereby ensuring battery safety and lifespan.

[0003] Currently, common BMS architectures in engineering applications include centralized, distributed, and hierarchical architectures. Among them, centralized BMS is widely used in low-voltage or small-to-medium capacity battery pack scenarios due to its simple hardware structure and low cost. Its typical implementation is to integrate MCU, power management, data storage, and external communication interfaces on a single main control board. The MCU is responsible for data processing and control logic, flash memory is used to store operating data, and communication with external systems is achieved through CAN or 485 bus.

[0004] However, existing centralized BMS systems have shortcomings in terms of system reliability. Most BMS systems rely solely on the MCU's internal Flash or external EEPROM to store operating parameters. These memories have slow write speeds and limited erase / write lifespans. When the system loses power or experiences an abnormal power outage, critical operating parameters may not have had time to be written, easily leading to data loss and the system's inability to accurately recover its operating state. Therefore, improvements are needed to address the reliability deficiencies of existing centralized BMS systems. Summary of the Invention

[0005] In view of the problems existing in the current BMS main control board, the present invention is proposed.

[0006] Therefore, the purpose of this invention is to provide a BMS main control board, which aims to solve the technical problem that the system cannot accurately restore its operating state under abnormal conditions.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a microcontroller; and a storage circuit unit, including a first non-volatile memory and a second non-volatile memory; wherein the first non-volatile memory and the second non-volatile memory are independently connected to the microcontroller, and the microcontroller and the first non-volatile memory are independently connected to a first crystal oscillator and a second crystal oscillator; the first non-volatile memory has high-speed write and power-loss retention characteristics, and relies on the second crystal oscillator to form a clock reference; the second non-volatile memory is a large-capacity memory used for batch writing of historical running data, and calls the clock reference provided by the first non-volatile memory to generate timestamps during the writing process.

[0008] In a preferred embodiment of the BMS main control board of the present invention, the first non-volatile memory is a ferroelectric memory chip, the second non-volatile memory is a flash memory chip, and both are connected to the microcontroller via an SPI bus.

[0009] As a preferred embodiment of the BMS main control board of the present invention, the first crystal oscillator has an operating frequency of 16MHz and the second crystal oscillator has an operating frequency of 32.768kHz.

[0010] In a preferred embodiment of the BMS main control board of the present invention, the power supply port VBAK of the first non-volatile memory is connected to an auxiliary power supply, and the auxiliary power supply is connected in parallel with a capacitor C56.

[0011] As a preferred embodiment of the BMS main control board of the present invention, two second non-volatile memories are provided, and the clock port SCLK, data input port SI, and data output port SO of the two second non-volatile memories are all connected to the serial peripheral interface bus SPI of the microcontroller.

[0012] As a preferred embodiment of the BMS main control board of the present invention, the storage circuit unit further includes a voltage conversion circuit, wherein the input terminal VIN and VCC_CPU of the voltage conversion circuit are electrically connected, and one end of the output terminal VOUT forms an output terminal 3V3_CPU.

[0013] The input terminal VIN is connected in parallel with ground GND, and input filter capacitors C49 and C50 are connected in parallel with ground GND, and output filter capacitors C53 and C54 are connected in parallel with output terminal VOUT.

[0014] As a preferred embodiment of the BMS main control board of the present invention, the microcontroller is electrically connected to a status indication circuit, the status indication circuit including: a current limiting resistor R36 connected to the output pin of the microcontroller; and a light-emitting diode D14 connected in series with the current limiting resistor, the cathode of which is connected to ground GND_CPU.

[0015] As a data storage method according to the present invention, the method includes the following steps: periodically collecting battery voltage, current, and temperature parameters and caching them in the random access memory inside the microcontroller; when the operating state changes or a preset time interval is reached, writing the cached parameters into the storage area of ​​the first non-volatile memory, the first non-volatile memory having a built-in second crystal oscillator Y2 for generating a time reference to ensure parameter integrity and time continuity under power failure conditions; when the amount of cached historical data reaches a preset quantity or a preset time interval is reached, writing the historical data in batches into the storage area of ​​the second non-volatile memory, and calling the real-time clock reference provided by the first non-volatile memory, adding a timestamp and checksum to each record; when undervoltage or power failure occurs, immediately writing the key operating parameters and corresponding timestamps into the first non-volatile memory, and terminating new write operations to the second non-volatile memory; when the system is powered on or reset, prioritizing the reading of the operating parameters and time reference in the first non-volatile memory to restore the operating state of the battery management system, and locating the write position in the second non-volatile memory according to the pointer information stored in the first non-volatile memory, and continuing to read and write.

[0016] In a preferred embodiment of the data storage method of the present invention, the microcontroller independently activates the target second non-volatile memory by selecting the control pins of different chips. When the target second non-volatile memory is selected, the microcontroller performs data writing or reading operations through the serial peripheral interface bus. After the data operation is completed, the chip select control pin is set to the unselected state so that the microcontroller can switch to another chip for access.

[0017] As a preferred embodiment of the data storage method of the present invention, when the system is powered on or reset, the microcontroller first reads the write pointer information and corresponding timestamp stored in the first non-volatile memory, and locates the end position of the most recent batch write in the second non-volatile memory accordingly, so as to correct the writing order of subsequent data and thus ensure the continuity and consistency of historical data.

[0018] The beneficial effects of this invention are as follows: By configuring an independent crystal oscillator in the first non-volatile memory, time continuity is achieved under power failure conditions, ensuring that historical data has complete time stamps and can be compared with the data inside the first non-volatile memory, thereby enhancing the continuity between data and thus enhancing the traceability of system operation data. After power failure recovery, the data consistency and continuity between the first non-volatile memory and the second non-volatile memory are guaranteed, thereby significantly improving the reliability and robustness of the battery management system. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 The pin connection diagram of the microcontroller is shown;

[0021] Figure 2 The connection diagram of the first non-volatile memory and the crystal oscillator circuit is shown;

[0022] Figure 3 The pin connection diagram of the second non-volatile memory is shown;

[0023] Figure 4 The circuit diagram of the first crystal oscillator is shown;

[0024] Figure 5 The circuit diagram of the voltage conversion circuit is shown;

[0025] Figure 6 The circuit diagram of the status indicator circuit is shown;

[0026] Figure 7 A flowchart of the data storage method is shown. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0028] The terminology used in this invention is that which is currently widely used in the art in consideration of the function of the invention; however, these terms may vary according to the intent of those skilled in the art, precedent, or new technology in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of the invention. Therefore, the terms used in this specification should not be construed as simple names, but rather based on their meanings and the overall description of the invention.

[0029] Reference Figure 1-3 This embodiment provides a BMS main control board, including a microcontroller 100 and a storage circuit unit 200, including a first non-volatile memory 201 and a second non-volatile memory 202. The first non-volatile memory 201 and the second non-volatile memory 202 are independently connected to the microcontroller 100, and the microcontroller 100 and the first non-volatile memory 201 are independently connected to a first crystal oscillator Y1 and a second crystal oscillator Y2. The first non-volatile memory 201 has high-speed write and power-down retention characteristics, and relies on the second crystal oscillator Y2 to form a clock reference. The second non-volatile memory 202 is a large-capacity memory used for batch writing of historical running data, and calls the clock reference provided by the first non-volatile memory 201 to generate a timestamp during the writing process.

[0030] During use, the microcontroller 100 executes the core control logic, data acquisition and processing, and data storage control of the battery management system. Preferably, the microcontroller 100 is an S912XDP512J1MAL model, which integrates a RAM cache for temporarily storing operational data.

[0031] The storage circuit unit 200 includes a first non-volatile memory 201 and a second non-volatile memory 202, which are used independently to store key operating parameters and batch historical operating data, respectively. Specifically, the first non-volatile memory 201 uses an FRAM chip (e.g., FM31256-G), which internally incorporates a second crystal oscillator Y2 to provide a stable real-time clock reference.

[0032] The second non-volatile memory 202 preferably uses a high-capacity Flash memory chip (such as GD25Q128ESIG) to store a large number of historical voltage, current and temperature records.

[0033] The microcontroller 100 is independently connected to the first non-volatile memory 201 and the second non-volatile memory 202 via the SPI bus. The two do not share the bus, ensuring that the first non-volatile memory 201 can still be accessed independently in case of power failure or other abnormal conditions.

[0034] Preferably, the microcontroller 100 is also equipped with a first crystal oscillator Y1 to maintain the stable operation of its clock system.

[0035] During operation, the microcontroller 100 periodically caches real-time collected operating parameters (including battery voltage, current, temperature, etc.) into its internal RAM. When the operating state changes or a preset time condition is met, the operating parameters are written to the first non-volatile memory 201. Simultaneously, the microcontroller 100 periodically writes accumulated historical data in batches to the second non-volatile memory 202 and uses the real-time clock reference provided in the first non-volatile memory 201 to add a timestamp and checksum information to each written record. At this time, the timestamp and checksum information in the second non-volatile memory 202 are consistent with those in the corresponding first non-volatile memory 201, thus ensuring contextual coherence during recovery, reducing recovery time, and improving recovery speed.

[0036] This method enables the main control circuit unit and the storage circuit unit to work together, achieving data integrity protection in the event of power failure, rapid recovery of the operating status after power-on, and improving the temporal continuity and traceability of historical operating data.

[0037] Example 2, refer to Figure 1-6 This is the second embodiment of the present invention, which differs from the first embodiment in that: the first non-volatile memory 201 is a ferroelectric memory chip, and the second non-volatile memory 202 is a flash memory chip. Both are connected to the microcontroller 100 via the SPI bus. The first crystal oscillator Y1 operates at a frequency of 16MHz, and the second crystal oscillator Y2 operates at a frequency of 32.768kHz. The power supply port VBAK of the first non-volatile memory 201 is connected to an auxiliary power supply 203, and the auxiliary power supply 203 is connected in parallel with a capacitor C56. Two second non-volatile memories 202 are provided. The clock port SCLK, data input port SI, and data output port SO of the two second non-volatile memories 202 are all connected to the serial peripheral interface bus SPI of the microcontroller 100. The storage circuit unit 200 also includes a voltage conversion circuit 204. The input terminal VIN and VCC_CPU of the voltage conversion circuit 204 are electrically connected, and one end of the output terminal VOUT forms an output terminal 3V3_CPU.

[0038] Among them, input filter capacitors C49 and C50 are connected in parallel between the input terminal VIN and ground GND, and output filter capacitors C53 and C54 are connected in parallel between the output terminal VOUT and ground GND. The microcontroller 100 is electrically connected to a status indicator circuit 102, which includes: a current-limiting resistor R36 connected to the output pin of the microcontroller 100; and a light-emitting diode D14 connected in series with the current-limiting resistor, with its cathode connected to ground GND_CPU.

[0039] Compared to Embodiment 1, the first non-volatile memory 201 is preferably a ferroelectric RAM (FRAM) chip, such as the FM31256-G model. This chip not only has fast write and high erasure resistance, but also integrates a second crystal oscillator Y2 and an auxiliary power supply 203, which can independently provide a time base for continuous operation under power failure.

[0040] The second non-volatile memory 202 is preferably a high-capacity flash memory chip, such as the GD25Q128ESIG model, used for batch recording of historical data such as voltage, current, and temperature during BMS operation.

[0041] Both the FRAM and Flash memory chips mentioned above are connected to the microcontroller 100 via the SPI bus. To improve the system's anti-interference and reliability, each chip is equipped with an independent chip select signal line and connected to different pins of the microcontroller 100 to avoid communication resource conflicts and ensure independent read and write capabilities even under extreme conditions (such as power failure, reset, etc.).

[0042] With the above structural configuration, not only can the high-frequency writing and low power consumption advantages of FRAM be utilized to achieve rapid storage of critical data, but the large capacity characteristics of Flash chips can also be combined to store historical data for a long time. Under the unified control of the microcontroller, a data management architecture that is both fast-responding and has persistent storage capabilities can be constructed.

[0043] Meanwhile, the second non-volatile memory 202 adopts a dual-chip configuration, that is, it is equipped with two independent Flash memory chips, both of which can be GD25Q128ESIG.

[0044] The SCLK and SO pins of the two Flash chips are connected in parallel to the SPI serial peripheral interface bus SPIBus of the microcontroller 100. To achieve inter-chip access isolation, the second non-volatile memory 202 is configured with independent chip select pins CS1 and CS2, which are respectively connected to different GPIO pins of the microcontroller 101 and used as chip select control signals.

[0045] In practical applications, the microcontroller 100 can activate only one Flash chip by controlling the high and low levels of the chip select signal, thereby enabling independent read and write access to any second non-volatile memory 202 and ensuring that bus conflicts or inter-chip interference are avoided in operations such as batch data storage, rotation management, or redundant writing.

[0046] This dual-chip structure not only increases the storage capacity of historical data, but also enables functions such as data backup, misaligned writing, and fault redundancy, significantly enhancing the reliability and maintainability of the main control system in critical application scenarios.

[0047] The storage circuit unit 200 is also provided with a voltage conversion circuit 204, which can convert the external power supply into a stable 3.3V CPU power supply for use by the CPU or related logic circuits.

[0048] Specifically, the voltage conversion circuit 204 is implemented using a low-dropout linear regulator (LDO) chip, such as the TPS76333DBV. The chip's input terminal VIN receives an externally supplied 5V power supply voltage, which, after conversion by the internal voltage regulator module, provides a stable 3.3V power supply voltage at the output terminal VOUT, ensuring reliable power supply to external circuits.

[0049] To ensure the stability of the voltage conversion process, input filter capacitors C49 and C50 are placed between VIN and ground (GND) to suppress input power supply ripple and transient interference, thereby improving the input power quality of the regulator. Correspondingly, output filter capacitors C53 and C54 are connected in parallel between VOUT and ground (GND) to improve the regulator's transient response performance and output voltage stability, ensuring a stable 3.3V output voltage even during load fluctuations or memory switching.

[0050] The storage circuit unit 200 also includes a second crystal oscillator Y2, which provides a stable clock reference for the first non-volatile memory 201.

[0051] Specifically, the second crystal oscillator Y2 has its output terminals connected to ports X1 and X2 of the first non-volatile memory 201, respectively, to drive the real-time clock module RTC inside the memory. Preferably, the frequency of the crystal oscillator is 32.768kHz, which is suitable for the clock requirements of the low-power real-time clock module.

[0052] In this embodiment, the first non-volatile memory 201 is connected to the auxiliary power supply 203 to ensure that it continues to run after the main control board is powered off, providing a continuous time reference for system recovery.

[0053] With the above configuration, the second crystal oscillator Y2 not only ensures the clock accuracy of the FRAM, but also provides a unified and stable time source for the timestamp information attached to the second non-volatile memory 202, thereby realizing the time continuity and traceability of historical data.

[0054] The microcontroller 100 is electrically connected to a status indicator circuit 102. The connection can be direct, via an adapter chip, or through a pin array. This circuit is used to visually display the operating status of the main control board. The status indicator circuit 102 includes: a current-limiting resistor R36, one end of which is connected to a GPIO output pin of the microcontroller 100; and a light-emitting diode D14, with its anode connected to the other end of the current-limiting resistor R36 and its cathode grounded to GND_CPU. This circuit forms a typical LED indicator path. When the microcontroller 100 output pin outputs a high level (e.g., 3.3V or 5V), current flows from the MCU output pin to GND_CPU, passing through the current-limiting resistor R36 and the light-emitting diode D14, thereby driving D14 to emit light. Simultaneously, the unidirectional conductivity of diode D14 prevents reverse current and protects the circuit.

[0055] The resistance value of the current-limiting resistor R36 is selected based on the LED current specification and operating voltage. It can be either 330Ω or 470Ω and is used to limit the forward current of the LED within the safe operating range to prevent overcurrent damage.

[0056] With the above structural setup, the BMS main control board can control the D14 to emit light according to the operating status (such as successful startup, fault alarm, communication activity, etc.) by the microcontroller, realizing an intuitive status indication function, which makes it easier for users to identify the system status on site and improves the convenience of operation and maintenance.

[0057] The remaining structure is the same as that in Example 1.

[0058] Example 3, referring to Figure 7 This is the third embodiment of the present invention, which differs from the second embodiment in that it provides a data storage method for the main control board of a battery management system, including the following steps:

[0059] Battery voltage, current and temperature parameters are periodically collected and cached in the random access memory inside the microcontroller 101;

[0060] When the operating state changes or a preset time interval is reached, the cached parameters are written into the storage area of ​​the first non-volatile memory 201. The first non-volatile memory 201 has a built-in second crystal oscillator Y2 for generating a time base to ensure the integrity of parameters and the continuity of time under power failure.

[0061] The microcontroller 100 independently activates the second non-volatile memory 202 by selecting the control pins of different chips. When the second non-volatile memory 202 is selected, the data writing or reading operation is completed through the serial peripheral interface bus. After the data operation is completed, the microcontroller (100) is switched to another chip as needed for access.

[0062] When the amount of cached historical data reaches a preset quantity or a preset time interval, the historical data is written in batches to the storage area of ​​the second non-volatile memory 202, and the real-time clock reference provided by the first non-volatile memory 201 is called to add a timestamp and check code to each record.

[0063] When undervoltage or power failure occurs, the key operating parameters and corresponding timestamps are immediately written to the first non-volatile memory 201, and the new writing operation to the second non-volatile memory 202 is terminated.

[0064] When the system is powered on or reset, the operating parameters and time base in the first non-volatile memory 201 are read first to restore the operating state of the battery management system. Based on the pointer information stored in the first non-volatile memory 201, the microcontroller 100 locates the write position in the second non-volatile memory 202. Specifically, when the system is powered on or reset, the microcontroller 100 first reads the write pointer information and corresponding timestamp stored in the first non-volatile memory 201, and locates the end position of the most recent batch write in the second non-volatile memory 202 accordingly to correct the writing order of subsequent data, thereby ensuring the continuity and consistency of historical data, and then continues to read and write.

[0065] Compared to Embodiment 2, furthermore, the operating parameters are periodically collected and temporarily stored in the random access memory (RAM) inside the microcontroller 100 to form a cache. This cache is used to temporarily store data, avoiding frequent direct writes to non-volatile memory and improving storage efficiency.

[0066] When a change in operating status is detected, or a preset sampling time interval is reached, the microcontroller writes the cached data into the storage area of ​​the first non-volatile memory 201. The first non-volatile memory 201 is a ferroelectric RAM (FRAM) chip, which integrates an independent second crystal oscillator Y2 with an operating frequency of 32.768kHz. This crystal oscillator provides a reference for the chip's real-time clock, ensuring that time counting continues even when the system loses power, thereby guaranteeing that the written parameters are not only complete but also maintain time continuity.

[0067] When the cached historical data reaches a preset quantity or exceeds a preset time interval, the microcontroller writes the data in batches to the storage area of ​​the second non-volatile memory 202. The second non-volatile memory 202 is a large-capacity flash memory chip, and its write speed is lower than that of the first non-volatile memory 201, making it more suitable for batch storage. When performing batch writing, the microcontroller 100 obtains a real-time clock reference from the first non-volatile memory 201 and adds a timestamp and checksum to each historical data record to enable subsequent time tracking and data verification.

[0068] When the battery management system experiences undervoltage or power failure, the external power monitoring circuit sends a power failure signal to the microcontroller 100. The microcontroller 100 immediately writes the key operating parameters (such as battery state of charge (SOC), state of health (SOH), and fault flags) and their corresponding timestamps from the current cache into the first non-volatile memory 201. At the same time, it aborts the write operation to the second non-volatile memory 202 to prevent the flash memory data from being corrupted due to power failure.

[0069] Since the second non-volatile memory 202 consists of two independent flash memory chips, in order to achieve independent access, the SPI interface of the microcontroller 100 connects the SCLK, MOSI, and MISO buses of the two flash memory chips in parallel, while the chip select terminal (CS#) of each flash memory chip is connected to an independent control pin of the microcontroller chip.

[0070] During operation, the microcontroller 100 activates the flash memory chip by pulling its chip select pin low. Once the target flash memory chip is selected, data is transmitted via the SPI bus, allowing the microcontroller 100 to complete read and write operations on the target chip. After the operation is complete, the microcontroller 100 releases (pulls up) the chip select pin, deselecting the chip. In this way, the microcontroller can flexibly switch between different flash memory chips, independently addressing and accessing them.

[0071] When the system is powered on or reset, the microcontroller prioritizes reading the operating parameters and time reference stored in the first non-volatile memory 201 to quickly restore the operating state of the battery management system, and calibrates the write position of the second non-volatile memory 202 according to the pointer information stored in the first non-volatile memory 201 to realize continuous data appending.

[0072] Specifically, the microcontroller 100 first reads the stored write pointer information and corresponding timestamp from the first non-volatile memory 201. This write pointer information is synchronously updated to the first non-volatile memory 201 during normal batch writing to the second non-volatile memory 202, and is used to mark the last write position of data in the second non-volatile memory 202.

[0073] After power-on, the microcontroller uses the pointer information to directly locate the end position of the most recent batch write in the second non-volatile memory 202, and compares it with the timestamp to ensure that the data is logically sequential.

[0074] In this way, when new historical data needs to be written, it can be appended to the correct location, avoiding data misalignment or overwriting issues caused by power outages.

[0075] The remaining structure is the same as that in Example 2.

[0076] It is important to note that the constructions and arrangements of this application shown in several different exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, those who consult this disclosure will readily understand that many modifications are possible (e.g., changes in the size, dimensions, structure, shape, and proportions of various elements, as well as parameter values ​​(e.g., temperature, pressure, etc.), installation arrangements, use of materials, color, orientation, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in this application). For example, an element shown as integrally formed may be composed of multiple parts or elements, the position of elements may be inverted or otherwise altered, and the nature or number or position of discrete elements may be changed or altered. Therefore, all such modifications are intended to be included within the scope of the invention. The order or sequence of any process or method steps may be changed or rearranged according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure described herein that performs the function, and not only structural equivalents but also equivalent structures. Other substitutions, modifications, alterations, and omissions may be made in the design, operation, and arrangement of the exemplary embodiments without departing from the scope of the invention. Therefore, the present invention is not limited to the specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.

[0077] Furthermore, in order to provide a concise description of exemplary embodiments, not all features of actual embodiments (i.e., those features that are not relevant to the best mode of carrying out the invention as currently considered, or those features that are not relevant to implementing the invention) may be omitted.

[0078] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A BMS main control board, characterized in that: Including a microcontroller (100); and, The storage circuit unit (200) includes a first non-volatile memory (201) and a second non-volatile memory (202). The first non-volatile memory (201) and the second non-volatile memory (202) are independently connected to the microcontroller (100), and the microcontroller (100) and the first non-volatile memory (201) are independently connected to the first crystal oscillator (Y1) and the second crystal oscillator (Y2). The first non-volatile memory (201) has high-speed writing and power-down retention characteristics, and relies on the second crystal oscillator (Y2) to form a clock reference. The second non-volatile memory (202) is a large-capacity memory used for batch writing of historical running data, and calls the clock reference provided by the first non-volatile memory (201) to generate timestamps during the writing process. The second non-volatile memory (202) is provided in two pieces, and the clock port SCLK, data input port SI and data output port SO of the two pieces of the second non-volatile memory (202) are all connected to the serial peripheral interface bus SPI of the microcontroller (100). The storage circuit unit (200) also includes a voltage conversion circuit (204), the input terminal VIN and VCC_CPU of the voltage conversion circuit (204) are electrically connected, and one end of the output terminal VOUT forms an output terminal 3V3_CPU; The input terminal VIN is connected in parallel with ground GND, and input filter capacitors C49 and C50 are connected in parallel with ground GND, and output filter capacitors C53 and C54 are connected in parallel with output terminal VOUT.

2. The BMS main control board according to claim 1, characterized in that: The first non-volatile memory (201) is a ferroelectric memory chip, and the second non-volatile memory (202) is a flash memory chip. Both are connected to the microcontroller (100) via the SPI bus.

3. The BMS main control board according to claim 2, characterized in that: The first crystal oscillator (Y1) operates at a frequency of 16MHz, and the second crystal oscillator (Y2) operates at a frequency of 32.768kHz.

4. The BMS main control board according to any one of claims 1 to 3, characterized in that: The power supply port VBAK of the first non-volatile memory (201) is connected to an auxiliary power supply (203), and the auxiliary power supply (203) is connected in parallel with a capacitor C56.

5. The BMS main control board according to any one of claims 1 to 3, characterized in that: The microcontroller (100) is electrically connected to a status indicator circuit (102), which includes: a current-limiting resistor R36 connected to the output pin of the microcontroller (100); and a light-emitting diode D14 connected in series with the current-limiting resistor, the cathode of which is connected to ground GND_CPU.

6. A data storage method, employing a BMS main control board as described in any one of claims 1-5, characterized in that: Includes the following steps: Battery voltage, current and temperature parameters are periodically collected and cached in the random access memory inside the microcontroller (100); When the operating state changes or the preset time interval is reached, the cached parameters are written into the storage area of ​​the first non-volatile memory (201). The first non-volatile memory (201) has a built-in second crystal oscillator Y2 to generate a time base to ensure the integrity of parameters and the continuity of time under power failure. When the amount of cached historical data reaches a preset quantity or a preset time interval, the historical data is written in batches to the storage area of ​​the second non-volatile memory (202), and the real-time clock reference provided by the first non-volatile memory (201) is called to add a timestamp and check code to each record. When undervoltage or power failure occurs, the key operating parameters and corresponding timestamps are immediately written to the first non-volatile memory (201), and the new writing operation to the second non-volatile memory (202) is terminated. When the system is powered on or reset, the operating parameters and time base in the first non-volatile memory (201) are read first to restore the operating state of the battery management system, and the pointer information stored in the first non-volatile memory (201) is used to locate the write position of the second non-volatile memory (202) and continue to read and write. When the system is powered on or reset, the microcontroller (100) first reads the write pointer information and corresponding timestamp stored in the first non-volatile memory (201), and then locates the end position of the most recent batch write in the second non-volatile memory (202) to correct the writing order of subsequent data, thereby ensuring the continuity and consistency of historical data.

7. The data storage method according to claim 6, characterized in that: The microcontroller (100) independently activates the target second non-volatile memory (202) by selecting the control pins of different chips respectively. When the target second non-volatile memory (202) is selected, the microcontroller completes the data writing or reading operation through the serial peripheral interface bus. After the data operation is completed, the microcontroller (100) is switched to another chip for access as needed.

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