A multi-chip interconnection system and its decoding method
By employing a ring interconnect structure and address resolution recovery module in a multi-chip system, the problems of large chip interconnect interface area and complex decoding are solved, achieving chip area reduction and decoding efficiency improvement, and supporting optimal access paths for any number of chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN C CORE TECH CO LTD
- Filing Date
- 2025-12-08
- Publication Date
- 2026-06-30
Smart Images
Figure CN121277876B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of multi-chip systems, and in particular relates to a multi-chip interconnection system and its decoding method. Background Technology
[0002] In multi-chip collaborative scenarios, a method is needed to connect the various chips. Existing multi-chip collaborative scenarios require multiple interconnect interfaces, occupying a large chip area, and the decoding method is relatively complex. To reduce chip area, a chip may contain only two interconnect interfaces. Simultaneously, an address allocation and decoding method is needed to determine the data location, and the decoding logic needs to be as simple as possible to reduce chip area. Summary of the Invention
[0003] In view of this, the present invention aims to propose a multi-chip interconnect system and its decoding method to solve the problems of low address allocation and decoding efficiency in the prior art.
[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:
[0005] In a first aspect, the present invention provides a multi-chip interconnection system, comprising a plurality of chips, wherein each chip includes a processor, an address resolution module, a bus matrix, an address recovery module, an interface A and an interface B; both interface A and interface B include a slave interface and a master interface;
[0006] The processor is connected to the bus matrix through the address resolution module. The slave interfaces of interface A and interface B are both connected to the bus matrix through the address recovery module. The master interfaces of interface A and interface B are both connected to the bus matrix through the address resolution module.
[0007] Interface A is located at the beginning of the chip, and interface B is located at the end of the chip. Several chips are connected end to end to form a ring interconnection structure.
[0008] Furthermore, the number of chips in the ring interconnect structure is There are 100 chips, where n is the number of binary bits used for the chip number, ranging from 0 to 100. .
[0009] Furthermore, the system's addressing range is divided into global addresses and local addresses, with the global addresses using a unified multi-chip addressing method.
[0010] Furthermore, the n binary bits of the chip number occupy the high bits of the global address.
[0011] Secondly, based on the same concept, the present invention also provides a decoding method for a multi-chip interconnect system, comprising the following steps:
[0012] S1, The host sends a request;
[0013] S2. Based on the chip number, the address resolution module resolves the global address into a local address;
[0014] S3. Based on the local address, the bus matrix sends the request to the corresponding slave device;
[0015] S4. Based on the chip number, the address recovery module restores the local address to the global address;
[0016] S5. Interface A or Interface B will send the request to the adjacent chip.
[0017] In step S3, based on the local address, the bus matrix sends a request to the corresponding slave device, including:
[0018] If the high-order bits of the local address are 0, the request is sent to the local module;
[0019] In a ring interconnect structure, when the direction from interface A of one chip to interface B of another chip is consistent with the direction of sequentially incrementing the chip number, if the high-order bits of the local address are greater than or equal to 1 and less than or equal to 1, then... If the local address's high-order bits are greater than or equal to the specified bits, then the request is sent to interface A; and less than or equal to If so, the request is sent to interface B;
[0020] When the direction from interface B of one chip to interface A of another chip is consistent with the direction of sequentially incrementing the chip number, if the high-order bits of the local address are greater than or equal to 1 and less than or equal to 1, then... If the local address is greater than or equal to the specified value, then the request is sent to interface B; and less than or equal to If so, the request is sent to interface A.
[0021] Furthermore, in step S2, based on the chip number, the address resolution module resolves the global address into a local address, as shown in the following expression:
[0022] LocalAddrHB = GlobalAddrHB - ChipID;
[0023] LocalAddrLB = GlobalAddrLB;
[0024] In the formula, LocalAddrHB is the high-order byte of the local address, GlobalAddrHB is the high-order byte of the global address, ChipID is the chip number, LocalAddrLB is the low-order byte of the local address, and GlobalAddrLB is the low-order byte of the global address.
[0025] Furthermore, in step S4, based on the chip number, the address recovery module restores the local address to the global address, as shown in the following expression:
[0026] GlobalAddrHB = LocalAddrHB + ChipID;
[0027] GlobalAddrLB = LocalAddrLB;
[0028] In the formula, LocalAddrHB is the high-order byte of the local address, GlobalAddrHB is the high-order byte of the global address, ChipID is the chip number, LocalAddrLB is the low-order byte of the local address, and GlobalAddrLB is the low-order byte of the global address.
[0029] Compared with existing technologies, the multi-chip interconnection system and its decoding method described in this invention have the following advantages:
[0030] This invention provides a multi-chip interconnection method and an address allocation and decoding method. Regardless of the number of chips interconnected, only two interconnection interfaces are required on each chip, reducing chip area. Only an address resolution module needs to be added to the host accessing off-chip resources, the host of interface A, and the host of interface B, and an address recovery module needs to be added to the slave of interface A and the slave of interface B. This completes the global address decoding logic. The added modules only contain adders, resulting in simple logic, small area, and the ability to obtain the optimal access path. Attached Figure Description
[0031] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:
[0032] Figure 1 This is a schematic diagram of the chip interface according to an embodiment of the present invention;
[0033] Figure 2 This is a schematic diagram of the chip interconnect structure described in an embodiment of the present invention;
[0034] Figure 3 This is a schematic diagram of the internal module connection according to an embodiment of the present invention;
[0035] Figure 4 This is a schematic diagram of the decoding process described in an embodiment of the present invention. Detailed Implementation
[0036] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0037] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0038] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0039] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0040] like Figure 1 As shown, the chip contains two interconnect interfaces: Interface A and Interface B. Each interface can connect to different chips. For 4-chip interconnection, the following can be used: Figure 2 The ring interconnect structure shown has chip interface A connected to another chip interface B.
[0041] Addresses are divided into global addresses and local addresses. The global addressing method uses a unified addressing across multiple chips, distinguishing which chip it belongs to based on the high-order bits of the address. The local address uses the same encoding method for each chip: a high-order bit of 0 indicates a local module, while a high-order bit of non-zero indicates an external address, which is decoded by the bus to interface A or B.
[0042] Internal module connections such as Figure 3As shown. Interfaces A and B each include a slave interface and a master interface. The processor is connected to the bus matrix through an address resolution module. The slave interfaces of both interfaces A and B are connected to the bus matrix through address recovery modules. The master interfaces of both interfaces A and B are connected to the bus matrix through address resolution modules. Interface A is located at the beginning of the chip, and interface B is located at the end of the chip. Several chips are connected end-to-end to form a ring interconnection structure. The processor is a CPU, NPU, etc., and interfaces A and B are arbitrary inter-chip interconnection interfaces. The bus matrix is arbitrary. Inside the chip, address resolution and address recovery modules are added to process the global address. All bus hosts (interface A, interface B, processor, etc.) within the chip that need to access the addresses of other chips must have their addresses resolved into local addresses by the address resolution module before being sent to the bus matrix. The slave interfaces of interfaces A and B need to be connected to the address recovery module to restore the local address before sending it to the slave interface.
[0043] Assume the number of interconnected chips is The chip number range is The specific decoding process is as follows: Figure 4 As shown in the diagram, when a host sends a request, the address resolution module resolves the global address to a local address based on the chip number. Then, the bus matrix sends the request to the corresponding slave device based on the resolved local address. If the high-order bits of the local address are 0, the request is sent to the local module by the bus.
[0044] like Figure 2 As shown, when the direction from chip interface A to another chip interface B is consistent with the direction of sequentially incrementing the chip number, if the high-order bits of the local address are greater than or equal to 1 and less than or equal to 1, then... If so, the request is sent to interface A; Figure 4 As shown, if the high-order bits of the local address are greater than or equal to and less than or equal to If so, the request is sent to interface B.
[0045] Furthermore, when the direction from chip interface B to another chip interface A is consistent with the direction of sequentially incrementing the chip number, if the high-order bits of the local address are greater than or equal to 1 and less than or equal to 1, If the local address is greater than or equal to the specified value, then the request is sent to interface B; and less than or equal to If so, the request is sent to interface A.
[0046] The address recovery module restores the local address to the global address based on the chip number and sends it to interface A / B. Then, interface A / B sends the request to the adjacent chip.
[0047] The address resolution module will perform the following operation on the global address to resolve it into a local address, where the high-order bits of the local address, the high-order bits of the global address, and the chip number are all n bits wide.
[0048] Local address high byte = Global address high byte - Chip number;
[0049] Local address low byte = Global address low byte;
[0050] The address recovery module will perform the following operation on the local address to restore it to the global address, where the high-order bits of the local address, the high-order bits of the global address, and the chip number bit width are all n.
[0051] Global address high byte = Local address high byte + Chip number;
[0052] Global address low byte = Local address low byte;
[0053] After using the address resolution and recovery module and bus decoding logic described above, accessing any chip can be done at most once. External interface delay of the chip.
[0054] Taking the interconnection of four chips as an example, assume that in the global address space, chip 0's address is 0x0000~0x0FFF, chip 1's address is 0x1000~0x1FFF, chip 2's address is 0x2000~0x2FFF, and chip 3's address is 0x3000~0x3FFF. In each chip's local address space, 0x0000~0x0FFF represents the local module, and 0x1000~0x3FFF represents the external address. The bus matrix decodes 0x0000~0x0FFF to each slave interface inside the chip (excluding interface A and interface B), decodes 0x1000~0x1FFF to interface A, and decodes 0x2000~0x3FFF to interface B.
[0055] The address resolution module calculates the address sent to the bus matrix:
[0056] Bus matrix address [13:12] = Main interface transmit address [13:12] - Chip number [1:0];
[0057] The address recovery module calculates the address sent to the slave interface:
[0058] The interface receive address [13:12] = bus matrix address [13:12] + chip number [1:0];
[0059] When four chips are interconnected, the chip numbers are 0, 1, 2, and 3.
[0060] The following example uses chip 2 to demonstrate how to access each address.
[0061] When the main interface of chip 2 accesses the local address, it sends an address from 0x2000 to 0x2FFF. After passing through the address resolution module, the address sent to the bus matrix is 0x0000 to 0x0FFF, which will be decoded by the bus matrix and sent to the local address.
[0062] When the main interface of chip 2 accesses external addresses 0x0000~0x1FFF, after passing through the address resolution module, the address sent to the bus matrix is 0x2000~0x3FFF. This address is then decoded by the bus matrix and sent to interface B. The address recovery module then restores the address to 0x0000~0x1FFF before sending it to interface A of chip 1. Addresses 0x1000~0x1FFF sent from interface A of chip 1, after passing through the address resolution module, are sent to the bus matrix as 0x0000~0x0FFF, and are then decoded by the bus matrix and sent locally. Addresses 0x0000~0x0FFF sent from interface A of chip 1, after passing through the address resolution module, are sent to the bus matrix as 0x3000~0x3FFF. This address is then decoded by the bus matrix and sent to interface B. The address recovery module then restores the address to 0x0000~0x0FFF before sending it to interface A of chip 0. The addresses 0x0000~0x0FFF sent by interface A in chip 0 are still 0x0000~0x0FFF after passing through the address resolution module and are then decoded by the bus matrix to local address.
[0063] When the main interface of chip 2 accesses external addresses 0x3000~0x3FFF, after passing through the address resolution module, the address sent to the bus matrix is 0x1000~0x1FFF. This address is then decoded by the bus matrix and sent to interface A. The address recovery module then restores the address to 0x3000~0x3FFF before sending it to interface B of chip 3. The address 0x3000~0x3FFF sent by interface B of chip 3, after passing through the address resolution module, is sent to the bus matrix as 0x0000~0x0FFF, where it is decoded by the bus matrix and sent locally.
[0064] For each chip, using this address decoding method, accessing any chip involves a maximum of two levels of external interface latency. This means the access request only needs to pass through two external interfaces to reach the destination chip, representing the optimal access path. Table 1 shows the modules to which different addresses for each chip are decoded.
[0065] Table 1
[0066]
[0067] For an 8-chip ring interconnect configuration, the bus matrix decodes the address with the high-order bits of 0 to the local address, decodes the address with the high-order bits of 1, 2, and 3 to interface A, and decodes the address with the high-order bits of 4, 5, 6, and 7 to interface B. In this configuration, accessing any chip involves a maximum of four levels of off-chip interface latency.
[0068] Advantages and benefits of this invention:
[0069] This invention provides a multi-chip interconnection method and an address allocation and decoding method. Regardless of the number of chips interconnected, only two interconnection interfaces are required on each chip, reducing chip area. Only an address resolution module needs to be added to the host accessing off-chip resources, the host of interface A, and the host of interface B, and an address recovery module needs to be added to the slave of interface A and the slave of interface B. This completes the global address decoding logic. The added modules only contain adders, resulting in simple logic, small area, and the ability to obtain the optimal access path.
[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A decoding method for a multi-chip interconnect system, applied to a multi-chip interconnect system, characterized in that: It includes several chips, each chip comprising a processor, an address resolution module, a bus matrix, an address recovery module, interface A, and interface B; interface A and interface B each include a slave interface and a master interface; The processor is connected to the bus matrix through the address resolution module. The slave interfaces of interface A and interface B are both connected to the bus matrix through the address recovery module. The master interfaces of interface A and interface B are both connected to the bus matrix through the address resolution module. Interface A is located at the beginning of the chip, and interface B is located at the end of the chip. Several chips are connected end to end to form a ring interconnection structure. The number of chips in the ring interconnect structure is: There are 100 chips, where n is the number of binary bits used for the chip number, ranging from 0 to 100. ; The system's addressing range is divided into global addresses and local addresses. The global addressing method is a unified addressing method for multiple chips. The n binary bits of the chip number occupy the high-order bits of the global address; The method includes the following steps: S1, The host sends a request; S2. Based on the chip number, the address resolution module resolves the global address into a local address; S3. Based on the local address, the bus matrix sends the request to the corresponding slave device; S4. Based on the chip number, the address recovery module restores the local address to the global address; S5. Interface A or Interface B will send the request to the adjacent chip. In step S3, based on the local address, the bus matrix sends a request to the corresponding slave device, including: If the high-order bits of the local address are 0, the request is sent to the local module; In a ring interconnect structure, when the direction from interface A of one chip to interface B of another chip is consistent with the direction of sequentially incrementing the chip number, if the high-order bits of the local address are greater than or equal to 1 and less than or equal to 1, then... If the local address's high-order bits are greater than or equal to the specified bits, then the request is sent to interface A; and less than or equal to If so, the request is sent to interface B; When the direction from interface B of one chip to interface A of another chip is consistent with the direction of sequentially incrementing the chip number, if the high-order bits of the local address are greater than or equal to 1 and less than or equal to 1, then... If the local address is greater than or equal to the specified value, then the request is sent to interface B; and less than or equal to If so, the request is sent to interface A; In step S2, based on the chip number, the address resolution module resolves the global address into a local address, where the high-order bits of the local address, the high-order bits of the global address, and the chip number are all n bits wide, as shown in the following expression: LocalAddrHB = GlobalAddrHB - ChipID; LocalAddrLB = GlobalAddrLB; In the formula, LocalAddrHB is the high-order byte of the local address, GlobalAddrHB is the high-order byte of the global address, ChipID is the chip number, LocalAddrLB is the low-order byte of the local address, and GlobalAddrLB is the low-order byte of the global address; In step S4, based on the chip number, the address recovery module restores the local address to the global address, as shown in the following expression: GlobalAddrHB = LocalAddrHB + ChipID; GlobalAddrLB = LocalAddrLB.