Memory chip repair method and device, host computer and storage medium

Abstract

The application belongs to the technical field of chip testing, and relates to a memory chip repairing method and device, an upper computer and a storage medium. Defect repairing information of repairable tested chips in each group of tested chips is acquired. Based on the defect repairing information, repairing data corresponding to the repairable tested chips in each group of tested chips is generated, and the repairing data is written into an address mapping memory of a test function board card corresponding to the repairable tested chips. A control signal is sent to each group of tested chips, so that the repairable tested chips in each group of tested chips acquire chip identification numbers corresponding to the repairable tested chips according to the control signal. The repairable tested chips in each group of tested chips are repaired according to the chip identification numbers and the repairing data. Based on this, the repairing data is divided into corresponding address mapping memories according to test function board cards, a parallel repairing mechanism between test function board cards and a serial repairing mechanism in test function board cards are constructed, and the repairing efficiency of the chips is greatly improved.

Description

Technical Field

[0001] This application belongs to the field of chip testing technology, specifically relating to a method, apparatus, host computer, and storage medium for repairing memory chips. Background Technology

[0002] In the current field of integrated circuit manufacturing, as chip integration density continues to increase, the probability of local defects appearing in the internal memory cells of chips during manufacturing also rises. To improve yield, chips must undergo functional testing by automated test equipment (ATE) after manufacturing to screen out defective chips. For chips with repairable defects, ATE typically works in conjunction with the chip's own spare cells to repair the defective chips after testing.

[0003] However, existing chip repair processes often involve complex testing and address management mechanisms. Especially in large-scale chip testing environments, the processing efficiency of repair operations faces challenges as the number of chips under test increases. Therefore, how to improve chip repair efficiency on ATE testing platforms has become an urgent problem to be solved in this field. Summary of the Invention

[0004] The embodiments of this application mainly address the technical problem of how to improve the repair efficiency of chips in a large-scale chip testing environment.

[0005] To address the aforementioned technical problems, one technical solution adopted in this application is as follows: a memory chip repair method is provided, applied to a host computer. The host computer is communicatively connected to multiple test service boards, each test service board including several test function boards, and each test function board electrically connected to a group of chips under test. The method includes: acquiring defect repair information of repairable chips in each group of chips under test; generating repair data corresponding to the repairable chips in each group of chips under test based on the defect repair information, and writing the repair data into the address mapping memory of the test function board corresponding to the repairable chips; sending a control signal to each group of chips under test, so that the repairable chips in each group of chips under test acquire a chip identifier corresponding to the repairable chips according to the control signal; and performing a repair process on the repairable chips in each group of chips under test according to the chip identifier and the repair data.

[0006] In some embodiments, before obtaining defect repair information for repairable chips in each group of tested chips, the method further includes: controlling each test function board to execute a preset test strategy, performing functional tests on each group of tested chips connected to each test function board, and obtaining corresponding test result data; determining whether there are defective units in the tested chips based on the test result data; if there are defective units in the tested chips, determining that the tested chips are defective chips; determining whether the defective chips meet the repairability conditions; if the defective chips meet the repairability conditions, determining that the defective chips are repairable tested chips, and recording the number of the repairable tested chips and the location information of the defective units in the repairable tested chips; wherein, the location information of the defective units includes defect row address information and defect column address information.

[0007] In some embodiments, obtaining defect repair information for repairable chips in each group of chips under test includes: determining location information for replacing defective units based on the location information of defective units in the repairable chips under test and preset spare units in the repairable chips under test; wherein the location information for replacing defective units includes replacement row address information and replacement column address information; obtaining first replacement information based on the number of the repairable chips under test and the replacement row address information; obtaining second replacement information based on the replacement column address information; and generating defect repair information corresponding to the repairable chips under test based on the first replacement information and the second replacement information.

[0008] In some embodiments, writing repair data into the address mapping memory of the test function board corresponding to the repairable chip under test includes: determining the target test function board based on the connection relationship between the repairable chip under test and the test function board, and determining the repair data for each group of repairable chips under test corresponding to each target test function board; and writing the repair data for each group of repairable chips under test into the address mapping memory of the corresponding target test function board through a preset service interface.

[0009] In some embodiments, a control signal is sent to each group of chips under test (DUTs) to enable the repairable DUTs in each group to obtain a chip identifier corresponding to the repairable DUT based on the control signal. This includes: sending a control signal to each group of DUTs to enable each group of DUTs to enter a repair preparation state; and sequentially performing an activation operation on the repairable DUTs in each group. The activation operation includes: outputting a data value to the data pin of each DUT to enable each DUT to judge the data value; if the data value is non-zero, then determining that the DUT receiving the non-zero data value is the target repairable DUT; and simultaneously receiving the chip identifier corresponding to the target repairable DUT; if the data value is zero, then determining that the DUT receiving the zero data value is a non-target repairable DUT; and simultaneously not receiving the chip identifier corresponding to the non-target repairable DUT.

[0010] In some embodiments, a repair process is performed on repairable chips in each group of tested chips based on chip identification numbers and repair data. This includes: performing a repair process on repairable chips in each group of tested chips until preset conditions are met. The repair process includes: generating input row address information and input column address information through an automatic logic pattern generator on a test function board corresponding to each group of repairable chips; transmitting the input row address information and input column address information to an address mapper on the test function board, so that the address mapper extracts repair data from an address-mapped memory based on the input row address information and input column address information; wherein the repair data includes the number of the repairable chip, replacement row address information, and replacement column address information; and determining whether the number of the repairable chip and the corresponding chip identification number are the same: if the number of the repairable chip and the corresponding chip identification number are the same, then receiving the repair data corresponding to the repairable chip, and performing defect unit repair operations on the repairable chip based on the repair data.

[0011] In some embodiments, based on repair data, a defect cell repair operation is performed on the repairable chip under test, including: performing a defect cell repair operation on the repairable chip under test, wherein the defect cell repair operation includes: disconnecting the defect row and defect column connection of the defect cell according to the location information of the defect cell in the repairable chip under test; and connecting the spare row and spare column of the spare cell in the repairable chip under test according to the replacement row address information and replacement column address information of the repairable chip under test.

[0012] To address the aforementioned technical problems, another technical solution adopted in this application is: providing a memory chip repair device, the device comprising: an acquisition module for acquiring defect repair information of repairable chips in each group of tested chips; a writing module for generating repair data based on the defect repair information and writing the repair data to an address-mapped memory of a test function board corresponding to the repairable chip; an activation module for sending a control signal to each group of tested chips, so that the repairable chips in each group of tested chips acquire a chip identifier corresponding to the repairable chip according to the control signal; and a repair module for performing a repair process on each group of repairable chips according to the chip identifier and the repair data.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of this application is: to provide a host computer, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned method.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of this application is: to provide a non-volatile computer-readable storage medium that stores computer-executable instructions, which, when executed by a host computer, cause the host computer to execute the above-mentioned method.

[0015] Unlike related technologies, this application provides a method, apparatus, host computer, and storage medium for repairing memory chips. The method involves acquiring defect repair information for repairable chips in each group of tested chips; generating repair data corresponding to the repairable chips in each group based on the defect repair information, and writing the repair data into the address-mapped memory of the test function board corresponding to the repairable chips; sending control signals to each group of tested chips to enable the repairable chips in each group to obtain their corresponding chip identifiers according to the control signals; and executing a repair process for the repairable chips in each group based on the chip identifiers and the repair data. Based on this, by dividing the repair data into corresponding address-mapped memories according to the test function boards, a parallel repair mechanism between test function boards and a serial repair mechanism within the test function boards is constructed, significantly improving chip repair efficiency and making it suitable for large-scale chip testing environments. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 This is a schematic diagram of the structure of an automatic testing device provided in an embodiment of this application; Figure 2 This is a schematic diagram of the hardware structure of a host computer for executing a memory chip repair method according to an embodiment of this application; Figure 3 This is a flowchart of a memory chip repair method provided in an embodiment of this application; Figure 4 This is a schematic diagram of a memory chip repair device provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0019] It should be noted that, unless otherwise specified, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device schematic diagram or the order in the flowchart. When an element is described as "connected" to another element, it can be directly connected to the other element, or there may be one or more intervening elements.

[0020] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0021] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application.

[0022] With the continuous evolution of semiconductor manufacturing processes, the integration and capacity of chips such as DDR DRAM (Double Data Rate Dynamic Random Access Memory) have been continuously increasing. The number of memory cells inside these chips has reached billions or even tens of billions, making the requirements for their reliability and yield increasingly stringent. In the chip manufacturing process, ATE (Automatic Equipment) is responsible for testing the functional and structural integrity of each chip. During testing, ATE applies test vectors as input stimuli to drive the chip under test (DUT) to respond and collect the output results to determine whether there are defects in its logic and memory cells.

[0023] For DDR DRAM chips, due to their large-scale memory array structure, the ATE (Automatic Equipment) must inspect the state of each memory cell corresponding to each bit. If an anomaly is found, it is marked as a defective cell, and its address information is recorded. To improve chip yield, modern memory chips are generally designed with spare cells, which can replace defective cells with spare cells after inspection through a repair mechanism, thereby achieving fault tolerance and functional recovery. The ATE equipment generates specific repair solutions by running a repair analysis program, specifying which spare rows / columns will replace the faulty rows / columns, and loads them into the address-mapped memory (Scrambler Memory) through an address translator (Scrambler). This Scrambler Memory serves as repair data to drive the DUT (Device Under Test) to perform repair operations in subsequent processes.

[0024] While current ATE testing systems possess mature detection and repair capabilities, efficiency bottlenecks still exist in the repair process for large batches of DUT chips. Current mainstream ATE platforms support parallel testing of a large number of chips (e.g., testing thousands of DDR DRAM chips at once), but once in the repair phase, they still employ a serial output strategy for repair data: that is, only one DUT is sent the row and column replacement information required for repair at a time, while the remaining DUTs remain idle and waiting. Specifically, in the repair process, the ATE serves only one DUT per cycle, loading and sending its corresponding Scrambler address mapping and repair data one by one, waiting for the DUT to receive and complete repair operations such as fuse breaking. This serial repair method leads to several problems: low repair efficiency: repair time increases linearly with the number of DUTs, severely limiting test throughput; wasted ATE resources: most DUTs are inactive during the repair process, failing to fully utilize parallel testing capabilities; unfavorable for large-scale production line deployment: in large-scale mass production environments, serial repair increases the time spent repairing each chip, affecting the overall production line cycle time; poor system scalability: it is difficult to effectively expand the number of DUTs and improve repair concurrency capabilities under a serial process. Therefore, there is an urgent need for a strategy that can break through the limitations of the existing serial repair process and give full play to the parallel capabilities of ATE, so as to fundamentally improve the overall efficiency and system utilization of the chip repair stage.

[0025] To address this, this application proposes a memory chip repair method, apparatus, host computer, and storage medium, aiming to overcome the performance bottleneck of the existing ATE serial repair mode, enabling simultaneous parallel repair of multiple DUT chips, and significantly improving repair efficiency and production line throughput. Without modifying the original repair pattern program, the data loading and address mapping method of the Scrambler Memory is finely designed and scheduled, allowing multiple DUTs to accurately obtain their required repair data based on their own DUT numbers within the same pattern process, thus achieving concurrent execution of repair actions.

[0026] Specifically, the memory chip repair method proposed in this application has the following characteristics: Partitioned loading of repair data: Based on the connection relationship between the DUT and the test function board, the repair data for each group of DUTs corresponding to each test function board is determined, and the repair data for each group of DUTs is written into the Scrambler Memory of the corresponding test function board, ensuring that the repair data is stored in partitions; Unchanged Pattern Process: The original repair pattern program is not modified, and its repair instruction sequence, address scanning method, and control logic are retained to maintain compatibility; DUT Self-Identification and Filtering Mechanism: During the activation phase, a non-zero value is sent through the data pin in the pattern to make a specific DUT record its own chip identifier, and in subsequent repair cycles, it autonomously determines whether to process the current cycle data by identifying the DUT number in the Scrambler address to avoid conflicts; Parallel Execution of Repair Actions: After each group of DUTs is tested in parallel according to the group, it can receive the valid repair data of each group according to the group and perform internal row and column replacement operations.

[0027] Based on this, the memory chip repair method proposed in this application significantly reduces the time required for the ATE repair stage. Furthermore, since it involves no intrusive modification to the original pattern process, it possesses good compatibility and ease of deployment, making it easy to integrate into existing testing platforms and providing a more efficient and feasible technical path for the large-scale mass production of high-density memory chips.

[0028] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an automatic testing device provided in an embodiment of this application. Figure 1 As shown, the automatic test equipment 1000 includes a host computer 100 and a test unit 200. The host computer 100 communicates with the test unit 200 via a control CPU. The test unit 200 is internally divided into multiple groups, each group containing multiple pairs of test service boards (e.g., test service boards 21, ...) and DUT socket boards (e.g., DUT board 31, ...). Each DUT socket board houses multiple sets of chips under test (e.g., DUT311, ...). The DUT socket board connects the pins of the DUT to the ATE pins to achieve electrical connection between the test service board and the chips under test. Each test service board includes several test function cards (e.g., test function card 211, ...) composed of an Automatic Logic Graphics Generator (ALPG), a Scrambler, a Scrambler Memory, a PDS / FC / SC, etc. Each test function card is electrically connected to a set of chips under test. For example, test function board 211 is electrically connected to DUT311, and test function board 212 is electrically connected to DUT312.

[0029] In the ATE (Automatic Test Equipment) for DDR DRAM chip testing, the host computer 100 is the core control and scheduling center of the entire automated test equipment 1000. Its role is equivalent to the "brain," responsible for the overall management and distribution control of test resources, processes, data acquisition and processing, and test commands. The host computer 100 typically consists of a high-performance industrial control computer or a customized embedded server system. Common forms include, but are not limited to: industrial PCs (IPCs, running Windows or Linux), customized main control modules (using proprietary RTOS or embedded Linux), PXI main control platforms (for modular ATE systems), and embedded control boards with network interfaces (for distributed test systems). In this embodiment, the functions of the host computer 100 include, but are not limited to: Test program management: loading and executing the test plan program, controlling the loading of pattern programs, parameter settings, test vectors, etc., and providing a graphical or script-based interface for engineers to configure test logic. Test process scheduling: controlling various stages of the test process, such as initialization, loading, running, comparison, and recording; allocating test tasks to different test service boards; and coordinating complex processes such as pattern loops, parameter scans, and temperature loops. Resource Control and Configuration: Controls data transmission between various test service boards and DUT socket boards; manages the initialization and startup / shutdown of modules such as the Automatic Logic Graphics Generator (ALPG), Scrambler, and PDS / FC / SC; controls the writing and configuration process of Scrambler Memory. Data Acquisition and Analysis: Collects test data in real time, including repair data and yield data, automatically performs comparative analysis, and provides a data visualization interface for engineers to debug and analyze. System Communication and Monitoring: Communicates with the factory MES system, programming platform, and remote debugging server to monitor ATE equipment status, power consumption, temperature, and test health status.

[0030] Please see Figure 2 , Figure 2 This is a schematic diagram of the hardware structure of a host computer for executing a memory chip repair method, provided in an embodiment of this application. Figure 2 As shown, the host computer 100 includes: at least one processor 11; and a memory 12 communicatively connected to the at least one processor 11. Figure 2 Taking a processor 11 as an example, the memory 12 stores instructions executable by at least one processor 11. These instructions, when executed by the at least one processor 11, enable the at least one processor 11 to perform the memory chip repair method proposed in this embodiment. The processor 11 and the memory 12 can be connected via a bus or other means. Figure 2 Taking the example of a connection between China and Israel via a bus.

[0031] The memory 12, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 11 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 12, thereby implementing the memory chip repair method.

[0032] The memory 12 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computing device. Furthermore, the memory 12 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 12 may optionally include memory remotely located relative to the processor 11, and these remote memories may be connected to the computing device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. One or more modules are stored in the memory 12 and, when executed by one or more processors 11, perform a memory chip repair method.

[0033] In the ATE (Automatic Test Equipment), the test unit 200 is a hardware structure unit responsible for directly interacting with the chip under test (DUT) and completing test execution. The test unit 200 is divided into multiple groups, each containing multiple pairs of test service boards and DUT socket boards. Among them, the test service boards and their internal test function boards are the core modules for performing refined electrical signal testing on the DUT. They bear the crucial responsibility of receiving instructions from the host computer and accurately generating and acquiring electrical signals at the physical layer. In this embodiment, the test service board is the middle-layer control module in the ATE, responsible for: distributing test commands, pattern programs, and repair data from the host computer to the test function boards; coordinating the resources of the test function boards to orderly send test waveforms to the DUT; and summarizing the DUT response results acquired by the test function boards and uploading them to the host computer for analysis. The functions of the test service board include, but are not limited to: strong control and coordination capabilities: managing the collaborative work of multiple test function boards; good scalability: supporting different numbers and types of test function board configurations and adapting to various chip specifications; and high real-time response capability: responding to host computer scheduling and test feedback at the nanosecond level.

[0034] Test function boards are functional unit cards on test service boards. Each test function board is mainly responsible for signal processing tasks on a certain number of DUT pins, typically including: generating test signal waveforms; receiving and comparing DUT outputs; and control signal conversion and address mapping (such as Scramble). Each test service board generally contains multiple test function boards, which work in parallel to achieve large-scale parallel chip testing. Test function boards typically consist of ALPG, Scrambler, ScramblerMemory, and PDS / FC / SC. Among them, APLG is an automatic logic pattern generator, responsible for generating address waveform sequences (such as Pattern) to drive DUT address lines. The Scrambler (address converter) is used to remap the addresses generated by ALPG to repair addresses in Scrambler Memory, realizing the conversion and output of repair data. PDS is a timing driver module, used to control the output timing of data and addresses. FC is a failure comparator, used to compare the acquired DUT output with the expected value to detect whether the DUT has passed. SC stands for Signal Acquisition Unit, used to acquire, buffer, package, and upload the DUT response signal (can be integrated into FC). In this embodiment, the functions of the test function board include, but are not limited to: Distributed parallel processing: Each test function board independently processes a portion of the pins, improving overall throughput; Support for repair functions: Supports flexible address replacement through Scrambler, and completes row and column repair in conjunction with technologies such as Fuse / laser; High bandwidth and high precision: Supports GHz-level clock frequencies and nanosecond-level precision testing.

[0035] In addition, the collaborative relationship between the test function board and the test service board is as follows: the host computer controls the test service board through the overall control command; the test service board distributes the control and test content (Pattern, Scramble Data) to the test function board; the test function board generates precise address and data signals based on ALPG and Scrambler, and connects to the DUT through the DUT board; after the test function board collects the DUT output, the FC / SC module performs data comparison and feedback; the test service board uploads the feedback results to the host computer for subsequent decision-making (such as repair judgment).

[0036] The memory chip repair method proposed in this application is described below through specific embodiments.

[0037] Please see Figure 3 , Figure 3 This is a flowchart of a memory chip repair method provided in an embodiment of this application. The method is applied to the host computer in the aforementioned ATE. Figure 3 As shown, the method includes steps S11-S14: Before step S11, the method further includes: S10: Control each test function board to execute a preset test strategy, perform functional tests on each group of chips under test connected to each test function board, and obtain corresponding test result data; based on the test result data, determine whether there are defective units in the chip under test; if there are defective units in the chip under test, determine that the chip under test is a defective chip; determine whether the defective chip meets the repairability conditions; if the defective chip meets the repairability conditions, determine that the defective chip is a repairable chip under test, and record the number of the repairable chip under test and the location information of the defective units in the repairable chip under test; wherein, the location information of the defective units includes defect row information and defect column information.

[0038] This step is a preprocessing step, primarily used to identify and screen memory chips (DUTs) with repairable value. The host computer controls various test function boards in the ATE (Automatic Test Equipment) to execute a series of test strategies to identify whether each tested chip contains physically defective cells and determine whether the chip meets the repairability criteria, thus providing accurate basic data support for subsequent repair processes. Its specific implementation process is as follows: First, the host computer, acting as the main control platform of the ATE system, issues a set of preset test strategies to each test function board. These strategies include specific read / write patterns (read / write address, data bit width, frequency, etc.), test voltage, and level tolerance configurations. The test strategies cover all valid addresses of the chip's memory array to ensure full coverage scanning. Subsequently, the ALPG within each test function board receives the test patterns from the host computer and sends read / write signals to the corresponding DUT in sequence. The Scrambler module is responsible for mapping logical addresses to physical addresses to simulate access scenarios in actual use. With the cooperation of the PDS / FC / SC modules, the test function boards collect the response results of the DUT at each address unit and compare them bit-by-bit with the preset expected values ​​to identify abnormal storage locations (i.e., units with bit errors or address errors). All response results are recorded and cached in real time as test result data.

[0039] Secondly, the host computer analyzes and statistically processes the collected test results data. For defective units, clustering algorithms or localization template techniques are used to further determine their positions in the physical array, extracting the corresponding row and column addresses, thereby constructing preliminary location information for the defective units.

[0040] Next, the host computer assesses each identified defective unit in conjunction with the chip's internal repair structure (such as the number of redundant rows / columns). If the defective chip meets the repairability criteria, such as whether the number and location of defective units meet a preset repair threshold (e.g., no more than 4 rows / columns and located within a specific area), then the DUT is determined to be a repairable chip; otherwise, it is an unrepairable chip.

[0041] Finally, for repairable tested chips, the system records the chip's number (such as test location number, logic number, etc.) and the location information of defective units (defect row address information, defect column address information) in the database to form a "defect repair information table" to provide data support for subsequent steps S11-S14.

[0042] This embodiment employs a high-coverage testing strategy to achieve comprehensive functional testing and defect identification of the chip under test. By combining this with the chip's redundant design structure, it quickly determines whether defects are repairable, thereby accurately selecting chips with repair value. This step improves the accuracy and efficiency of chip selection, avoiding resource waste caused by ineffective repair operations. Furthermore, by structurally recording chip serial numbers and defective unit location information, it provides a data foundation for subsequent repair data generation and execution, enhancing the automation control and batch repair capabilities of the entire ATE system. Ultimately, this step effectively improves yield control during the chip testing phase, reduces manufacturing costs, and enhances the overall adaptability and scalability of the system, demonstrating significant industrial application value.

[0043] S11: Obtain defect repair information for each group of tested chips that can be repaired.

[0044] The process of obtaining defect repair information for repairable chips in each group of tested chips includes: determining the location information for replacing defective units based on the location information of defective units in the repairable chips and preset spare units in the repairable chips; wherein the location information for replacing defective units includes replacement row address information and replacement column address information; obtaining first replacement information based on the number of the repairable chip and the replacement row address information; obtaining second replacement information based on the replacement column address information; and generating defect repair information corresponding to the repairable chip based on the first and second replacement information.

[0045] After identifying the repairable chip in step S10, the host computer extracts the location information of the defective unit based on these repairable chips. The location of the defective unit usually includes the defective row address information and the defective column address information.

[0046] Subsequently, according to the grouping, for each repairable chip under test in each group of chips under test, the system will allocate a suitable spare row or spare column address for each defective row or defective column based on the pre-designed spare unit (such as redundant rows or columns) resources inside the DUT and according to the preset repair strategy (such as giving priority to using the available redundant resources of adjacent rows or columns), that is, generate "replacement row address information" and "replacement column address information".

[0047] Next, the host computer will combine this replacement information with the DUT's number to generate the following two types of key information: First replacement information (used for X-direction address replacement in Scramble Memory): The DUT number (e.g., 16 bits) and the replacement row address information (e.g., 16 bits) are concatenated or encoded to form a complete set of X-direction replacement data. Since the Scrambler typically outputs a set of data every two X-address cycles, the encoding design must ensure that even-numbered X-addresses contain the DUT number, and odd-numbered cycles output their corresponding replacement row address information. Second replacement information (used for Y-direction address replacement in Scramble Memory): The replacement column address information is encoded in a fixed format and corresponds one-to-one with the Y address output by the Pattern. Each Y-address cycle can output a Y value in the Scramble Memory, which is the replacement column address information in the column direction.

[0048] Finally, after arranging the first and second replacement information in order, the host computer will construct the XScramble Memory according to the Scrambler interface requirements, in the manner of "outputting the DUT number in even-numbered X-cycles and outputting the replacement row address in odd-numbered X-cycles", and construct the YScramble Memory according to the manner of "each r Y address corresponds to r replacement column address information", thereby finally generating a complete data structure for repair operations. For example, assuming that a DUT number is 0x0012, its defective unit is row address 0x0A and column address 0x1F, and the system allocates a spare row address 0x15 and a spare column address 0x3C for it, then the first replacement information is (0x0012, 0x15), and the second replacement information is (0x3C). This information will eventually be written into the Scramble Memory at the following locations: XScramble Memory[0] = DUT ID: 0x0012; XScramble Memory[1] = Replacement row address: 0x15; YScramble Memory[0] = Replacement column address: 0x3C. By following this pattern, defect repair information for each group of tested chips can be obtained.

[0049] In this embodiment, the host computer can accurately generate defect repair information for each repairable chip under test and convert it into a standardized data format for subsequent storage in the Scrambler address mapping memory. This ensures both the integrity and timing correspondence of the repair data and that the Scrambler can accurately deliver the repair data to the target DUT at the correct cycle during subsequent Pattern execution. This supports automated, efficient, and parallel repair operations for multiple DUTs, significantly improving the overall throughput and repair capability of the test platform and reducing redundant dependence on Scrambler storage resources.

[0050] S12: Based on the defect repair information, generate repair data corresponding to the repairable chips in each group of tested chips, and write the repair data to the address mapping memory of the test function board corresponding to the repairable chips.

[0051] The process of writing repair data into the address mapping memory of the test function board corresponding to the repairable chip under test includes: determining the target test function board based on the connection relationship between the repairable chip under test and the test function board, and determining the repair data for each group of repairable chips under test corresponding to each target test function board; and writing the repair data for each group of repairable chips under test into the address mapping memory of the corresponding target test function board through a preset service interface.

[0052] First, the defect repair information generated in step S11 is standardized using the Scramble data format. This includes: for each repairable chip under test (DUT), the DUT number and replacement row address are combined to generate first replacement information; the replacement column address information serves as second replacement information; all repair information is encoded in chronological order according to the Pattern's operational requirements: that is, the Scrambler organizes the data flow according to the format of "even numbers X output DUT number, odd numbers X output corresponding row repair address; Y outputs column repair address sequentially"; finally, a set of address-mapped Scramble data conforming to the ALPG / Scrambler's operational logic is formed. It can be understood that this set of Scramble data represents the repair data corresponding to the repairable DUTs in this group of DUTs.

[0053] Secondly, to distribute and write Scramble data according to the test function board dimension where the DUT is located, avoiding the efficiency bottleneck of "all test function boards redundantly storing all DUT repair data", the following operations need to be performed before writing Scramble data, based on the connection relationship table between the DUT and the ATE test function board: traverse each repairable DUT and find its connected test function board number; for each test function board, collect the Scramble data of all DUTs on that test function board; and independently construct the required Scramble Data Set (repair dataset) for each test function board.

[0054] Secondly, distributed writing is implemented using the ATE business interface. It's understandable that in traditional ATE systems, the pre-defined Test Plan Program typically writes uniform scramble data to all test function boards by calling business interface layer functions provided by ATE (such as WriteScrambleMemory()). To maintain compatibility with traditional interfaces while simultaneously enabling data distribution by test function board, this embodiment adopts the following approach: The Test Plan Program itself remains unchanged; an intelligent data distribution logic layer is added to the business interface layer (ATE API Wrapper). When a write request is received, the system automatically identifies the test function board number to be written and writes its corresponding scramble data to the address-mapped memory of that test function board; each write operation only affects the target test function board, preventing redundant or irrelevant data from being written to other test function boards. For example, if test function board 211 is responsible for DUT 1 to DUT n, then its Scramble Memory will only write the Scramble data of DUT 1 to DUT n; if test function board 212 is responsible for DUT (n+1) to DUT (2n), then its Scramble Memory will only write the Scramble data of DUT (n+1) to DUT (2n).

[0055] The data writing process includes: the host computer sequentially calls the business interface function. For example, the business interface function is WriteScrambleMemory(); after the interface layer confirms the test function board number, it extracts the Scramble data required by the test function board from the pre-generated ScrambleData Set (repair dataset); it calls the driver layer interface to write to the Scramble Memory through a hardware communication link (such as SPI, I2C, or a proprietary bus protocol); it returns a write success signal and enters the writing process for the next test function board.

[0056] This embodiment efficiently distributes and stores the repair data of each repairable DUT according to the dimension of its respective test function board. Compared with the traditional approach of storing all DUT repair data uniformly across all test function boards, this significantly reduces the storage redundancy of Scramble Memory and shortens the write time of repair data. Simultaneously, it is fully compatible with existing Test Plan Programs and Pattern Programs, avoiding large-scale modifications to existing systems. Furthermore, by embedding intelligent data scheduling logic at the business interface layer, it achieves data isolation and parallel scheduling at the DUT granularity in the repair process, thereby supporting parallel repair at the test function board level and significantly improving ATE repair efficiency and test throughput.

[0057] S13: Send a control signal to each group of tested chips so that the repairable tested chip in each group can obtain the chip identification number corresponding to the repairable tested chip according to the control signal.

[0058] The process involves sending control signals to each group of chips under test (DUTs) to enable repairable DUTs within each group to acquire their corresponding chip identifiers. This includes: sending control signals to each group of DUTs to put them into a repair preparation state; and sequentially performing activation operations on the repairable DUTs within each group. The activation operations include: outputting data values ​​to the data pins of each DUT to allow each DUT to evaluate the data values; if the data value is non-zero, identifying the DUT that received the non-zero data value as the target repairable DUT; and simultaneously receiving the chip identifier corresponding to the target repairable DUT; if the data value is zero, identifying the DUT that received the zero data value as a non-target repairable DUT; and simultaneously not receiving the chip identifier corresponding to a non-target repairable DUT.

[0059] First, all DUTs are put into repair preparation state. Understandably, the host computer issues a "Enter Repair Preparation State" command through the ATE system. The test function board broadcasts this command to all DUTs via test pins, notifying them that they are currently in "Waiting to Activate State". In this state, the internal repair logic of the DUT begins listening for inputs on the data lines and address lines (X / Y lines), preparing to receive the DUT's chip identifier (DUT ID).

[0060] It should be noted that the chip identifier of the DUT is not pre-written, but dynamically injected during this step through an "activation process". The basic principle is: broadcast a data transmission to all DUTs; in each round of broadcasting, only one target DUT receives non-zero data, while the other DUTs receive invalid data with a value of zero; only the DUT that receives non-zero data reads its chip identifier (DUT ID) from the address pins (X / Y address lines); the outputs of the data lines and address lines are sent directly to the DUT as is without scramble.

[0061] The specific process includes: (1) The i-th activation loop (i=1,2,…,m): The host computer selects the DUT number to be activated this time as ; Control APLG to broadcast data to all DUT data pins, where: only The corresponding data pin sends a non-zero value, while all other DUT data pins send a zero value. Simultaneously, the current active address is sent via the X / Y address pins; this address value is... (2) All DUT received data: If a non-zero value is detected on its data pin, it determines that it is the target to be activated this time; then it reads the chip identifier from the current X address (or XY address combined) pin; and stores this number as an internal identification value (i.e., "self-DUT ID") in the local register; all other DUTs detect that the data pin is zero and automatically ignore the current X / Y address input without processing. (3) Repeat steps (1) and (2) until all repairable DUTs have been activated. For example, if there are 128 DUTs, 128 rounds of activation broadcasting are performed, and only one DUT is activated in each round. After completion, each DUT has recorded its own chip identifier internally.

[0062] It should be noted that during the activation process, the XY address output by ALPG is a non-Scramble address, that is, the "real address" that has not been transformed by the Scrambler. To prevent chip identification errors, the following verification measures can be added: each DUT immediately sends back a receive confirmation signal after activation; if a DUT does not respond correctly, the system reactivates the chip; for chips that do not meet the repair conditions, the system can set a skip mechanism to skip the activation round with the corresponding number.

[0063] In this embodiment, assigning a unique number to each repairable DUT (DUT) (i.e., DUT ID injection) provides a crucial prerequisite for subsequent distribution and identification of repair data based on Scramble address mapping. This method employs a "non-zero activation, zero ignore" broadcast mechanism, enabling the identification and activation of multiple DUTs without additional control lines, avoiding the overhead and complexity of independent communication. Simultaneously, all DUTs share address and data lines, achieving accurate multi-chip numbering solely through data content and address synchronization. This approach boasts advantages such as simplicity, high efficiency, and strong stability, significantly improving the testing and repair capabilities and automation level of the ATE system.

[0064] S14: Based on the chip identification number and repair data, perform the repair process for the repairable chips in each group of tested chips.

[0065] The process involves performing a repair procedure on repairable chips in each group of tested chips, based on the chip identification number and repair data. This includes: performing the repair procedure on repairable chips in each group of tested chips until preset conditions are met; the repair procedure includes: generating input row address information and input column address information using the automatic logic pattern generator of the test function board corresponding to each group of repairable chips; transmitting the input row address information and input column address information to the address mapper of the test function board, so that the address mapper can extract repair data from the address-mapped memory based on the input row address information and input column address information; wherein the repair data includes the chip number, replacement row address information, and replacement column address information of the repairable chip; and judging whether the chip number and the corresponding chip identification number are the same: if they are the same, then the repair data corresponding to the repairable chip is received, and based on the repair data, defect unit repair operations are performed on the repairable chip.

[0066] The defect cell repair operation on the repairable chip under test based on the repair data includes: performing defect cell repair operation on the repairable chip under test, which includes: disconnecting the defect row and defect column connection of the defect cell according to the location information of the defect cell in the repairable chip under test; and connecting the spare row and spare column of the spare cell in the repairable chip under test according to the replacement row address information and replacement column address information of the repairable chip under test.

[0067] In the production and testing of highly integrated DDR DRAM chips, defective cell repair is a crucial step in improving yield and production capacity. This step is a core design for automating and efficiently parallelizing this repair process. Its overall goal is to complete highly parallel physical repair operations on the ATE platform based on the chip identifier (DUT ID) activated in previous steps and its associated repair data. The specific implementation process is as follows: First, for each group of repairable chips under test, a repair address sequence is generated and sent to the Scrambler module. Understandably, the system first generates a series of consecutive address patterns using ALPG, representing the logical row and column coordinates of the repair data (input row address information and input column address information). These addresses are typically executed in a pattern loop, for example, the X address increments from 0 to the maximum value (e.g., ...). The address Y increments from 0 to... The X / Y addresses are entered into the Scrambler module for address remapping. This Scrambler module maps logical addresses to physical addresses based on a preset Scramble Memory. The X Scramble Memory provides the target DUT number and replacement row address information; the Y Scramble Memory provides the replacement column address information for the target DUT. Each test function board's Scramble Memory only stores data for the range of DUTs it is responsible for. For example, if test function board 211 is responsible for DUT311 (DUT1~DUTn), its Scramble Memory only stores Scramble mapping entries related to these DUTs. This locality optimization significantly reduces memory redundancy and matching latency. It should be noted that, assuming the number of test units in the ATE is g, the number of test service boards in each group is s, the number of test function boards per test service board is c, the total number of DUTs under test in the entire ATE is m, and the number of DUTs each test function board is responsible for is n, then... And when the maximum number of repair data per DUT is r, the X Scramble Memory contains The data, Y Scramble Memory contains Item data.

[0068] Secondly, the Scramble address broadcast matches the chip identifier of the repairable DUT. Understandably, as the Pattern runs continuously, each cycle outputs a scramble-converted X / Y address value and broadcasts it to all DUTs. Each DUT, based on its own DUT ID (chip identifier) ​​obtained in step S13, extracts the DUT ID (DUT number) field (usually embedded in the even-numbered entries of the X address) from the scramble-converted address and performs a matching check: if the DUT number carried in the current scramble address matches the chip identifier recorded by the DUT itself, then the broadcast is considered a repair instruction for that DUT, and the DUT enters the repair receiving state; otherwise, the DUT skips the address content of the current cycle, performs no operation, and remains in a standby state. This mechanism enables precise instruction distribution to multiple DUTs on the broadcast bus without establishing an independent communication path for each DUT, thus simplifying the circuit structure and improving synchronous repair efficiency.

[0069] Next, the repair data is received and the replacement action is executed. Understandably, after the DUT identified as the target matches the DUT number in the Scramble address, it extracts the corresponding replacement information from the subsequent cycle address passed by the Scrambler. The DUT utilizes internal fuse control mechanisms (such as fuse blowing, laser blowing, eFuse, etc.) to complete the following operations: Logical isolation: logically disconnecting the defective row and column containing the defective cell; Connection mapping: connecting the spare row and spare column to the original logical location of the defective cell; Information persistence: persistently writing the repair mapping relationship into the chip's internal configuration unit to ensure that subsequent access instructions can be correctly redirected. Through the above methods, the DUT completes the physical replacement process of its defective cell, thereby achieving good functionality.

[0070] In addition, while performing the repair operation, the ATE (Automatic Test Equipment) periodically reads the Pattern execution status and DUT feedback signals (such as Done Flag and Fuse Status bits) to determine whether the current repair is complete and whether there are any abnormalities such as fuse failure or incorrect address connection. Once any abnormality is detected, the system will interrupt the current process and resend or mark the abnormal test function board as an error for engineers to judge later. In addition, the system maintains a repair log in the background in real time, recording detailed information such as the number of repairs for each DUT, repair type (row / column), spare unit number, and whether the write was successful, providing basic data for subsequent analysis and mass production screening.

[0071] Finally, the system determines whether the repair process executed on the repairable DUTs in the group meets the preset conditions. Understandably, after the Scramble Pattern execution cycle ends, the system checks whether all repairable DUTs in the group have completed: if all DUTs marked as repairable have reported success, the repair process is marked as complete; if some DUTs are still incomplete or abnormally interrupted, the system can re-execute the repair process once or partially until one of the following preset conditions is met: all repairable DUTs in the group have completed repair; r repair attempts have been performed but still failed (r is the maximum fault tolerance); the maximum repair cycle limit configured by the system has been reached; or the process has been terminated by manual intervention from the operator. These preset conditions provide the system with flexible control boundaries, avoiding infinite loops while ensuring the maximum possible completion of qualified DUT repairs.

[0072] In this embodiment, by constructing a highly parallel repair process, the ATE platform no longer relies on the inefficient traditional serial repair process of each DUT. Instead, it utilizes the Scrambler address remapping mechanism to achieve multi-chip parallel identification, accurate matching, and rapid repair operations at the test function board level. Compared to traditional repair methods, it has the following significant advantages: Significantly improved repair speed: The repair action that was originally executed in a single thread is now performed concurrently on g×s×c DUTs, greatly shortening the total repair cycle; Improved ScrambleMemory efficiency: Localized storage of DUT-related data for each test function board avoids global redundancy, reduces memory load, and facilitates memory expansion; Enhanced system capacity adaptability: Facing the trend of increasing chip size and rapidly increasing repair data, it can more flexibly expand repair capabilities; Improved yield and enhanced stability: The repair mechanism automatically judges the DUT ID and data matching, reducing human intervention and the risk of mis-repair, and improving the overall yield; Applicable to high-end DRAM large-scale parallel testing scenarios: Especially suitable for applications such as DDR4 / DDR5 that have high defect tolerance requirements and large production capacity. Therefore, it not only improves repair efficiency and resource utilization in process design, but also significantly promotes the automation and intelligent upgrading of the DDR chip testing industry in engineering practice.

[0073] This application provides a method for repairing memory chips. Compared with the traditional ATE repair process, it has significant technical advantages and practical application value, specifically reflected in the following aspects: First, it significantly improves repair speed. In traditional ATE systems, the repair process is usually performed one DUT at a time, meaning only one DUT can be repaired at a time. This serial mechanism leads to long overall repair time and low resource utilization. This application, however, allocates and writes corresponding repair data to the Scramble Memory of each test function board according to the DUTs connected to the test function board. This allows each test function board to execute its own DUT repair tasks in parallel during the Pattern program's execution. Repair operations between DUTs on different test function boards do not interfere with each other, achieving parallel repair across test function boards. For example, in an ATE platform with g groups, each group containing s test service boards, and each test service board containing c test function boards, the repair efficiency is theoretically increased to s×c times that of the traditional method. Taking g=32, s=1, c=2 as an example, the traditional method can only repair one DUT at a time, while this application can repair g×s×c=64 DUTs in parallel, achieving a 64-fold improvement in repair speed and significantly optimizing test throughput and mass production efficiency.

[0074] Secondly, it is perfectly compatible with existing testing processes and program structures. The Pattern program and Test Plan Program used during the repair process require no modification; existing program resources already debugged on traditional ATE boards can be directly reused, greatly simplifying the deployment of the new solution. This is thanks to the fact that this application encapsulates the Scramble Memory data distribution logic within the ATE platform's software interface layer. When business interface functions such as WriteScrambleMemory() are called, the intelligent allocation of repair data among various test function boards is automatically completed, thereby achieving core function upgrades while maintaining the original interface calls. This mechanism significantly lowers the technical threshold for system compatibility modifications.

[0075] Third, it places virtually no learning burden on test engineers. Since the Pattern and Test Plan procedures remain unchanged, testers can directly use familiar tools and processes to complete the repair tasks without retraining or adapting to a new development environment. This "plug-and-play" repair solution retains the ease of use of traditional solutions while overcoming their technical bottleneck of insufficient parallelism.

[0076] Based on the memory chip repair method provided in the above embodiments, this application further provides a memory chip repair apparatus. Please refer to... Figure 4 , Figure 4 This is a schematic diagram of the memory chip repair device. Figure 4 As shown, the device 2000 includes: an acquisition module 2001, a writing module 2002, an activation module 2003, and a repair module 2004.

[0077] The module includes: an acquisition module 2001, used to acquire defect repair information of repairable chips in each group of tested chips; a writing module 2002, used to generate repair data based on the defect repair information and write the repair data to the address mapping memory of the test function board corresponding to the repairable chips; an activation module 2003, used to send control signals to each group of tested chips so that the repairable chips in each group can acquire the chip identifier corresponding to the repairable chips according to the control signals; and a repair module 2004, used to perform a repair process on each group of repairable chips according to the chip identifier and the repair data.

[0078] It should be noted that the above-described memory chip repair device can execute the memory chip repair method provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in the embodiments of the memory chip repair device can be found in the memory chip repair method provided in the embodiments of this application.

[0079] This application provides a non-volatile computer-readable storage medium storing computer-executable instructions. These instructions are executed by one or more processors to enable the at least one processor to perform the memory chip repair method described in the above embodiments. For example, the non-volatile computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0080] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for repairing a memory chip, applied to a host computer, wherein the host computer is communicatively connected to multiple test service boards, each test service board includes several test function cards, and each test function card is electrically connected to a group of chips under test, characterized in that... The method includes: Obtain defect repair information for repairable chips in each group of tested chips; Based on the defect repair information, repair data corresponding to the repairable chips in each group of chips under test is generated, and the repair data is written into the address mapping memory of the test function board corresponding to the repairable chips under test. A control signal is sent to each group of the tested chips so that the repairable tested chip in each group obtains the chip identification number corresponding to the repairable tested chip according to the control signal; Based on the chip identifier and the repair data, a repair process is performed on the repairable chips in each group of tested chips.

2. The memory chip repair method according to claim 1, characterized in that, Before acquiring defect repair information for repairable chips in each group of tested chips, the method further includes: Each of the test function boards is controlled to execute a preset test strategy to perform functional tests on each group of chips under test connected to each of the test function boards, and to obtain the corresponding test result data. Based on the test results data, it is determined whether there are defective units in the chip under test; If a defective unit is found in the chip under test, the chip under test is determined to be a defective chip. Determine whether the defective chip meets the repairability criteria; If the defective chip meets the repairable condition, then the defective chip is determined to be a repairable chip under test, and the number of the repairable chip under test and the location information of the defective unit in the repairable chip under test are recorded; wherein, the location information of the defective unit includes defect row address information and defect column address information.

3. The memory chip repair method according to claim 2, characterized in that, The step of obtaining defect repair information for repairable chips in each group of tested chips includes: Based on the location information of the defective unit in the repairable chip under test and the preset spare unit in the repairable chip under test, the location information for replacing the defective unit is determined; wherein, the location information for replacing the defective unit includes replacement row address information and replacement column address information; Based on the number of the repairable chip under test and the replacement row address information, the first replacement information is obtained; Based on the replacement column address information, the second replacement information is obtained; Based on the first replacement information and the second replacement information, defect repair information corresponding to the repairable chip under test is generated.

4. The memory chip repair method according to claim 1, characterized in that, The step of writing the repair data into the address mapping memory of the test function board corresponding to the repairable chip under test includes: Based on the connection relationship between the repairable chip under test and the test function board, the target test function board is determined, and the repair data of each group of repairable chips under test corresponding to each target test function board is determined. Through a preset business interface, the repair data of each group of repairable tested chips is written to the address mapping memory of the corresponding target test function board.

5. The memory chip repair method according to claim 1, characterized in that, Sending control signals to each group of the tested chips, so that the repairable tested chips in each group obtain the chip identifier corresponding to the repairable tested chip according to the control signals, includes: A control signal is sent to each group of the tested chips to put each group of the tested chips into a repair preparation state; For each group of tested chips that can be repaired, the activation operation is performed sequentially. The activation operation includes: Data values ​​are output to the data pins of each of the chips under test, so that each of the chips under test can judge the data values; If the data value is non-zero, then the chip under test that receives the non-zero data value is determined to be a target repairable chip under test; at the same time, the chip identification number corresponding to the target repairable chip under test is received. If the data value is zero, the chip under test that receives the data value of zero is determined to be a non-target repairable chip under test; at the same time, the chip identifier corresponding to the non-target repairable chip under test is not received.

6. The memory chip repair method according to claim 3, characterized in that, The step of performing a repair process on repairable chips in each group of tested chips based on the chip identifier and the repair data includes: For each group of tested chips, a repair process is performed on the repairable chips until preset conditions are met. The repair process includes: The input row address information and input column address information are generated by the automatic logic graph generator of the test function board corresponding to each group of repairable chips under test; The input row address information and the input column address information are transmitted to the address mapper of the test function board, so that the address mapper can extract the repair data from the address mapping memory based on the input row address information and the input column address information; wherein, the repair data includes the number of the repairable chip under test, the replacement row address information, and the replacement column address information; The serial number of the repairable chip under test and the chip identification number corresponding to the repairable chip under test are determined: If the number of the repairable chip under test is the same as the chip identifier corresponding to the repairable chip under test, then the repair data corresponding to the repairable chip under test is received, and a defect unit repair operation is performed on the repairable chip under test based on the repair data.

7. The memory chip repair method according to claim 6, characterized in that, The defect cell repair operation on the repairable chip under test based on the repair data includes: The defective cell repair operation is performed on the repairable chip under test, and the defective cell repair operation includes: Based on the location information of the defective unit in the repairable chip under test, disconnect the defective row and defective column connections of the defective unit; Based on the replacement row address information and replacement column address information of the repairable chip under test, the spare row and spare column of the spare unit in the repairable chip under test are connected.

8. A memory chip repair device, applied to a host computer, wherein the host computer is communicatively connected to multiple test service boards, each test service board including several test function cards, each test function card being electrically connected to a group of chips under test, characterized in that, The device includes: The acquisition module is used to acquire defect repair information of repairable chips in each group of chips under test; The writing module is used to generate repair data based on the defect repair information and write the repair data to the address mapping memory of the test function board corresponding to the repairable chip under test. An activation module is used to send a control signal to each group of the tested chips, so that the repairable tested chip in each group of the tested chips obtains the chip identification number corresponding to the repairable tested chip according to the control signal; The repair module is used to perform a repair process on each group of repairable tested chips according to the chip identifier and the repair data.

9. A host computer, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1-7.

10. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores computer-executable instructions, which, when executed by a host computer, cause the host computer to perform the method described in any one of claims 1-7.

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