Low-power consumption vehicle-mounted hibernation signal and CC signal holding latch circuit

Abstract

The application relates to a low-power-consumption vehicle-mounted sleep signal and CC signal holding latch circuit. The circuit mainly comprises a power sleep signal holding latch circuit and a CC signal holding latch circuit; the power sleep signal holding latch circuit comprises a WALKUP signal processing branch, a VCC_CUT signal processing branch and a first NAND gate logic combination module, the first NAND gate logic combination module is used for outputting a VCC_CUT_END signal; the CC signal holding latch circuit comprises a CC_IN signal processing branch, a CC_MCU_Det signal processing branch and a second NAND gate logic combination module, and the second NAND gate logic combination module is used for outputting a CC_State signal. The application can accurately and efficiently detect and hold the charging interface state without relying on a high-cost low-power-consumption MCU under the premise of keeping the vehicle-mounted power sleep state, so that the implementation cost is reduced and the energy consumption is optimized.

Description

Technical Field

[0001] This application relates to the field of vehicle charging technology, and in particular to a low-power vehicle sleep signal and CC signal holding latch circuit. Background Technology

[0002] In the electric vehicle sector, monitoring the charging interface status of on-board power supplies is crucial for ensuring charging safety and optimizing the charging process. With the booming development of the electric vehicle market, improving the efficiency of on-board power systems and reducing system costs have become common goals across the industry.

[0003] In existing technologies, the detection of the charging connector (CC) resistance status by the vehicle power supply typically relies on a low-power microcontroller unit (MCU). Vehicle power supplies generally include a sampling and identification circuit for the charging pile's CC resistance. In the power-on state, the power supply identifies the value of the CC resistance and uses different CC resistance values ​​to confirm the connection status of the electric vehicle's charging interface. (See relevant documentation for details.) Figure 1 As shown. In the power sleep state, the power supply needs to remain in sleep mode until a wake-up source appears to wake up the vehicle power supply; at the same time, when the CC resistor is connected in the sleep state, the connection state of the CC resistor also needs to be maintained until the CC resistor is disconnected; and in order to monitor the charging interface status in real time, the connection status of the CC resistor still needs to be continuously monitored by a low-power MCU in the power sleep state.

[0004] However, there are obvious drawbacks to using low-power MCUs for continuous monitoring: on the one hand, the introduction of low-power MCUs increases the hardware cost of the vehicle power system, which is not conducive to cost control; on the other hand, the MCU will generate additional energy consumption during continuous monitoring, which is contrary to the development direction of electric vehicles pursuing high energy efficiency and will also have a certain impact on the range of the vehicle power battery.

[0005] Therefore, overcoming the problems of high cost and high energy consumption in the existing technology of using low-power MCUs to monitor the CC signal of the vehicle charging interface is a problem to be solved in this technical field. Summary of the Invention

[0006] In view of the above-mentioned defects or improvement needs of the prior art, and in order to solve the problems of high cost and high energy consumption in the prior art of using low-power MCU to monitor the CC signal of the vehicle charging interface, this application provides a low-power vehicle sleep signal and CC signal holding latch circuit. Under the premise of keeping the vehicle power supply in sleep state, it can accurately and efficiently detect and maintain the charging interface status without relying on the high cost of low-power MCU, thereby reducing implementation cost and optimizing energy consumption.

[0007] The embodiments of this application adopt the following technical solutions:

[0008] This application provides a low-power vehicle sleep signal and CC signal holding latch circuit, including a power sleep signal holding latch circuit and a CC signal holding latch circuit;

[0009] The power sleep signal holding latch circuit includes a WAKEUP signal processing branch, a VCC_CUT signal processing branch, and a first NAND gate logic combination module. The WAKEUP signal processing branch is used to invert and delay the WAKEUP signal, and the VCC_CUT signal processing branch is used to invert and delay the VCC_CUT signal. The first NAND gate logic combination module includes two cross-connected NAND gates. The outputs of the WAKEUP signal processing branch and the VCC_CUT signal processing branch are respectively connected to the input of a NAND gate. The first NAND gate logic combination module is used to output the VCC_CUT_END signal.

[0010] The CC signal holding latch circuit includes a CC_IN signal processing branch, a CC_MCU_Det signal processing branch, and a second NAND gate logic combination module. The CC_IN signal processing branch is used to delay the CC_IN signal, and the CC_MCU_Det signal processing branch is used to invert and delay the CC_MCU_Det signal. The second NAND gate logic combination module includes two cross-connected NAND gates. The outputs of the CC_IN signal processing branch and the CC_MCU_Det signal processing branch are respectively connected to the input of a NAND gate. The second NAND gate logic combination module is used to output the CC_State signal.

[0011] By adopting the above technical solution, the charging interface status can be accurately and efficiently detected and maintained without relying on a high-cost low-power MCU, while keeping the vehicle power supply in a sleep state. This ensures charging safety, reduces the implementation cost of the vehicle power system, reduces additional energy consumption in the sleep state, and improves system energy efficiency.

[0012] In some embodiments, the operating logic of the power sleep signal holding latch circuit includes:

[0013] When the VCC_CUT signal is high and the WAKEUP signal is low, the VCC_CUT_END signal enters a high-level sleep state.

[0014] When the VCC_CUT signal goes low and the WAKEUP signal remains low, the VCC_CUT_END signal remains high and in a sleep state.

[0015] When the VCC_CUT signal remains low and the WAKEUP signal goes high, the VCC_CUT_END signal enters a low-level wake-up state.

[0016] When the VCC_CUT signal remains low and the WAKEUP signal goes low, the VCC_CUT_END signal remains low in the wake-up state.

[0017] By adopting the above technical solution, the power supply can enter or remain in a sleep state and enter or remain in a wake-up state according to different level combinations of VCC_CUT signal and WAKEUP signal, ensuring that the power supply accurately switches the working mode under different operating conditions. At the same time, it avoids the use of high-cost low-power MCU, reduces the implementation cost of the vehicle power supply system, reduces the extra energy consumption in the sleep state, and improves the system energy efficiency.

[0018] In some embodiments, the operating logic of the CC signal holding latch circuit includes:

[0019] When the CC_IN signal is high and the CC_MCU_Det signal is high, the CC_State signal enters a high-level state with CC resistance.

[0020] When the CC_IN signal remains high and the CC_MCU_Det signal goes low, the CC_State signal remains high and is in a CC resistor state.

[0021] When the CC_IN signal goes low and the CC_MCU_Det signal remains low, the CC_State signal enters a low-level state with no CC resistor.

[0022] By adopting the above technical solution, the connection state of the CC resistor of the charging interface can be accurately detected and stably maintained according to the different level states of the CC_IN signal and the CC_MCU_Det signal. That is, when there is a CC resistor, the indicator remains high, and when there is no CC resistor, it changes to a low level, ensuring charging safety. Moreover, it eliminates the need for an MCU, reducing the implementation cost of the vehicle power system, reducing the extra energy consumption in the sleep state, and improving the system energy efficiency.

[0023] In some embodiments, the WAKEUP signal processing branch includes a first inverter and a first RC delay circuit. The WAKEUP signal outputs a WAKEUP_NOT signal after passing through the first inverter, and then enters the first NAND gate of the first NAND gate logic combination module after passing through the first RC delay circuit. The VCC_CUT signal processing branch includes a second inverter and a second RC delay circuit. The VCC_CUT signal outputs a VCC_CUT_NOT signal after passing through the second inverter, and then enters the second NAND gate of the first NAND gate logic combination module after passing through the second RC delay circuit.

[0024] By adopting the above technical solution, the WAKEUP signal processing branch uses a first inverter to invert the WAKEUP signal and a first RC delay circuit to delay the WAKEUP signal; the VCC_CUT signal processing branch uses a second inverter to invert the VCC_CUT signal and a second RC delay circuit to delay the VCC_CUT signal. This can accurately process the signal. Combined with the first NAND gate logic combination module, it outputs the VCC_CUT_END signal. It can achieve accurate detection and stable maintenance of the power sleep signal without the need for an MCU, reducing the implementation cost of the vehicle power system, reducing the extra energy consumption in the sleep state, improving system energy efficiency, and ensuring charging safety.

[0025] In some embodiments, the VCC_CUT signal processing branch further includes a first logic generation module, which includes a third inverter and a first XOR gate. The input signal is input to the first XOR gate along with another clock signal after passing through the third inverter, and finally generates the VCC_CUT signal.

[0026] By adopting the above technical solution, a first logic generation module containing a third inverter and a first XOR gate is set to generate the VCC_CUT signal. Combined with the other settings, an MCU is not required, reducing the implementation cost of the vehicle power system and reducing the extra energy consumption in the sleep state to improve system energy efficiency.

[0027] In some embodiments, a voltmeter is provided at the WAKEUP signal input, the first RC delay circuit node, the VCC_CUT signal input, the second RC delay circuit node, and the VCC_CUT_END signal output.

[0028] By adopting the above technical solution, it is convenient to monitor the voltage at each key position in the power sleep signal holding latch circuit, which helps to accurately understand the circuit's working status and signal processing, and ensures that the circuit can stably and accurately output the VCC_CUT_END signal to realize the sleep and wake-up functions of the vehicle power supply.

[0029] In some embodiments, the CC_IN signal processing branch includes a third RC delay circuit, and the CC_IN signal enters the first NAND gate of the second NAND gate logic combination module after passing through the third RC delay circuit; the CC_MCU_Det signal processing branch includes a fourth inverter and a fourth RC delay circuit, and the CC_MCU_Det signal outputs a CC_MCU_Det_NOT signal after passing through the fourth inverter, and then enters the second NAND gate of the second NAND gate logic combination module after passing through the fourth RC delay circuit.

[0030] By adopting the above technical solution, the function of the CC signal holding latch circuit can be realized, accurately detect and stably maintain the charging interface state, ensure charging safety, and at the same time eliminate the need for an MCU, reduce the implementation cost of the vehicle power system, reduce the extra energy consumption in the sleep state, and improve system energy efficiency.

[0031] In some embodiments, the CC_MCU_Det signal processing branch further includes a second logic generation module, which includes a fifth inverter and a second XOR gate. The input signal is input to the second XOR gate along with another clock signal after passing through the fifth inverter, and finally generates the CC_MCU_Det signal.

[0032] By adopting the above technical solution, a second logic generation module is set up. Using the fifth inverter and the second XOR gate, the input signal is input together with another clock signal after passing through the fifth inverter and input to the second XOR gate to generate the CC_MCU_Det signal. Combined with the low-power vehicle sleep signal and the CC signal, the overall structure of the latch circuit is maintained. Without the need for an MCU, the implementation cost of the vehicle power system can be reduced, the extra energy consumption in the sleep state can be reduced to improve the system energy efficiency, and the charging interface status can be accurately detected and stably maintained.

[0033] In some embodiments, a voltmeter is provided at the CC_IN signal input, the third RC delay circuit node, the CC_MCU_Det signal input, the fourth RC delay circuit node, and the CC_State signal output.

[0034] By adopting the above technical solution, the voltage of relevant nodes in the CC signal holding latch circuit can be monitored, which helps to accurately detect and stably maintain the charging interface state and ensure charging safety. At the same time, combined with the feature that the overall circuit does not require an MCU, the implementation cost of the vehicle power system is further reduced, the extra energy consumption in the sleep state is reduced, and the system energy efficiency is improved.

[0035] In summary, this application includes at least the following beneficial technical effects:

[0036] 1. The circuit does not require the use of a low-power MCU, reducing the implementation cost of the vehicle power system;

[0037] 2. It avoids the additional energy consumption introduced by the continuous monitoring of the low-power MCU, reduces the energy consumption of the vehicle power system in the sleep state, and improves the system energy efficiency;

[0038] 3. It can accurately detect and stably maintain the charging interface status, ensuring the charging safety of electric vehicles. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A schematic diagram of the charging interface status detection of the vehicle power supply in the prior art provided in this application;

[0041] Figure 2 A schematic diagram of the power sleep signal holding latch circuit provided in this application;

[0042] Figure 3 A schematic diagram of the CC signal holding latch circuit provided in this application;

[0043] Figure 4 A simulation diagram of the first signal of the power sleep signal holding latch circuit provided in this application;

[0044] Figure 5 A simulation diagram of the second signal for the power sleep signal holding latch circuit provided in this application;

[0045] Figure 6 A simulation diagram of the first signal of the CC signal holding latch circuit provided in this application;

[0046] Figure 7 A simulation diagram of the second signal of the CC signal holding latch circuit provided in this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The application will now be described in detail with reference to the accompanying drawings and embodiments.

[0048] like Figure 2 and Figure 3 As shown in the figure, this application provides a low-power automotive sleep signal and CC signal holding latch circuit, including a power sleep signal holding latch circuit and a CC signal holding latch circuit. The power sleep signal holding latch circuit includes a WAKEUP signal processing branch, a VCC_CUT signal processing branch, and a first NAND gate logic combination module. The WAKEUP signal processing branch is used to invert and delay the WAKEUP signal, and the VCC_CUT signal processing branch is used to invert and delay the VCC_CUT signal. The first NAND gate logic combination module includes two cross-connected NAND gates. The outputs of the WAKEUP signal processing branch and the VCC_CUT signal processing branch are respectively connected to the input of a NAND gate. The first NAND gate logic combination module is used to output the VCC_CUT_END signal. The CC signal holding latch circuit includes a CC_IN signal processing branch, a CC_MCU_Det signal processing branch, and a second NAND gate logic combination module. The CC_IN signal processing branch is used to delay the CC_IN signal, and the CC_MCU_Det signal processing branch is used to invert and delay the CC_MCU_Det signal. The second NAND gate logic combination module includes two cross-connected NAND gates. The outputs of the CC_IN and CC_MCU_Det signal processing branches are each connected to the input of a NAND gate. The second NAND gate logic combination module is used to output the CC_State signal. Through this technical solution, while maintaining the vehicle power supply in sleep mode, the charging interface status can be accurately and efficiently detected and maintained without relying on a high-cost low-power MCU, ensuring charging safety, reducing the implementation cost of the vehicle power supply system, reducing additional energy consumption in sleep mode, and improving system energy efficiency.

[0049] For details, please refer to Figure 2 In some embodiments, the WAKEUP signal processing branch is used to invert and RC delay the WAKEUP signal, specifically including a first inverter and a first RC delay circuit. WAKEUP is the input signal; after passing through the first inverter, it outputs a WAKEUP_NOT signal (implementing logical inversion), and then passes through the first RC delay circuit before entering the first NAND gate of the first NAND gate logic combination module. The first RC delay circuit consists of a resistor R9 (10kΩ) and a capacitor C4 (1000pF). Current charges C4 through R9, utilizing the characteristic that capacitor voltage cannot change abruptly to achieve signal delay. The delay time can be approximated as t≈0.7×R×C, here approximately 0.7×10⁻⁶. 4 ×10 −9=7μs. In this branch, voltmeters are installed at the WAKEUP signal input and at the first RC delay circuit node. The two voltmeters are used to observe the voltage of the original WAKEUP signal and the RC circuit node, respectively, to facilitate the adjustment of the signal amplitude and delay characteristics.

[0050] In some embodiments, the VCC_CUT signal processing branch is used to invert and RC delay the VCC_CUT signal, specifically including a second inverter and a second RC delay circuit; the VCC_CUT signal is output as VCC_CUT_NOT after passing through the second inverter, and then enters the second NAND gate of the first NAND gate logic combination module after passing through the second RC delay circuit; the second RC delay circuit consists of R8 (1kΩ) and C3 (1000pF), with a delay time of approximately 0.7×10 3 ×10 −9 =0.7μs. The VCC_CUT signal processing branch also includes a first logic generation module, which includes a third inverter and a first XOR gate. After the input signal passes through the third inverter, it is input together with another clock signal (provided by the pulse source below) into the first XOR gate to finally generate the VCC_CUT signal. The logic of the XOR gate is "different inputs result in a high output, and the same inputs result in a low output", which is used to generate a specific logic waveform. For the first NAND gate logic combination module, it is formed by two NAND gates cross-connected to form a logic function unit, which can realize further logical operations or timing control of the signal, and finally output the VCC_CUT_END signal. Voltmeters are set at the VCC_CUT signal input, the second RC delay circuit node, and the VCC_CUT_END signal output. Multiple voltmeters are used to observe the original VCC_CUT signal, the RC node voltage, and the final output VCC_CUT_END voltage to assist in the analysis of logic and timing characteristics.

[0051] By adopting the above technical solution, the voltage at each key location in the power supply sleep signal latch circuit can be easily monitored. This helps to accurately understand the circuit's operating status and signal processing, ensuring that the circuit can stably and accurately output the VCC_CUT_END signal to achieve the sleep and wake-up functions of the vehicle power supply. The VCC_CUT_END signal directly controls the on / off state of the vehicle power supply's auxiliary source. When VCC_CUT_END is high, the auxiliary source is off, and the vehicle power supply enters sleep mode; when VCC_CUT_END is low, the auxiliary source is on, and the vehicle power supply is woken up.

[0052] The specific structural connections of the power sleep signal latch circuit include: the WAKEUP signal is input to the input of the first inverter, and the output of the first inverter is connected to the WAKEUP_NOT signal node; one end of R9 is connected to the WAKEUP signal node, and the other end is connected to one end of C4, with the other end of C4 grounded. The connection node between R9 and C4 is an RC delay output node, which is connected to the first input of the first NAND gate; the VCC_CUT signal is input to the input of the second inverter, and the output of the second inverter is connected to the VCC_CUT_NOT signal node; one end of R8 is connected to the VCC_CUT signal node, and the other end is connected to one end of C3, with the other end of C3 grounded. The connection node between R8 and C3 is an RC delay output node, which is connected to the second input of the second NAND gate; the second input of the first NAND gate is connected to the output of the second NAND gate, and the first input of the second NAND gate is connected to the output of the first NAND gate. Finally, the VCC_CUT_END signal is led out from the outputs of the two NAND gates.

[0053] Vehicle power supply sleep state control process: When the vehicle power supply needs to enter sleep state, the VCC_CUT signal becomes high and the WAKEUP signal becomes low. After processing by the first NAND gate logic combination module, the VCC_CUT_END signal becomes high, shutting off the vehicle power supply auxiliary source and the power supply enters sleep state. During sleep, even if the VCC_CUT signal fluctuates and becomes low, the cross-feedback logic of the first NAND gate logic combination module can still ensure that the VCC_CUT_END signal remains high, keeping the power supply in sleep mode. When the power supply needs to be woken up, the WAKEUP signal becomes high. After inversion and RC delay, the first NAND gate logic combination module is triggered, causing the VCC_CUT_END signal to become low, turning on the auxiliary source and waking up the power supply.

[0054] Table 1:

[0055]

[0056] Referring to Table 1 above, which shows the function table of the power sleep signal holding latch circuit in sequential order, where 1 represents a high level and 0 represents a low level. The operating logic of the power sleep signal holding latch circuit, as described in Table 1, includes the following: when the VCC_CUT signal is high and the WAKEUP signal is low, the VCC_CUT_NOT signal is low, the WAKEUP_NOT signal is high, and the VCC_CUT_END signal enters a high-level sleep state; when the VCC_CUT signal becomes low and the WAKEUP signal remains low, the VCC_CUT_NOT signal is high, the WAKEUP_NOT signal is high, and the VCC_CUT_END signal enters a high-level sleep state. The ND signal remains high in the sleep state; when the VCC_CUT signal remains low and the WAKEUP signal goes high, the VCC_CUT_NOT signal is high, the WAKEUP_NOT signal is low, and the VCC_CUT_END signal enters the low-level wake-up state; when the VCC_CUT signal remains low and the WAKEUP signal goes low, the VCC_CUT_NOT signal is high, the WAKEUP_NOT signal is high, and the VCC_CUT_END signal remains low in the wake-up state.

[0057] refer to Figure 4 As shown, shortly after VCC_CUT sends a high-level sleep signal, VCC_CUT goes low, while the VCC_CUT_END sleep signal remains high, effectively shutting down the auxiliary source and entering sleep mode. (Reference) Figure 5 As shown, after a period of time, the WAKEUP wake-up signal becomes active high, the VCC_CUT_END sleep signal goes low, waking up the auxiliary source and entering the working state.

[0058] By adopting the above technical solution, the power supply can enter or remain in a sleep state and enter or remain in a wake-up state according to different level combinations of VCC_CUT signal and WAKEUP signal, ensuring that the power supply accurately switches the working mode under different operating conditions. At the same time, it avoids the use of high-cost low-power MCU, reduces the implementation cost of the vehicle power supply system, reduces the extra energy consumption in the sleep state, and improves the system energy efficiency.

[0059] refer to Figure 3In some embodiments, the CC_IN signal processing branch is used to perform RC delay processing on the CC_IN signal, specifically including a third RC delay circuit; CC_IN is the input signal, which enters the first NAND gate of the second NAND gate logic combination module after passing through the third RC delay circuit; the third RC delay circuit consists of a resistor R12 (10kΩ) and a capacitor C7 (1000pF). Current charges C7 through R12, utilizing the characteristic that the capacitor voltage cannot change abruptly to achieve signal delay. The delay time can be approximated as t≈0.7×R×C, here approximately 0.7×10 4 ×10 −9 =7μs. In this branch, voltmeters are installed at the CC_IN signal input and at the node of the third RC delay circuit. The two voltmeters are used to observe the voltage of the original CC_IN signal and the RC circuit node, respectively, to facilitate the adjustment of the signal amplitude and delay characteristics.

[0060] In some embodiments, the CC_MCU_Det signal processing branch is used to invert and RC delay the CC_MCU_Det signal, specifically including a fourth inverter and a fourth RC delay circuit; the CC_MCU_Det signal is output as CC_MCU_Det_NOT after passing through the fourth inverter, and then enters the second NAND gate of the second NAND gate logic combination module after passing through the fourth RC delay circuit; the fourth RC delay circuit consists of R11 (1kΩ) and C6 (1000pF), with a delay time of approximately 0.7×10 3 ×10 −9 =0.7μs. The CC_MCU_Det signal processing branch also includes a second logic generation module, which includes a fifth inverter and a second XOR gate. After the input signal passes through the fifth inverter, it is input together with another clock signal (provided by the pulse source below) into the second XOR gate to finally generate the CC_MCU_Det signal. The logic of the XOR gate is "different inputs result in high output, and the same inputs result in low output", which is used to generate specific logic waveforms. For the second NAND gate logic combination module, it is formed by cross-connecting two NAND gates to form a logic function unit, which can realize further logical operations or timing control of the signal, and finally output the CC_State signal. Voltmeters are set at the CC_MCU_Det signal input, the fourth RC delay circuit node, and the CC_State signal output. Multiple voltmeters are used to observe the original CC_MCU_Det signal, the RC node voltage, and the voltage of the final output CC_State to assist in the analysis of logic and timing characteristics.

[0061] By adopting the above technical solution, the voltage of relevant nodes in the CC signal holding latch circuit can be monitored, which helps to accurately detect and stably maintain the charging interface state and ensure charging safety. At the same time, combined with the feature that the overall circuit does not require an MCU, the implementation cost of the vehicle power system is further reduced, the extra energy consumption in the sleep state is reduced, and the system energy efficiency is improved.

[0062] The specific structural connections of the CC signal latch circuit include: the CC_IN signal is input to one end of R12, the other end of R12 is connected to one end of C7, the other end of C7 is grounded, and the connection node between R12 and C7 is an RC delay output node, which is connected to the first input of the first NAND gate; the CC_MCU_Det signal is input to the input of the fourth inverter, and the output of the fourth inverter is connected to the CC_MCU_Det_NOT signal node; one end of R11 is connected to the CC_MCU_Det signal node, and the other end is connected to one end of C6, the other end of C6 is grounded, and the connection node between R11 and C6 is an RC delay output node, which is connected to the second input of the second NAND gate; the second input of the first NAND gate is connected to the output of the second NAND gate, and the first input of the second NAND gate is connected to the output of the first NAND gate, finally leading to the CC_State signal from the outputs of the two NAND gates.

[0063] CC resistor status detection process: When the charging gun is inserted into the vehicle charging interface, the CC_IN signal becomes high (CC resistor is present). After being delayed by the third RC delay circuit, it is input to the second NAND gate logic combination module. At the same time, the CC_MCU_Det signal is high. After inversion, a low-level CC_MCU_Det_NOT signal is obtained. After logic operation, the second NAND gate logic combination module outputs a high-level CC_State signal, indicating the presence of a CC resistor. During charging, if the CC_MCU_Det signal fluctuates and becomes low, the cross-feedback logic of the NAND gate can still keep the CC_State signal high. When the charging gun is pulled out, the CC_IN signal becomes low. After RC delay, it triggers the second NAND gate logic combination module, causing the CC_State signal to become low, indicating the absence of a CC resistor.

[0064] Table 2:

[0065]

[0066] Referring to Table 2 above, which shows the function table of the CC signal holding latch circuit in sequential order, where 1 represents high level and 0 represents low level. The operating logic of the CC signal holding latch circuit, as described in Table 2, includes the following: when both the CC_IN and CC_MCU_Det signals are high, the CC_MCU_Det_NOT signal is low, and the CC_State signal enters a high-level state with CC resistance; when the CC_IN signal remains high and the CC_MCU_Det signal goes low, the CC_MCU_Det_NOT signal is high, and the CC_State signal remains high with CC resistance; when the CC_IN signal goes low and the CC_MCU_Det signal remains low, the CC_MCU_Det_NOT signal is high, and the CC_State signal enters a low-level state without CC resistance.

[0067] refer to Figure 6 As shown, CC_IN being high indicates the presence of a CC resistor, and the MCU detects the CC resistor. After issuing a high-level CC_MCU_Det, CC_State remains high, indicating the presence of a CC resistor. (Reference) Figure 7 As shown, after a period of time, CC_IN goes low to indicate that there is no CC resistor. After there is no CC resistor, CC_State also goes low to indicate that there is no CC resistor.

[0068] By adopting the above technical solution, the connection state of the CC resistor of the charging interface can be accurately detected and stably maintained according to the different level states of the CC_IN signal and the CC_MCU_Det signal. That is, when there is a CC resistor, the indicator remains high, and when there is no CC resistor, it changes to a low level, ensuring charging safety. Moreover, it eliminates the need for an MCU, reducing the implementation cost of the vehicle power system, reducing the extra energy consumption in the sleep state, and improving the system energy efficiency.

[0069] Optionally, the selection and parameter determination of some circuit components in the embodiments of this application are as follows:

[0070] Resistors: R9 and R12 are selected as 10kΩ metal film resistors with an accuracy of ±5% and a rated power of 0.25W. This type of resistor has the characteristics of high stability and small temperature coefficient, which can ensure the delay time accuracy of the RC delay circuit.

[0071] Capacitors: C4 and C7 are ceramic capacitors with a capacitance of 1000pF and an accuracy of ±10%. The operating temperature range is -55℃ to 125℃, which meets the temperature requirements of the automotive environment. Ceramic capacitors also have the advantages of small size and good high-frequency characteristics, which facilitates circuit integration.

[0072] Inverters: 74HC series CMOS inverters (such as 74HC04) are selected. This series of inverters has a wide operating voltage range (2V~6V) and low static power consumption, which can meet the low power consumption requirements of automotive systems.

[0073] NAND gate: 74HC series CMOS NAND gate (such as 74HC00) is selected. It belongs to the same series as the inverter, has good compatibility, and has strong driving capability, which can ensure the stability of the output signal.

[0074] Voltmeter: A DC voltmeter is selected, with a measurement range of 0~5V and an accuracy of ±0.01V. It is used to monitor the voltage values ​​of key nodes in the circuit in real time, which facilitates circuit debugging and fault diagnosis.

[0075] In summary, this application has the following advantages:

[0076] 1. Cost advantage: This application achieves the maintenance of the vehicle power supply sleep state and the latching of the CC signal through pure hardware circuits (resistors, capacitors, inverters, NAND gates), without relying on low-power MCUs, which significantly reduces the hardware cost and design complexity of the vehicle power supply system.

[0077] Low power consumption advantage: All components in the circuit are low power devices. The static power consumption of the RC circuit and CMOS logic devices in the sleep state is extremely low. Compared with the MCU continuous monitoring mode, it greatly reduces the extra energy consumption of the vehicle power supply in the sleep state, which is conducive to improving the driving range of electric vehicles.

[0078] Stability and reliability advantages: Signal interference is filtered out by RC delay circuit and state latching is achieved by NAND gate cross-feedback logic, which avoids circuit false triggering or false switching caused by signal fluctuations and ensures the accuracy and stability of power sleep state control and CC signal detection.

[0079] Compatibility advantages: The circuit structure of this application is simple and the component selection is universal, which can be seamlessly compatible with the hardware architecture of existing vehicle power systems without the need for large-scale modification of existing systems, making it easy for engineering applications and mass production.

[0080] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A low-power vehicle-mounted sleep signal and CC signal holding latch circuit, characterized in that, This includes a power sleep signal holding latch circuit and a CC signal holding latch circuit; The power sleep signal holding latch circuit includes a WAKEUP signal processing branch, a VCC_CUT signal processing branch, and a first NAND gate logic combination module. The WAKEUP signal processing branch includes a first inverter and a first RC delay circuit, used to invert and delay the WAKEUP signal. The VCC_CUT signal processing branch includes a second inverter and a second RC delay circuit, used to invert and delay the VCC_CUT signal. The first NAND gate logic combination module includes two cross-connected NAND gates; the second input of the first NAND gate is connected to the output of the second NAND gate, and the first input of the second NAND gate is connected to the output of the first NAND gate. The output of the WAKEUP signal processing branch is connected to the first input of the first NAND gate. The output terminal of the VCC_CUT signal processing branch is connected to the second input terminal of the second NAND gate. The first NAND gate logic combination module is used to output the VCC_CUT_END signal. The working logic of the power sleep signal holding latch circuit includes: when the VCC_CUT signal is high and the WAKEUP signal is low, the VCC_CUT_END signal enters a high-level sleep state; when the VCC_CUT signal becomes low and the WAKEUP signal remains low, the VCC_CUT_END signal remains in a high-level sleep state; when the VCC_CUT signal remains low and the WAKEUP signal becomes high, the VCC_CUT_END signal enters a low-level wake-up state; when the VCC_CUT signal remains low and the WAKEUP signal becomes low, the VCC_CUT_END signal remains in a low-level wake-up state. The CC signal holding latch circuit includes a CC_IN signal processing branch, a CC_MCU_Det signal processing branch, and a second NAND gate logic combination module. The CC_IN signal processing branch includes a third RC delay circuit, which is used to delay the CC_IN signal. The CC_MCU_Det signal processing branch includes a fourth inverter and a fourth RC delay circuit, which is used to invert and delay the CC_MCU_Det signal. The second NAND gate logic combination module includes two cross-connected NAND gates. The second input of the first NAND gate is connected to the output of the second NAND gate, and the first input of the second NAND gate is connected to the output of the first NAND gate. The CC_IN signal... The output of the processing branch is connected to the first input of the first NAND gate, and the output of the CC_MCU_Det signal processing branch is connected to the second input of the second NAND gate. The second NAND gate logic combination module is used to output the CC_State signal. The working logic of the CC signal holding latch circuit includes: when the CC_IN signal is high and the CC_MCU_Det signal is high, the CC_State signal enters a high-level state with CC resistance; when the CC_IN signal remains high and the CC_MCU_Det signal becomes low, the CC_State signal remains high with CC resistance; when the CC_IN signal becomes low and the CC_MCU_Det signal remains low, the CC_State signal enters a low-level state without CC resistance.

2. The low-power vehicle sleep signal and CC signal holding latch circuit according to claim 1, characterized in that, The WAKEUP signal is output as WAKEUP_NOT after passing through the first inverter, and then enters the first NAND gate of the first NAND gate logic combination module after passing through the first RC delay circuit; the VCC_CUT signal is output as VCC_CUT_NOT after passing through the second inverter, and then enters the second NAND gate of the first NAND gate logic combination module after passing through the second RC delay circuit.

3. The low-power vehicle sleep signal and CC signal holding latch circuit according to claim 2, characterized in that, The VCC_CUT signal processing branch also includes a first logic generation module, which includes a third inverter and a first XOR gate. The input signal is input to the first XOR gate along with another clock signal after passing through the third inverter, and finally generates the VCC_CUT signal.

4. The low-power vehicle sleep signal and CC signal holding latch circuit according to claim 2, characterized in that, A voltmeter is provided at the WAKEUP signal input, the first RC delay circuit node, the VCC_CUT signal input, the second RC delay circuit node, and the VCC_CUT_END signal output.

5. The low-power vehicle sleep signal and CC signal holding latch circuit according to claim 1, characterized in that, The CC_IN signal enters the first NAND gate of the second NAND gate logic combination module after passing through the third RC delay circuit; the CC_MCU_Det signal outputs the CC_MCU_Det_NOT signal after passing through the fourth inverter, and then enters the second NAND gate of the second NAND gate logic combination module after passing through the fourth RC delay circuit.

6. The low-power vehicle sleep signal and CC signal holding latch circuit according to claim 5, characterized in that, The CC_MCU_Det signal processing branch also includes a second logic generation module, which includes a fifth inverter and a second XOR gate. After the input signal passes through the fifth inverter, it is input into the second XOR gate together with another clock signal to finally generate the CC_MCU_Det signal.

7. The low-power vehicle sleep signal and CC signal holding latch circuit according to claim 5, characterized in that, A voltmeter is provided at the CC_IN signal input, the third RC delay circuit node, the CC_MCU_Det signal input, the fourth RC delay circuit node, and the CC_State signal output.

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