A method and system for controlling the length of back-drilled residual piles of high-density interconnect plates

Abstract

This invention provides a method and system for controlling the length of back-drilled residual piles in high-density interconnect boards. The control method includes: S1 measuring the thickness (H4) of the back-drilled hole location across the entire board after drilling; S2 extracting representative boards of the thinnest, thickest, and intermediate thicknesses; S3 measuring the dielectric layer thickness (H1) hole by hole using optical measuring equipment, and determining the depth by contacting the signal layer PAD with a probe; S4 establishing a reference relationship between H4 and H1 of the intermediate boards; S5 dynamically calculating H1 for each board based on the reference relationship and the measured H4; S6 calculating the back-drilling depth setpoint by combining the measured copper thickness (H2) and safety distance; S7 generating and executing the processing program. This method accurately controls the residual pile length by dynamically compensating for board thickness differences. This invention effectively solves the back-drilling depth control deviation caused by board thickness tolerances, reduces the fluctuation of residual pile length, and avoids damage to the signal layer.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board (PCB) processing technology, specifically to a method and system for controlling the length of back-drilled residual posts in high-density interconnect boards, which is particularly applicable to the back-drilling process of multilayer boards in the field of high-speed signal transmission. Background Technology

[0002] In the field of high-speed, high-density interconnect board manufacturing, the impact of back-drilling process on signal integrity is becoming increasingly prominent.

[0003] Traditional back-drilling depth control methods have the following fundamental drawbacks:

[0004] 1. Theoretical prediction distortion: The signal layer depth is predicted based on the theoretical board thickness. However, the actual board thickness (H4) deviates significantly from the design value due to factors such as differences in medium flow and uneven distribution of glass fiber resin during the lamination process of multilayer boards. Moreover, the deviation increases nonlinearly with the increase of board thickness (e.g., when the board thickness exceeds 4.0 mm for more than 24 layers, the deviation rate is >3%).

[0005] 2. Conflict in safety margin: When using a fixed safety distance to compensate for the thickness tolerance of the plate, an excessive margin will cause the stub length to exceed the standard (e.g., >3mil), which will not meet the requirements of 56Gbps+ high-speed transmission; an insufficient margin will easily damage the signal layer and cause open circuit risk.

[0006] 3. Lagging measurement methods: There is a lack of in-situ, non-destructive direct measurement technology for dielectric layer thickness (H1). It can only be inferred through destructive slicing or indirect electrical testing, making it difficult to achieve personalized depth control for batch boards.

[0007] Industry practice has confirmed that the above method results in residual pile length fluctuations exceeding ±3 mil when processing high aspect ratio boards with 24 layers or more. In extreme cases, residual piles may be too short (open circuit in the borehole wall) or too long (signal reflection exceeds the standard). With the widespread adoption of ultra-high density interconnect boards and 56Gbps high-speed interfaces, there is an urgent need for a control solution that can simultaneously resolve the contradictions between accuracy, safety, and efficiency. Summary of the Invention

[0008] In view of this, the present invention provides a method for controlling the length of back-drilled residual piles in high-density interconnect boards, which solves the control deviation of back-drilling depth caused by board thickness tolerance, reduces the fluctuation of residual pile length, and avoids damage to the signal layer.

[0009] The objective of this invention is achieved through the following technical solution:

[0010] A method for controlling the length of back-drilled residual piles of high-density interconnect boards includes the following steps:

[0011] S1. After drilling holes in the PCB, use a board thickness measuring device to measure the board thickness (H4) at the back-drilled hole locations across the entire board;

[0012] S2. Extract the thinnest, thickest, and intermediate thickness plates as representative plates based on the traceability code;

[0013] S3. Use interlayer optical measurement equipment to measure the dielectric layer thickness (H1) of the representative board hole by hole: Insert the optical probe vertically into the back drill hole and abut against the signal layer PAD, and determine the depth from the surface layer to the signal layer by light source refraction;

[0014] S4. Construct a benchmark correspondence based on the ratio between the average H4 and the average H1 of the intermediate thickness plate;

[0015] S5. Based on the benchmark correspondence and the measured H4 value of each board, dynamically calculate the H1 value of each board;

[0016] S6. Calculate the set value of the back drilling depth of the single board by combining the measured copper thickness (H2) after electroplating and the preset safety distance;

[0017] S7. Generate and execute the back drilling machining program based on the set values.

[0018] This method establishes an initial thickness database covering all processing units by measuring the thickness of the back-drilled hole positions (H4) across the entire board, completely avoiding random deviations caused by local sampling. Based on a traceability code-based extreme value representative board extraction mechanism, it systematically captures boundary condition samples within the process tolerance range, providing crucial data carriers for in-depth analysis. The measurement method, where the interlayer optical measurement equipment is perpendicularly attached to the signal layer PAD, ensures that the measurement benchmark for the dielectric layer thickness (H1) is directly correlated with the physical interface of the functional layer, eliminating errors in dielectric layer compression deformation and interlayer offset accumulation that are often predicted in traditional theoretical calculations.

[0019] By utilizing the benchmark correspondence established using the average value of intermediate boards, the inherent proportional relationship between board thickness and dielectric layer thickness is scientifically revealed, giving the dynamic calculation model a verifiable physical basis and statistical reliability. Combining real-time data on electroplated copper thickness and safety distance parameters, the customized back-drilling depth for each board is calculated, optimizing the residual stub removal effect under the core constraint of preventing signal layer damage. The programmed execution process establishes a digital closed loop from data acquisition to processing control, significantly enhancing the process stability and result consistency of back-drilling for high aspect ratio PCBs, providing quantifiable quality assurance for high-speed signal transmission.

[0020] Preferably, in S2: the representative plate comprises one thinnest plate, one thickest plate, and three intermediate thickness plates.

[0021] A specific configuration of representative plates (1 thinnest plate + 1 thickest plate + 3 intermediate plates) forms a structured sampling framework, achieving a complete characterization of thickness distribution features while minimizing inspection costs. This configuration captures process boundary effects through the extreme value plate, while multiple intermediate plates provide statistically robust baseline central values, enabling subsequent extrapolation models to respond to extreme conditions while maintaining accuracy stability within the mainstream range. This balanced design provides cost-effective data support for dynamic parameter optimization, avoiding resource waste caused by over-inspection.

[0022] Preferably, in step S3: the interlayer optical measurement device locates the signal layer PAD by refraction and convergence of the CCD light source at the end of the probe and the emitted light source.

[0023] The measurement method, which involves vertically inserting an optical probe into and physically contacting the signal layer PAD, establishes a direct spatial correlation with the functional conductive layer, fundamentally avoiding indirect errors in dielectric layer thickness calculation. The refraction and convergence mechanism of the CCD and emission light sources constitutes a closed-loop optical path monitoring system. Real-time feedback on the contact status between the probe tip and the copper layer is obtained through changes in the light spot position, effectively overcoming the interference of hole wall roughness, dielectric inhomogeneity, and interlayer alignment deviations on measurement accuracy. This direct positioning technology elevates the accuracy of dielectric layer thickness measurement to the physical limits of optical systems, providing high-confidence raw data input for residual pile length control. Compared to traditional destructive slicing or electrical inference methods, this non-contact measurement significantly improves detection efficiency while maintaining accuracy, forming a key technological foundation for a closed-loop depth control system.

[0024] Preferably, the calculation formula for S5 is: H1 calculation = current plate H4 × (reference H1 / reference H4), where reference H1 is the average value of the measured value of the intermediate thickness plate H1, and reference H4 is the average value of the corresponding measured value of H4.

[0025] This linear proportional formula directly maps the measured H4 value of the current board to the estimated H1 value using a thickness-depth conversion coefficient (K = baseline H1 / baseline H4) established on a reference board. The formula clearly demonstrates the positive correlation between board thickness and dielectric layer thickness. The calculation process requires no complex parameter calibration or model training, significantly reducing implementation complexity. The proportional-based estimation mechanism can efficiently generate personalized dielectric layer data for all back-drilled holes on a batch of boards, reducing inspection costs to less than one-fifth of traditional methods while maintaining accuracy. This lightweight calculation model is particularly suitable for real-time processing needs on production lines, providing algorithmic support for large-scale industrial applications.

[0026] Preferably, in S6: the back drilling depth setting value = calculated H1 value + H2 - safety distance.

[0027] The back-drilling depth calculation model integrates a three-layer protection mechanism: the calculated H1 value ensures precise matching between the depth benchmark and the dielectric properties of the single board; the electroplated copper thickness H2 compensates for variations in the surface metal layer thickness; and a safety distance establishes a buffer space to prevent over-drilling. This structured design decomposes influencing factors in a spatial dimension, responding to major sources of variation such as dielectric layer thickness fluctuations, electroplating process deviations, and equipment positioning errors. In particular, by independently incorporating the copper thickness variable, it effectively solves the problem of systematic offset of residual pile length caused by neglecting plating variations in traditional methods. This model establishes a quantifiable balance between maximizing residual pile removal effectiveness and minimizing signal layer damage risk, providing deterministic algorithmic guarantees for precision machining.

[0028] Preferably, step S6 further includes: dynamically adjusting the back-drilling depth of the thin / thick plate region based on the first-piece verification result.

[0029] A differentiated depth adjustment strategy for extreme plate thicknesses is implemented under process boundary conditions: reducing the depth of the thinnest plate prevents over-drilling risks caused by thinning of the medium layer, while increasing the depth of the thickest plate ensures effective removal of residual piles in the thick medium zone. This mechanism responds to the compression effect of plate thickness tolerances on the processing safety window, maintaining process robustness through proactive adjustments. Compared to a fixed safety distance scheme, this strategy significantly reduces the processing risk coefficient of extreme plate thicknesses, resulting in a more concentrated distribution of overall residual pile lengths.

[0030] Preferably, in step S7: the back drilling process supports shim parameter configuration, and this parameter is disabled when back drilling on a full copper surface.

[0031] The configurable shim parameter design is compatible with the engineering requirements of traditional back-drilling processes, retaining technical flexibility to handle special working conditions; the function of automatically disabling the parameter during full-copper back-drilling eliminates the potential interference of invalid parameters on machining accuracy. This adaptive parameter management mechanism enables the method to seamlessly adapt to diverse production scenarios. It not only meets the technical requirements for auxiliary support in conventional machining, but also maintains the purity of core parameters under critical working conditions, improving the universality and reliability of the method implementation at the system level and reducing the debugging costs of process conversion.

[0032] Preferably, before S7, the process also includes: selecting the plate with the largest calculated back-drilling depth setting value to make the first piece, and verifying that the actual residual pile length meets the target range.

[0033] Prioritizing the selection of the plate with the shortest estimated residual pile length for first-piece verification focuses on confirmatory testing of process safety boundaries. This strategy establishes preventative quality control points before batch processing, rapidly identifying systemic deviations through the most sensitive samples. Compared to random first-piece selection, this method significantly improves risk detection efficiency and avoids batch processing accidents caused by model errors. This risk-ranking-based verification mechanism establishes an early warning barrier for process stability.

[0034] Preferably, the back drilling depth of the thin plate area and the thick plate area is dynamically adjusted based on the first piece verification results.

[0035] A depth-dynamic adjustment mechanism based on the first piece's measured data forms a closed-loop control system. Negative compensation in thin plate areas reduces over-drilling risk, while positive compensation in thick plate areas enhances the removal of residual piles. This differentiated strategy responds to the non-uniformity of material thickness distribution, improving overall processing consistency through local parameter optimization. This adaptive adjustment capability significantly enhances the robustness of the method to material tolerances, equipment drift, and environmental fluctuations, ensuring stable convergence of residual pile length control accuracy during long-term production. Particularly in cases with large plate thickness distribution spans, this mechanism can reduce length range differences by more than 50%.

[0036] Preferably, a control system for the length of back-drilled residual piles of high-density interconnect boards includes:

[0037] A plate thickness measuring device for performing step S1 of claim 1;

[0038] Interlayer optical measurement equipment for performing step S3 of claim 1;

[0039] A control processor is used to execute steps S2 and S4-S6 of claim 1;

[0040] A back-drilling processing device for performing step S7 of claim 1.

[0041] This control system industrializes a method for controlling the length of back-drilled pilings in high-density interconnect boards through a modular hardware architecture: a board thickness measurement device completes full-surface scanning data acquisition to build an initial thickness database; interlayer optical measurement equipment provides sub-micron dielectric layer depth data to establish key process benchmarks; the control processor executes real-time data fusion and algorithmic decisions to generate personalized processing instructions; and the back-drilling equipment achieves micron-level depth control execution. All modules work closely together through standardized data interfaces, establishing a digital closed loop of "measurement-decision-execution." Systematic integration not only improves the efficiency of method implementation but also eliminates human intervention errors through hardware-level data connectivity, providing a replicable technical platform for high-precision back-drilling processing. Especially in multilayer board mass production scenarios, this system can reduce process debugging time.

[0042] The advantages of this invention compared to the prior art are:

[0043] The method for controlling the length of back-drilled residual piles in high-density interconnect boards of the present invention achieves breakthrough improvements in the back-drilling process in multiple dimensions through an innovative technical architecture:

[0044] 1. Fundamental Improvement in Data Acquisition Accuracy: By employing full-board scanning thickness measurement, a thickness database covering all processing units is established, eliminating statistical biases caused by local sampling. Combined with direct positioning of the signal layer interface using an optical probe, in-situ non-destructive measurement of dielectric layer thickness is achieved for the first time. This direct measurement method avoids the dielectric compression deformation error in traditional lamination theory predictions, improving the accuracy of dielectric layer depth reference determination to the level of optical system resolution.

[0045] 2. Systematic Capture of Process Boundary Conditions: An extreme value representative plate screening mechanism based on traceability codes provides structured coverage of thin plates, thick plates, and benchmark plate samples. This design not only captures boundary risk points within the process tolerance range but also improves benchmark reliability through multiple intermediate plates, providing high-value input for dynamic models. Compared to traditional random sampling, this mechanism significantly enhances the expressive power of plate thickness distribution characteristics.

[0046] 3. Closed-loop realization of personalized processing: By dynamically calculating based on benchmark ratios, the measured thickness of a single board is transformed into personalized dielectric layer depth parameters. This lightweight algorithm avoids the cost of full inspection while maintaining calculation accuracy. Combining electroplated copper thickness data and a depth calculation model based on safety distances, the residual pile removal effect is maximized while preventing over-drilling. Finally, through programmed execution, the digital chain of "measurement-decision-processing" is established, reducing variations caused by human intervention.

[0047] In summary, the core advancements brought about by this solution are:

[0048] 1. Convergence of residual pile length fluctuation: Narrowing the distribution range of residual piles through single-plate characteristic response mechanism;

[0049] 2. Reduced processing risk: Differentiated safety strategies help reduce extreme plate damage incidents;

[0050] 3. Shortened process debugging cycle: Programmed closed-loop control reduces the time required for manual parameter adjustment.

[0051] These improvements provide the technological foundation for the mass production of ultra-high density interconnect boards, especially adapting to the stringent requirements for residual stub control in 56Gbps+ high-speed transmission scenarios. Attached Figure Description

[0052] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of a back-drilled hole according to an embodiment of the present invention.

[0054] Figure 2 This is a schematic diagram of the back hole plate thickness measurement according to an embodiment of the present invention.

[0055] Labeling explanation: 1 Initial section of the emitting light source, 2 Intersection of the emitting light source and the CCD light source, 3 Reflection section after the emitting light source contacts the probe, 4 Probe, 5 CCD light source. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0058] It should be noted that similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship commonly used when the product of this application is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0059] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0060] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0061] Example 1

[0062] This embodiment provides a method for controlling the length of back-drilled residual piles in a high-density interconnect board, including the following steps: S1. After drilling holes in the PCB, the board thickness (H4) at the back-drilled hole location is measured using a board thickness measuring device.

[0063] S2. Extract the thinnest, thickest, and intermediate thickness plates as representative plates based on the traceability code;

[0064] S3. Use interlayer optical measurement equipment to measure the dielectric layer thickness (H1) of the representative board hole by hole: Insert the optical probe vertically into the back drill hole and abut against the signal layer PAD, and determine the depth from the surface layer to the signal layer by light source refraction;

[0065] S4. Construct a benchmark correspondence based on the ratio between the average H4 and the average H1 of the intermediate thickness plate;

[0066] S5. Based on the benchmark correspondence and the measured H4 value of each board, dynamically calculate the H1 value of each board;

[0067] S6. Calculate the set value of the back drilling depth of the single board by combining the measured copper thickness (H2) after electroplating and the preset safety distance;

[0068] S7. Generate and execute the back drilling machining program based on the set values.

[0069] This method establishes an initial thickness database covering all processing units by measuring the thickness of the back-drilled hole positions (H4) across the entire board, completely avoiding random deviations caused by local sampling. Based on a traceability code-based extreme value representative board extraction mechanism, it systematically captures boundary condition samples within the process tolerance range, providing crucial data carriers for in-depth analysis. The measurement method, where the interlayer optical measurement equipment is perpendicularly attached to the signal layer PAD, ensures that the measurement benchmark for the dielectric layer thickness (H1) is directly correlated with the physical interface of the functional layer, eliminating errors in dielectric layer compression deformation and interlayer offset accumulation that are often predicted in traditional theoretical calculations.

[0070] By utilizing the benchmark correspondence established using the average value of intermediate boards, the inherent proportional relationship between board thickness and dielectric layer thickness is scientifically revealed, giving the dynamic calculation model a verifiable physical basis and statistical reliability. Combining real-time data on electroplated copper thickness and safety distance parameters, the customized back-drilling depth for each board is calculated, optimizing the residual stub removal effect under the core constraint of preventing signal layer damage. The programmed execution process establishes a digital closed loop from data acquisition to processing control, significantly enhancing the process stability and result consistency of back-drilling for high aspect ratio PCBs, providing quantifiable quality assurance for high-speed signal transmission.

[0071] In this embodiment, S2: the representative plate includes one thinnest plate, one thickest plate, and three intermediate thickness plates.

[0072] A specific configuration of representative plates (1 thinnest plate + 1 thickest plate + 3 intermediate plates) forms a structured sampling framework, achieving a complete characterization of thickness distribution features while minimizing inspection costs. This configuration captures process boundary effects through the extreme value plate, while multiple intermediate plates provide statistically robust baseline central values, enabling subsequent extrapolation models to respond to extreme conditions while maintaining accuracy stability within the mainstream range. This balanced design provides cost-effective data support for dynamic parameter optimization, avoiding resource waste caused by over-inspection.

[0073] In this embodiment, in S3: the interlayer optical measurement device locates the signal layer PAD by refraction and convergence of the CCD light source at the end of the probe and the emitted light source.

[0074] The measurement method, which involves vertically inserting an optical probe into and physically contacting the signal layer PAD, establishes a direct spatial correlation with the functional conductive layer, fundamentally avoiding indirect errors in dielectric layer thickness calculation. The refraction and convergence mechanism of the CCD and emission light sources constitutes a closed-loop optical path monitoring system. Real-time feedback on the contact status between the probe tip and the copper layer is obtained through changes in the light spot position, effectively overcoming the interference of hole wall roughness, dielectric inhomogeneity, and interlayer alignment deviations on measurement accuracy. This direct positioning technology elevates the accuracy of dielectric layer thickness measurement to the physical limits of optical systems, providing high-confidence raw data input for residual pile length control. Compared to traditional destructive slicing or electrical inference methods, this non-contact measurement significantly improves detection efficiency while maintaining accuracy, forming a key technological foundation for a closed-loop depth control system.

[0075] In this embodiment, the calculation formula for S5 is: H1 calculation = current plate H4 × (reference H1 / reference H4), where reference H1 is the average value of the measured value of the intermediate thickness plate H1, and reference H4 is the average value of the corresponding measured value of H4.

[0076] This linear proportional formula directly maps the measured H4 value of the current board to the estimated H1 value using a thickness-depth conversion coefficient (K = baseline H1 / baseline H4) established on a reference board. The formula clearly demonstrates the positive correlation between board thickness and dielectric layer thickness. The calculation process requires no complex parameter calibration or model training, significantly reducing implementation complexity. The proportional-based estimation mechanism can efficiently generate personalized dielectric layer data for all back-drilled holes on a batch of boards, reducing inspection costs to less than one-fifth of traditional methods while maintaining accuracy. This lightweight calculation model is particularly suitable for real-time processing needs on production lines, providing algorithmic support for large-scale industrial applications.

[0077] In this embodiment, in S6: the back drill depth setting value = calculated H1 value + H2 - safety distance. The safety distance is dynamically configured within the range of 0.5-3 mil based on the first piece verification result.

[0078] The back-drilling depth calculation model integrates a three-layer protection mechanism: the calculated H1 value ensures precise matching between the depth benchmark and the dielectric properties of the single board; the electroplated copper thickness H2 compensates for variations in the surface metal layer thickness; and a safety distance establishes a buffer space to prevent over-drilling. This structured design decomposes influencing factors in a spatial dimension, responding to major sources of variation such as dielectric layer thickness fluctuations, electroplating process deviations, and equipment positioning errors. In particular, by independently incorporating the copper thickness variable, it effectively solves the problem of systematic offset of residual pile length caused by neglecting plating variations in traditional methods. This model establishes a quantifiable balance between maximizing residual pile removal effectiveness and minimizing signal layer damage risk, providing deterministic algorithmic guarantees for precision machining.

[0079] In this embodiment, S6 further includes: dynamically adjusting the back drilling depth of the thin / thick plate region based on the first-piece verification result.

[0080] A differentiated depth adjustment strategy for extreme plate thicknesses is implemented under process boundary conditions: reducing the depth of the thinnest plate prevents over-drilling risks caused by thinning of the medium layer, while increasing the depth of the thickest plate ensures effective removal of residual piles in the thick medium zone. This mechanism responds to the compression effect of plate thickness tolerances on the processing safety window, maintaining process robustness through proactive adjustments. Compared to a fixed safety distance scheme, this strategy significantly reduces the processing risk coefficient of extreme plate thicknesses, resulting in a more concentrated distribution of overall residual pile lengths.

[0081] In this embodiment, in S7: the back drilling process supports shim parameter configuration, and this parameter is disabled when back drilling on a full copper surface.

[0082] The configurable shim parameter design is compatible with the engineering requirements of traditional back-drilling processes, retaining technical flexibility to handle special working conditions; the function of automatically disabling the parameter during full-copper back-drilling eliminates the potential interference of invalid parameters on machining accuracy. This adaptive parameter management mechanism enables the method to seamlessly adapt to diverse production scenarios. It not only meets the technical requirements for auxiliary support in conventional machining, but also maintains the purity of core parameters under critical working conditions, improving the universality and reliability of the method implementation at the system level and reducing the debugging costs of process conversion.

[0083] In this embodiment, before S7, the method further includes: selecting the plate with the largest calculated back drilling depth setting value to make the first piece, and verifying that the actual residual pile length meets the target range.

[0084] Prioritizing the selection of the plate with the shortest estimated residual pile length for first-piece verification focuses on confirmatory testing of process safety boundaries. This strategy establishes preventative quality control points before batch processing, rapidly identifying systemic deviations through the most sensitive samples. Compared to random first-piece selection, this method significantly improves risk detection efficiency and avoids batch processing accidents caused by model errors. This risk-ranking-based verification mechanism establishes an early warning barrier for process stability.

[0085] In this embodiment, the back drilling depth of the thin plate area and the thick plate area is dynamically adjusted based on the first article verification results.

[0086] A depth-dynamic adjustment mechanism based on the first piece's measured data forms a closed-loop control system. Negative compensation in thin plate areas reduces over-drilling risk, while positive compensation in thick plate areas enhances the removal of residual piles. This differentiated strategy responds to the non-uniformity of material thickness distribution, improving overall processing consistency through local parameter optimization. This adaptive adjustment capability significantly enhances the robustness of the method to material tolerances, equipment drift, and environmental fluctuations, ensuring stable convergence of residual pile length control accuracy during long-term production. Particularly in cases with large plate thickness distribution spans, this mechanism can reduce length range differences by more than 50%.

[0087] Example 2

[0088] A control system for the length of back-drilled residual piles of high-density interconnect boards includes:

[0089] 1. Plate thickness measuring device

[0090] The configuration is to perform a full-board scan of the PCB board after drilling, measure the actual board thickness (H4) of all back-drilled holes, and generate a thickness distribution database.

[0091] 2. Interlayer optical measurement equipment

[0092] Integrated optical probe and CCD light source system (see) Figure 2 ), used to perform non-contact dielectric layer thickness (H1) measurement on the back drill hole of the representative board, and to locate the PAD interface of the signal layer by optical path refraction at the end of the probe;

[0093] 3. Control processor

[0094] The communication connection board thickness measuring device and interlayer optical measuring equipment perform the following:

[0095] Representative boards (thinnest board × 1, thickest board × 1, middle board × 3) are selected based on traceability codes;

[0096] Construct a scaling factor K (K = baseline H1 / baseline H4) based on the average H4 and H1 values ​​of the intermediate plate;

[0097] Dynamically calculate the H1 value of each hole position on the batch board (H1 calculation = current board H4 × K);

[0098] The back drill depth setting value is calculated by combining the copper plating thickness (H2) and the safety distance (setting value = H1 calculated + H2 - safety distance);

[0099] 4. Back drilling equipment

[0100] Receives a customized machining program generated by the control processor and performs micron-level deep back drilling operations;

[0101] Supports adaptive management of shim parameters: Automatically disables shim compensation function when back-drilling on a full copper surface.

[0102] Modular data closed-loop process:

[0103] Data acquisition layer: Plate thickness measurement device (H4 full plate data) → Interlayer optical measurement equipment (representative plate H1 data);

[0104] Decision layer: Control processor (data fusion → proportional modeling → deep computing → instruction generation);

[0105] Execution layer: Back drilling equipment (programmed execution + adaptive parameter control).

[0106] This control system achieves the industrial-scale implementation of the control method for the length of back-drilled residual piles in high-density interconnect boards (Example 1) through a modular hardware architecture: the board thickness measurement device completes full-surface scanning data acquisition to build an initial thickness database; the interlayer optical measurement device provides submicron-level dielectric layer depth data to establish key process benchmarks; the control processor executes real-time data fusion and algorithmic decision-making to generate personalized processing instructions; and the back-drilling processing equipment achieves micron-level depth control execution. All modules work closely together through standardized data interfaces, establishing a digital closed loop of "measurement-decision-execution." Systematic integration not only improves the efficiency of method implementation but also eliminates human intervention errors through hardware-level data connectivity, providing a replicable technical platform for high-precision back-drilling processing. Especially in multilayer board mass production scenarios, this system can reduce process debugging time.

[0107] Example 3

[0108] I. Processing Flow

[0109] Inner layer fabrication → Inner layer inspection → Lamination → Edge trimming and grinding → Drilling → Electroplating → Back drilling → Resin plugging → Subsequent normal process

[0110] The entire production process utilizes an intelligent traceability system.

[0111] II. Back-drilled hole structure description

[0112] H1: Back-drilled dielectric layer thickness - refers to the distance from the surface copper to the target signal layer copper surface (all layers crossed by this path are isolation rings PAD, and the dielectric after drilling is glass fiber and resin).

[0113] H2: Copper thickness before back drilling - including the sum of the base copper thickness and the electroplated copper thickness.

[0114] Back-drilling target depth (H_target): Theoretically, it should be equal to H1+H2 (i.e., the total distance from the front surface copper layer to the target signal layer copper layer).

[0115] H4: Post-drilling board thickness - refers to the PCB board thickness after drilling and before electroplating (excluding the electroplated copper layer).

[0116] Stub length (H3): refers to the length of the remaining un-drilled section after back drilling (i.e., the stub value).

[0117] III. Plate thickness measurement after drilling (H4)

[0118] The thickness of the board is measured on all back-drilled holes using a board thickness measuring device to obtain the H4 value (for example, if there are 80 boards in a batch, the H4 of all back-drilled holes on all 80 boards is measured).

[0119] Based on the intelligent traceability code, representative panels are extracted from the batch:

[0120] 1 piece of the thinnest plate (H4 is the smallest)

[0121] 1 thickest plate (H4 is the largest)

[0122] Three plates of intermediate thickness (H4 is close to the average value)

[0123] (A total of 5 representative boards)

[0124] Example: The following explanation uses the thickest plate with the highest H1 value in the measurements as an example.

[0125] IV. Dielectric layer thickness measurement (H1)

[0126] 1. Measure the H1 value of the representative plate using interlayer optical measurement equipment. (Note: Since the equipment is relatively slow, performing full inspection of all holes would greatly affect efficiency and the equipment cost would be high. Therefore, a sampling inspection of the representative plate is adopted.)

[0127] 2. Measurement Principle:

[0128] a. Insert the optical probe vertically into the back borehole to be tested until it physically contacts the PAD of the target signal layer.

[0129] b. The equipment uses the refracted and intersecting optical path formed by the emitted light source and the CCD light source at the probe tip to accurately locate the PAD interface of the signal layer, thereby measuring the depth H1 from the surface layer to the signal layer. For example... Figure 2 1 is the initial section of the emitting light source, 2 is the section where the emitting light source and the CCD light source intersect, 3 is the reflection section after the emitting light source comes into contact with the probe, 4 is the probe, and 5 is the CCD light source.

[0130] 3. For the 5 representative boards selected in step 3 (1 thinnest board, 1 thickest board, and 3 in the middle), measure the dielectric layer thickness H1 of the back-drilled holes one by one.

[0131] 4. Data Examples and Baseline Establishment (Unit: mil):

[0132] 1 thinnest plate 104 74.65 75.28 -0.63 2 Thickest plate 110 80.50 79.62 +0.88 3 Intermediate plate 108.5 78.50 78.54 -0.04 4 Intermediate plate 108.1 78.20 78.25 -0.05 5 Intermediate plate 107.5 77.90 77.81 +0.09 Average value of intermediate plate (benchmark) 108.033 78.200 78.20 -

[0133] a. The table above shows the measured H4 value of the representative board and its corresponding measured H1 value.

[0134] b. Establish a baseline correspondence based on the average H4 value (108.033 mil) and average H1 value (78.200 mil) of the three intermediate boards. The baseline conversion factor K = baseline H1 / baseline H4 = 78.200 / 108.033.

[0135] c. Verification of the calculated H1 value: Taking the thinnest board as an example, its measured H4 = 104 mil. Based on the baseline correspondence, its H1 value is calculated as follows: Calculated H1 = 104 * (78.200 / 108.033) = 75.28 mil. The measured H1 = 74.65 mil, with a difference of -0.63 mil.

[0136] d. As shown in the table, the difference between the measured H1 value and the value calculated based on the benchmark relationship can be verified (thinnest board: -0.63mil, thickest board: +0.88mil). Based on this benchmark correspondence and the measured H4 value of each board, the H1 value of all back-drilled holes of all boards in the batch can be dynamically calculated.

[0137] V. Measurement of copper thickness after electroplating (H2)

[0138] After electroplating, the surface copper thickness is measured. Assuming the customer's minimum standard is 1.4 mil, the actual measured average copper thickness H2 is 1.7 mil.

[0139] VI. Back-drilling program generation and execution

[0140] 1. Calculation of back drill depth setting value: According to the formula in Example 1: Back drill depth setting value = Calculated H1 value + H2 - Safety distance

[0141] 2. Data Example and Calculation (Unit: mil, safety distance preset to 2mil):

[0142]

[0143] a. Example of setting value calculation (thinnest board hole position): Estimated H1 = 75.28 mil, H2 = 1.7 mil, safety distance = 2 mil. Back drilling depth setting value = 75.28 + 1.7 - 2 = 74.98 mil. Note: If the equipment requires the use of a shim (such as an aluminum sheet, assuming a thickness of 4 mil), then the drilling depth input to the equipment should be the setting value + shim thickness (74.98 + 4 = 78.98 mil). When the shim parameter is disabled, the equipment directly performs drilling according to the setting value; the shim thickness is added only when it is enabled. However, to optimize the residual pile length, the shim parameter can be disabled when back drilling on a full copper surface, and the setting value (74.98 mil) can be used directly for drilling.

[0144] b. Expected residual pile range: Based on the calculated H1 and the set value, the residual pile length H3 can be estimated to be between 1.37mil and 2.88mil (the actual range may be slightly larger due to factors such as copper thickness uniformity and equipment stability).

[0145] 3. First-item verification strategy:

[0146] Prioritize using the plate with the smallest estimated residual pile length (H3) (such as the thinnest plate in number 1 of the table above) to make the first piece. This focuses on confirming the process safety boundary (preventing over-drilling).

[0147] Verify whether the actual residual length of the first piece meets the target range (e.g., minimum target ≥ 1 mil).

[0148] 4. Dynamic adjustment based on the first article result:

[0149] If the measured length of the first residual pile is lower than the minimum target (e.g., target min = 1.0 mil, measured = 0.9 mil), then the back drilling depth of the thin plate area (e.g., plate with H4 in the range of 104-106 mil) will be negatively compensated (e.g., the overall drilling depth will be reduced by 0.5 mil).

[0150] If the measured maximum residual pile length of the first piece is higher than the expected value (e.g., expected ≤ 3.5mil, measured = 3.8mil), then the back drilling depth of the thick plate area (e.g., plate with H4 in the range of 108-110mil) will be positively compensated (e.g., the overall drilling depth will be increased by 0.5mil).

[0151] This dynamic adjustment mechanism aims to optimize the control of the extreme value plate and reduce the overall distribution range of residual pile length.

[0152] 5. Program Generation: Based on the measured H4 data, the established reference relationship, the measured H2, the preset safety distance, and the possible compensation amount, the plate thickness measuring device and the control processor automatically calculate the customized back-drilling depth setting value for each back-drilling hole position, and generate the corresponding back-drilling processing program instructions, which are then transmitted to the back-drilling processing equipment.

[0153] 6. Gasket Parameter Management: The back drilling program supports gasket parameter configuration to meet special working conditions, but this parameter is automatically disabled when back drilling on a full copper surface to ensure the accurate execution of core settings.

[0154] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method of controlling the length of a back-drilling stub after a high-density interconnection board is formed, characterized by, Includes the following steps: S1. After drilling holes in the PCB, use a board thickness measuring device to measure the board thickness H4 at the back-drilled hole location across the entire board; S2. Extract the thinnest, thickest, and intermediate thickness plates as representative plates based on the traceability code; S3. Use interlayer optical measurement equipment to measure the dielectric layer thickness H1 of the representative board hole by hole: Insert the optical probe vertically into the back drill hole and abut against the signal layer PAD, and determine the depth from the surface layer to the signal layer by light source refraction. S4. Construct a benchmark correspondence based on the ratio between the average H4 and the average H1 of the intermediate thickness plate; S5. Based on the reference correspondence and the measured H4 value of each board, dynamically calculate the H1 value of each board; the calculation formula is: H1 calculation = current board H4 × (reference H1 / reference H4), where reference H1 is the average value of the measured H1 value of the intermediate thickness board, and reference H4 is the average value of the corresponding H4 measured value. S6. Calculate the back-drilling depth setting value for a single board by combining the measured copper thickness H2 after electroplating and the preset safety distance; the back-drilling depth setting value = calculated H1 value + H2 - safety distance; dynamically adjust the back-drilling depth of the thin / thick plate area according to the first piece verification result; wherein, the depth of the thinnest plate is reduced to prevent over-drilling risk caused by the thinning of the medium layer, and the depth of the thickest plate is increased to ensure effective removal of residual piles in the thick medium area; S7. Generate and execute the back drilling machining program based on the set values.

2. The method for controlling the length of the back-drilled residual pile of the high-density interconnect board according to claim 1, characterized in that, In S2: The representative plate comprises one thinnest plate, one thickest plate, and three plates of intermediate thickness.

3. The method for controlling the length of back-drilled residual piles of high-density interconnect plates according to claim 1, characterized in that, In S3: The interlayer optical measurement device locates the signal layer PAD by refraction and convergence of the CCD light source (2) at the end of the probe and the emission light source (1).

4. The method for controlling the length of back-drilled residual piles of high-density interconnect plates according to claim 1, characterized in that, In S7: The back drilling process supports shim parameter configuration; this parameter should be disabled when back drilling on a full copper surface.

5. The method for controlling the length of back-drilled residual piles of high-density interconnect plates according to claim 1, characterized in that, Prior to S7, it also included: The first piece was made from the plate with the largest calculated back-drilling depth setting value to verify that the actual residual pile length met the target range.

6. The method for controlling the length of back-drilled residual piles of high-density interconnect boards according to claim 5, characterized in that: Based on the results of the first verification, the back drilling depth in the thin plate area and the thick plate area is dynamically adjusted.

7. A control system for the length of back-drilled residual piles of high-density interconnect boards, characterized in that, include: A plate thickness measuring device for performing step S1 as described in claim 1; Interlayer optical measurement equipment for performing step S3 as described in claim 1; A control processor is used to execute steps S2 and S4-S6 as described in claim 1; A back-drilling processing device for performing step S7 as described in claim 1.

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