Semiconductor device and method for manufacturing the same, electronic device

Abstract

The application provides a semiconductor device and a preparation method thereof and an electronic device, and belongs to the field of semiconductors. The preparation method of the semiconductor device comprises the following steps: providing a semiconductor device; etching a metal layer by using a dry etching process; etching the metal layer by using a wet etching process; forming a passivation layer on the surface of the metal layer, the inner wall and the bottom of the first groove and the third groove; and etching the passivation layer to remove the passivation layer on the surface of the gate pad and the source pad and the passivation layer with a preset width of the cutting channel. The application etches part of the metal layer of the chip by using the dry etching first, and then etches the remaining metal layer by using the wet etching. The transmittance of the dry etching stage is less than 40%, and the transmittance of the wet etching stage is less than 60%. The bottom of the metal layer morphology is prevented from being eroded and damaged, the product requirements are met, and the reliability of the product is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, its fabrication method, and an electronic device. Background Technology

[0002] Silicon carbide (SiC) is a typical representative of third-generation semiconductor materials and one of the most mature and widely used wide-bandgap semiconductor materials in terms of crystal growth technology and device manufacturing. Compared with silicon, it has a larger bandgap, higher thermal conductivity, higher electron saturation drift velocity, and a critical breakdown electric field 10 times that of silicon, making it an ideal semiconductor material for high-temperature, high-frequency, high-power, and radiation-resistant applications.

[0003] Highly integrated silicon carbide MOS devices offer advantages such as high resistance (≥50Ω) and small chip area (<0.5mm²). 2 The characteristics of silicon carbide MOS devices are as follows: Due to chip design requirements, the transmittance of the mask is too high (≥90%) during metal layer etching, resulting in the polymer not being effectively protected by conventional dry etching processes. The metal sidewalls and top morphology are relatively poor, failing to meet product requirements. This causes damage at the top of the metal and abnormal corrosion at the bottom. These problems severely affect the chip's performance and reliability.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method, as well as an electronic device, to solve the problem of sidewall damage caused by etching of metal layers.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for fabricating a semiconductor device, comprising: A semiconductor device is provided, the semiconductor device comprising at least two chips, a dicing channel between two adjacent chips, each chip comprising a termination region and an active region, the termination region being disposed around the periphery of the active region, the active region being provided with a gate pad and a source pad, and the surface of the chip being covered with a metal layer; A dry etching process is used to etch the metal layer to remove the metal layer between the gate pad and the source pad, and at the same time remove part of the metal layer on the surface of the scribe line. A first trench is formed at the position between the gate pad and the source pad, and a second trench is formed at the position of the scribe line. The metal layer is etched using a wet etching process to remove the metal layer on the surface of the terminal area, and at the same time remove the remaining metal layer of the cutting channel to the reserved width, forming a third trench at the location of the cutting channel. A passivation layer is formed on the surface of the metal layer, the inner walls of the first trench and the third trench, and at the bottom. The passivation layer is etched to remove the passivation layer on the surface of the gate pad and the source pad, as well as the passivation layer with a predetermined width of the etch path.

[0007] Preferably, the dry etching gas includes Cl2 and BCL3, the flow rate ratio of Cl2 and BCL3 is 1:1, and the dry etching time is 250s~400s.

[0008] Preferably, the wet etching reagents include nitric acid, acetic acid and phosphoric acid, with the nitric acid concentration being 3%~4%, the acetic acid concentration being 3%~4% and the phosphoric acid concentration being 70%~80%.

[0009] Preferably, the step of using a wet etching process to etch the metal layer, removing the metal layer on the surface of the terminal area, and simultaneously removing the remaining metal layer of the cutting path to the predetermined width includes: Photoresist is coated on the surface of the metal layer, and the first trench is filled with photoresist, while exposing the terminal area and the dicing track; Wet etching is used to remove the metal layer on the surface of the terminal area, and at the same time remove the remaining metal layer of the cutting channel to the reserved width.

[0010] Preferably, the step of using a wet etching process to etch the metal layer, removing the metal layer on the surface of the terminal area, and simultaneously removing the remaining metal layer of the cutting path to the predetermined width includes: The metal layer is etched using a wet etching process to remove the metal layer on the surface of the terminal area. At the same time, the width of the remaining metal layer along the first direction is reserved to 10μm.

[0011] Preferably, the passivation layer is etched using a dry etching process, and the gas used in the dry etching includes a fluorine-based gas.

[0012] Preferably, the etching of the passivation layer to remove the passivation layer on the surface of the gate pad and source pad, as well as the passivation layer with a predetermined width of the etch path, includes: The passivation layer is etched to remove the passivation layer on the surface of the gate pad and the source pad, while retaining the passivation layer with a width of 5 μm on one side of the dicing track along the first direction, and removing the passivation layer of the remaining portion of the dicing track.

[0013] Preferably, the semiconductor device further includes a first dielectric layer and a second dielectric layer, the first dielectric layer covering the surface of the chip, the second dielectric layer covering the surface of the first dielectric layer, and the metal layer covering the surface of the second dielectric layer.

[0014] Based on the same inventive concept, the present invention also provides a semiconductor device, comprising: Prepared using the method described above.

[0015] Based on the same inventive concept, the present invention also provides an electronic device, comprising: Semiconductor devices as described above.

[0016] Compared with the prior art, the method for fabricating the semiconductor device of the present invention has the following advantages: This invention employs a combination of dry etching and wet etching to partially etch the metal layer of the chip. The transmittance is optimized to <40% during the dry etching stage and <60% during the wet etching stage, preventing erosion and damage to the bottom of the metal layer morphology, meeting product requirements, and improving product reliability.

[0017] The semiconductor device and electronic device provided by this invention belong to the same inventive concept as the semiconductor device fabrication method provided by this invention. Therefore, the semiconductor device and electronic device provided by this invention have at least all the advantages of the semiconductor device fabrication method provided by this invention, and can improve the reliability of the semiconductor device and electronic device. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the metal layer morphology formed in one embodiment.

[0019] Figure 2 This is a structural schematic diagram of the metal layer morphology formed in another embodiment.

[0020] Figure 3 This is a structural schematic diagram of the metal layer morphology formed in another embodiment.

[0021] Figure 4 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0022] Figure 5 This is a top view of a semiconductor device according to an embodiment of the present invention.

[0023] Figure 6 yes Figure 5 The cross-sectional structure at point AA, and the schematic diagram of the structure after the first photoresist pattern is formed on the surface of the metal layer.

[0024] Figure 7 This is a schematic diagram of the structure after dry etching of the metal layer in one embodiment of the present invention.

[0025] Figure 8 This is a schematic diagram of the structure after the photoresist has been removed from soil 7.

[0026] Figure 9 This is a top view of a semiconductor device according to another embodiment of the present invention.

[0027] Figure 10 yes Figure 9 The cross-sectional structure at the BB point in the middle, and the schematic diagram of the structure after photoresist is coated on the surface of the metal layer.

[0028] Figure 11 This is a schematic diagram of the structure after etching the terminal region in one embodiment of the present invention.

[0029] Figure 12 This is a top view of a semiconductor device in one embodiment of the present invention.

[0030] Figure 13 This is a schematic diagram of the structure after a second photoresist pattern is formed on the surface of the passivation layer in one embodiment of the present invention.

[0031] Figure 14 This is a schematic diagram of the structure after etching the passivation layer in one embodiment of the present invention.

[0032] In the picture, 100 - Cutting track; 110 - First dielectric layer; 120 - Second dielectric layer; 130 - Metal layer; 140 - Photoresist; 150 - First trench; 160 - Second groove; 170 - Third groove; 180 - Passivation layer; 200 - Terminal region; 300 - Gate pad; 400 - Active region; 410 - Source pad. Detailed Implementation

[0033] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device proposed by the present invention, its manufacturing method, and the electronic device will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the following described embodiments, sometimes the same reference numerals are used commonly between different drawings to represent the same part or parts having the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0034] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0035] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0036] As shown Figures 1 to 3 in the figure, in order to achieve the interconnection between silicon carbide chips, different metal layers need to be formed between the silicon carbide chips. Therefore, it is necessary to etch the metal layers. After the etching is completed, for the normal metal layer morphology such as Figure 1As shown, the top and bottom of the metal layer morphology transition naturally. However, when etching different metal layers using only dry etching, the high transmittance of the mask and the resulting high load, high heat, and strong plasma environment are the root causes of rapid photoresist consumption, sidewall protection failure, and ultimately, metal morphology damage and bottom erosion. This can easily damage the formed metal morphology, for example, forming... Figure 2 The morphology at point a is abnormal, and the bottom is damaged, or as shown in the image. Figure 3 As shown at point b, the bottom of the metal layer morphology is eroded, resulting in relatively poor morphology of the sidewalls and top of the metal layer, which cannot meet the product requirements.

[0037] The core idea of ​​this invention is to provide a method for fabricating silicon carbide MOS devices that can avoid damage to the morphology of the metal layer, meet product requirements, and improve device reliability.

[0038] To achieve the above-mentioned goals, this invention provides a method for fabricating a silicon carbide MOS device, as described above. Figures 4 to 14 This invention discloses a specific embodiment of a method for fabricating a silicon carbide MOS device. The method for fabricating this semiconductor device includes the following steps S1 to S5.

[0039] Step S1: Provide a semiconductor device, the semiconductor device including at least two chips, with a dicing channel 100 between two adjacent chips, each chip including a terminal region 200 and an active region 400, the terminal region 200 being disposed around the periphery of the active region 400, the active region 400 being provided with a gate pad 300 and a source pad 410, and the surface of the chip being covered with a metal layer 130.

[0040] Specifically, refer to Figures 4 to 6As shown, a semiconductor device is provided, comprising at least two chips. A dicing channel 100 is provided between adjacent chips. Each chip includes a termination region 200 and an active region 400. The termination region 200 is disposed around the periphery of the active region 400. The active region 400 is provided with pads, including a gate pad 300 and a source pad 410. The semiconductor device also includes a first dielectric layer 110 and a second dielectric layer 120, the first dielectric layer 110 covering the surface of the chip, the second dielectric layer 120 covering the surface of the first dielectric layer 110, and a metal layer 130 covering the surface of the second dielectric layer 120. The first dielectric layer 110 may be a field oxide (FLOX). The field oxide layer is used to isolate thick oxide layers between different active regions (such as transistors), achieving electrical isolation between devices and preventing leakage or short circuits. The second dielectric layer 120 can be an inter-layer dielectric (ILD) layer, used between the transistor and the first metal layer as an insulating dielectric layer to achieve electrical isolation and support the multilayer wiring structure. The metal layer 130 mentioned above is the first metal layer located on the chip surface.

[0041] Semiconductor devices can also include three, four, or more chips. For example, they can be like... Figure 5 As shown, as one example, the semiconductor device may include four chips, including chip 1, chip 2, chip 3, and chip 4. The four chips are symmetrically arranged about the dicing line 100.

[0042] Step S2: The metal layer 130 is etched using a dry etching process to remove the metal layer 130 between the gate pad 300 and the source pad 410, and at the same time remove part of the metal layer 130 on the surface of the dicing track 100. A first trench 150 is formed at the position between the gate pad 300 and the source pad 410, and a second trench 160 is formed at the position of the dicing track 100.

[0043] Specifically, refer to Figures 4 to 8 As shown. Dry etching is used to etch the metal layer 130 to remove the metal layer 130 between the gate pad 300 and the source pad 410 (i.e., Figure 5 The metal layer at the point indicated by arrow c is removed, along with a portion of the metal layer 130 on the surface of the etch path 100. A first trench 150 is formed between the gate pad 300 and the source pad 410, and a second trench 160 is formed at the location of the etch path 100. The dry etching gases include Cl2 and BCl3. The flow rate ratio of Cl2 to BCl3 gases is 1:1. The dry etching time is 250s to 400s.

[0044] The specific etching steps are as follows: Photoresist 140 is coated on the surface of metal layer 130; Through exposure and development, the first mask pattern is transferred to the photoresist 140 to form the first photoresist pattern, forming a pattern as shown in the image. Figure 6 The structure shown is as follows. It should be noted that because the angle of the first etching cannot be perpendicular, and the dry etching in this step and the subsequent wet etching cannot completely copy the etched pattern onto the chip, there is a certain deviation between the two etching processes.

[0045] Dry etching is used to etch the metal layer 130 to form the first trench 150 and the second trench 160, forming a structure as shown in the image. Figure 7 The structure shown.

[0046] Finally, the photoresist 140 is removed to form a shape like... Figure 8 The structure is shown. For etching at the dicing location 100, the metal layer 130, the second dielectric layer 120, and the first dielectric layer 110 are removed, exposing the chip.

[0047] By selectively removing the metal layer 130 in specific areas, the deposited continuous metal film is precisely etched into the interconnect pattern required by the design, thereby physically separating and forming independent gate pads 300 and source pads 410, while achieving reliable isolation between the internal electrical connections of the device and the critical electrodes.

[0048] In this dry etching stage, the transmittance of the first mask is optimized to <40%. High-precision pattern definition is prioritized in the low-temperature plasma region. By utilizing low ion energy and limited reaction area, the failure of photoresist 140 caused by heat accumulation and ion focusing damage on the metal top are eliminated at the source. After the key pattern is formed in one go during the dry etching stage, it is tightly isolated from the wet environment by photoresist 140, achieving effective protection of the pattern in the critical areas.

[0049] Step S3: The metal layer 130 is etched using a wet etching process to remove the metal layer 130 on the surface of the terminal area 200. At the same time, the remaining part of the metal layer 130 in the cutting channel 100 is removed to the reserved width, forming a third trench 170 at the position of the cutting channel 100.

[0050] Specifically, refer to Figure 4 , Figures 8 to 11 As shown, wet etching is used to continue etching the metal layer 130 on the surface of the terminal region 200. Simultaneously, the remaining portion of the metal layer 130 in the etch path 100 is removed to the pre-reserved width, forming a third trench 170 at the location of the etch path 100. The wet etching reagents include nitric acid, acetic acid, and phosphoric acid. The concentrations of nitric acid, acetic acid, and phosphoric acid are 3%–4%, 3%–4%, and 70%–80%, respectively. A pre-reserved trench 170 is formed on one side along the first direction (i.e.,...). Figure 9 The width d1 (in the direction of the middle arrow X) is 10μm to ensure that the oblique waveform formed by the first metal etching cut 100 and the chip edge contact part is not completely etched.

[0051] The third groove 170 is at the same position as the second groove 160. Furthermore, the second groove 160 and the third groove 170 are aligned along the second direction (i.e., Figure 11 The central axis of the third trench 170 (in the direction of the middle arrow Y) coincides with the central axis of the second direction. The depth of the third trench 170 along the second direction remains unchanged, and the third trench 170 located in the metal layer 130 along the first direction (i.e., Figure 11 The width of the direction (where the middle arrow X is located) increases.

[0052] The metal layer 130 is etched using a wet etching process to remove the metal layer 130 on the surface of the terminal region 200, and simultaneously removes the remaining portion of the metal layer 130 in the cutting channel 100 to the reserved width, including: Photoresist 140 is coated on the surface of the metal layer 130, and the first trench 150 is filled with photoresist 140, while exposing the terminal region 200 and the dicing track 100, forming a shape as shown in the image. Figure 10 The structure shown; A wet etching process is used to remove the metal layer 130 on the surface of the terminal region 200, and simultaneously remove the remaining portion of the metal layer 130 on the cutting path 100 to the predetermined width, forming a shape as shown. Figure 11 The structure shown. The metal layer 130, with a width d1 of 10 μm reserved along the first direction after removing the remaining portion of the cutting channel 100.

[0053] The purpose of etching away the metal layer 130 of the peripheral terminal region 200 is to avoid the metal layer 130 covering the critical high-voltage terminal structure of the device, such as field limiting rings (FLRs) or junction termination extensions (JTEs), and to ensure the uniform distribution of the electric field under the blocking state, thereby ensuring the high-voltage reliability and long-term stability of the device.

[0054] In this wet etching stage, the transmittance is optimized to <60%, and large metal areas are selectively removed by chemical solutions to avoid plasma physical bombardment and completely eliminate the risk of lateral drilling and bottom erosion.

[0055] Step S4: A passivation layer 180 is formed on the surface of the metal layer 130, the inner walls of the first trench 150 and the third trench 170, and at the bottom.

[0056] Step S5: Etch the passivation layer 180 to remove the passivation layer 180 on the surface of the gate pad 300 and the source pad 410, as well as the passivation layer 180 with a set width along the first direction at the location of the cut track 100.

[0057] Specifically, refer to Figure 4 , Figures 12 to 14 As shown, the passivation layer 180 is etched to remove the passivation layer 180 from the surfaces of the gate pad 300 and the source pad 410, leaving a cleaving path 100 along the first direction (i.e., Figure 12 A passivation layer 180 with a single-sided width d2 of 5 μm (in the direction of the middle arrow X) is removed, and the remaining portion of the passivation layer 180 at the dicing track 100 is removed. Dry etching is used to remove the gate pad 300 and source pad 410, as well as the 5 μm passivation layer 180 left on one side of the dicing track 100. The gases used for dry etching include fluorine-based gases such as CF4, SF6, C2F6, and NF3. The purpose of extending the passivation layer 180 to cover the chip is to reduce mechanical stress concentration points and prevent moisture corrosion.

[0058] The specific etching steps are as follows: Photoresist 140 is coated on the surface of the passivation layer 180; A second photoresist pattern is formed on the surface of the passivation layer 180 by photolithography and development, forming a pattern such as... Figure 13 The structure shown.

[0059] Dry etching is used to etch the passivation layer 180 to remove the passivation layer 180 on the surface of the gate pad 300 and the source pad 410, as well as the passivation layer 180 with a set width along the first direction at the location of the cut track 100.

[0060] Remove photoresist 140 to form as Figure 14 The structure shown.

[0061] The semiconductor device fabrication method disclosed in this embodiment involves first partially etching the metal layer 130 of the chip using dry etching, and then etching the remaining metal layer 130 using wet etching. In the dry etching stage, the transmittance is optimized to <40%, prioritizing high-precision pattern definition within the low-temperature plasma region. Utilizing low ion energy and a limited reaction area, it eliminates photoresist 140 failure caused by heat accumulation and ion focusing damage to the metal top from the source. In the wet etching stage, the transmittance is optimized to <60%, selectively removing large metal areas using chemical solutions, avoiding plasma physical bombardment, and completely eliminating the risk of lateral drilling and bottom erosion. After the critical patterns are formed in one step during the dry etching stage, they are tightly isolated from the wet etching environment by the photoresist 140, achieving effective protection of the critical area patterns.

[0062] To achieve the above-described ideas, this embodiment also discloses a semiconductor device, comprising fabricated using the methods described above. The semiconductor device includes multiple chips. These chips may be memory chips, processor chips, image chips, power chips, or logic chips, or other types of chips; this application embodiment is not limited to these.

[0063] To achieve the above ideas, this embodiment also discloses an electronic device including the semiconductor device described in the foregoing embodiments.

[0064] Electronic devices can be any electronic device, such as a personal digital assistant, a handheld computer system, a tablet computer, or a digital camera.

[0065] The semiconductor device and electronic device provided in this embodiment belong to the same inventive concept as the semiconductor device fabrication method provided in this embodiment. Therefore, the semiconductor device and electronic device provided in this embodiment have at least all the advantages of the semiconductor device fabrication method provided in this embodiment, and can improve the reliability of the semiconductor device and electronic device.

[0066] In summary, the above embodiments have provided detailed descriptions of semiconductor devices and their fabrication methods, as well as different configurations of electronic devices. Of course, the above descriptions are only descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention in any way. The present invention includes, but is not limited to, the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for producing a semiconductor device, characterized by, include: A semiconductor device is provided, the semiconductor device comprising at least two chips, a dicing channel between two adjacent chips, each chip comprising a termination region and an active region, the termination region being disposed around the periphery of the active region, the active region being provided with a gate pad and a source pad, and the surface of the chip being covered with a metal layer; A dry etching process is used to etch the metal layer to remove the metal layer between the gate pad and the source pad, and at the same time remove part of the metal layer on the surface of the scribe line. A first trench is formed at the position between the gate pad and the source pad, and a second trench is formed at the position of the scribe line. The metal layer is etched using a wet etching process to remove the metal layer on the surface of the terminal area, and at the same time remove the remaining metal layer of the cutting channel to the reserved width, forming a third trench at the location of the cutting channel. A passivation layer is formed on the surface of the metal layer, the inner walls of the first trench and the third trench, and at the bottom. The passivation layer is etched to remove the passivation layer on the surface of the gate pad and the source pad, as well as the passivation layer with a predetermined width of the etch path.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The dry etching gas includes Cl2 and BCL3, with a flow rate ratio of 1:1 for Cl2 and BCL3, and the dry etching time is 250s to 400s.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The wet etching reagents include nitric acid, acetic acid and phosphoric acid, with nitric acid concentration of 3% to 4%, acetic acid concentration of 3% to 4% and phosphoric acid concentration of 70% to 80%.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of using wet etching to etch the metal layer, removing the metal layer on the surface of the terminal area, and simultaneously removing the remaining metal layer of the cutting path to the predetermined width includes: Photoresist is coated on the surface of the metal layer, and the first trench is filled with photoresist, while exposing the terminal area and the dicing track; Wet etching is used to remove the metal layer on the surface of the terminal area, and at the same time remove the remaining metal layer of the cutting channel to the reserved width.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The process of using wet etching to etch the metal layer, removing the metal layer on the surface of the terminal area, and simultaneously removing the remaining metal layer of the cutting path to the predetermined width includes: The metal layer is etched using a wet etching process to remove the metal layer on the surface of the terminal area. At the same time, the width of the remaining metal layer along the first direction is reserved to 10μm.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The passivation layer is etched using a dry etching process, and the gas used in the dry etching process includes fluorine-based gases.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching of the passivation layer to remove the passivation layer on the surface of the gate pad and source pad, as well as the passivation layer with a predetermined width of diced track, includes: The passivation layer is etched to remove the passivation layer on the surface of the gate pad and the source pad, while retaining the passivation layer with a width of 5 μm on one side of the dicing track along the first direction, and removing the passivation layer of the remaining portion of the dicing track.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a first dielectric layer and a second dielectric layer, the first dielectric layer covering the surface of the chip, the second dielectric layer covering the surface of the first dielectric layer, and the metal layer covering the surface of the second dielectric layer.

9. A semiconductor device, characterized in that, include: Prepared using the method described in any one of claims 1-8.

10. An electronic device, characterized in that, include: The semiconductor device as described in claim 9.

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