Semiconductor device and method of manufacturing a semiconductor device

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device, which can be applied to the technical field of semiconductor technology. The semiconductor device includes: a lower field effect transistor and an upper field effect transistor stacked in a vertical direction; the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked apart from each other in the vertical direction; a source / drain layer which is in contact with the channel layers on both sides of the plurality of channel layers in a first direction; a gate stack; a device separation layer between the upper field effect transistor and the lower field effect transistor; a contact layer which is in contact with a bottom surface of the source / drain layer of the lower field effect transistor away from the upper field effect transistor, extends from the bottom surface of the source / drain layer of the lower field effect transistor to an outer sidewall of the source / drain layer of the lower field effect transistor, and vertically extends on the outer sidewall of the source / drain layer of the lower field effect transistor to be electrically connected with the source / drain layer of the lower field effect transistor.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method of manufacturing a semiconductor device. Background Technology

[0002] With the continuous development of integrated circuit manufacturing process nodes and key technologies, NS-GAA FET (Nano-SheetGate-All-Around Field Effect Transistor) will replace the existing Fin FET (Fin Field-Effect Transistor) technology at 3 nm and below. Furthermore, 3D Stacked Field Effect Transistor (3DS FET), also known as CFET (Complementary Field Effect Transistor) or VFET (Vertical Field-Effect Transistor), will become the main technology route after the 1 nm node.

[0003] The main process methods for realizing 3DS FETs include sequential integration and self-aligned in-line (single-step) integration. The former is a simple process method, but it is limited by performance and cost, while the latter is a complex integration method with various process technology challenges and limitations on device performance. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a semiconductor device and a method for manufacturing a semiconductor device.

[0005] According to a first aspect of this disclosure, a semiconductor device is provided, comprising: a lower field-effect transistor and an upper field-effect transistor stacked in a vertical direction; each of the lower and upper field-effect transistors includes: a plurality of channel layers stacked at intervals from each other in a vertical direction; source / drain layers adjoining the channel layers on both sides of the plurality of channel layers in a first direction; and a gate stack extending in a second direction intersecting the first direction and at least partially surrounding the outer periphery of the channel layers; and an inter-device isolation layer between the upper and lower field-effect transistors; and a contact layer adjoining the source / drain layer of the lower field-effect transistor away from the bottom surface of the upper field-effect transistor and extending from the bottom surface of the source / drain layer of the lower field-effect transistor to the outer sidewall of the source / drain layer of the lower field-effect transistor, and further extending vertically on the outer sidewall of the source / drain layer of the lower field-effect transistor, thereby electrically connecting to the source / drain layer of the lower field-effect transistor.

[0006] A second aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: forming a stacked structure and a sacrificial gate intersecting the stacked structure on a substrate, wherein the sacrificial gate extends along a second direction, the stacked structure includes a lower stacked structure and an upper stacked structure, each of the lower and upper stacked structures including an alternately disposed channel layer and a sacrificial layer, the ends of the channel layers being exposed in a first direction intersecting the second direction; forming trenches in the substrate on both sides of the stacked structure in the first direction, and forming a first dielectric layer in the trenches, the thickness of the first dielectric layer being such that it covers the ends of the channel layers in the lower stacked structure while exposing the ends of the channel layers in the upper stacked structure; and forming upper source terminals on the first dielectric layer on both sides of the upper stacked structure in the first direction, which are connected to the ends of the channel layers in the upper stacked structure. / drain layer; replace the sacrificial gate and sacrificial layer with a gate stack; remove the substrate from the back side of the substrate and form a second dielectric layer in the space freed up by the removal of the substrate in the first dielectric layer; thin the first dielectric layer from the back side to expose the end of the channel layer in the lower stack structure in the first direction; form a lower source / drain layer on both sides of the lower stack structure in the first direction in the space freed up by the thinning of the first dielectric layer, which is connected to the end of the channel layer in the lower stack structure; form a contact layer electrically connected to the lower source / drain layer in the space where the lower source / drain layer is formed, the contact layer being attached to the bottom surface of the lower source / drain layer away from the upper source / drain layer and extending from the bottom surface of the lower source / drain layer to the outer wall of the lower source / drain layer, and further extending vertically on the outer wall of the lower field source / drain layer.

[0007] According to embodiments of this disclosure, a semiconductor device is provided. The contact layer of this semiconductor device is attached to the bottom surface of the source / drain layer of a lower field-effect transistor (FET), away from the bottom surface of the upper FET. Furthermore, the contact layer extends from the bottom surface of the source / drain layer of the lower FET to the outer sidewall of the source / drain layer of the lower FET, and further extends vertically on the outer sidewall of the source / drain layer of the lower FET, thereby increasing the contact area between the contact layer and the lower source / drain layer of the lower FET and improving the device performance of the lower FET. Attached Figure Description

[0008] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1A The illustration schematically shows a positional diagram of a first axial direction extending along a first direction in a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 1BThe schematic diagram illustrates the position of a second axial direction extending along a second direction in a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2A A schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown in the first axial direction.

[0012] Figure 2B A schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown along a second axis.

[0013] Figure 3A A schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure is shown in the first axial direction.

[0014] Figure 3B A schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure is shown along a second axis.

[0015] Figure 4A A schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure is shown in the first axial direction.

[0016] Figure 4B A schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure is shown along a second axis.

[0017] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0018] Figures 6A to 41A , Figures 6B to 41B This schematically illustrates the execution of the above. Figure 5 Cross-sectional views of the structure obtained from the middle part of the process at different axes. Detailed Implementation

[0019] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0022] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0023] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0024] In advanced 2nm and below technology nodes, single-integrated 3D CFETs typically employ back-contact technology to bring out and interconnect the bottom devices (i.e., the lower field-effect transistors) to alleviate the congestion problem of wiring routes for the top devices (i.e., the upper field-effect transistors). However, traditional back-contact technology relies on extremely high-precision extreme ultraviolet (EUV) lithography and requires correction of lithographic errors caused by wafer variations, resulting in significant alignment difficulties and affecting the process yield of device fabrication.

[0025] In some solutions, the substrate can be self-aligned and etched during the CFET front-side process. Specifically, the substrate can be etched using a sacrificial gate as a mask to form a trench with an extremely high aspect ratio. Then, a placeholder layer (PH) can be formed at this trench via epitaxial growth. Next, the CFET fabrication process can continue. For example, the lower source / drain layer of the lower field-effect transistor and the upper source / drain layer of the upper field-effect transistor can be formed via epitaxial growth, and a gate replacement process can be performed to replace the sacrificial gate with a gate stack. The substrate can be flipped, the PH removed, and a back contact can be self-aligned and formed in the space freed up by the removal of the PH. However, forming the PH and lower source / drain layer in this way, specifically through epitaxial growth in a trench with an extremely high aspect ratio, is quite challenging. Furthermore, this method limits the performance of the resulting CFET.

[0026] In view of the above, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, which can reduce the process difficulty compared to the method described above, and the manufactured CFET can have better performance. The following description is in conjunction with the accompanying drawings.

[0027] Figure 1A This schematically illustrates the position of a first axial direction extending along a first direction in a semiconductor device according to an embodiment of the present disclosure. Figure 1B The schematic diagram illustrates the position of a second axial direction extending along a second direction in a semiconductor device according to an embodiment of the present disclosure.

[0028] It should be pointed out that, Figure 1A and Figure 1B The perspective view of the semiconductor device is shown only schematically and is intended to illustrate the location of the cross-sectional views involved in other figures, and is not intended to illustrate a specific three-dimensional structure of the semiconductor device according to embodiments of the present disclosure. The structure of the semiconductor device according to embodiments of the present disclosure can be understood from the following cross-sectional views.

[0029] More specifically, Figure 1A and Figure 1B The diagram illustrates the main components of a semiconductor device, such as STI (shallow trench isolation), NS (nanosheets), spacers (sidewalls), metal (metal contacts), and gates, and their positional relationships. For example, a semiconductor device may include an upper field-effect transistor (FET) and a lower FET, each comprising a corresponding channel layer. Here, two nanosheets NS stacked at a distance from each other are used to illustrate the respective channel layers of the upper and lower FETs. Of course, the number of nanosheets NS is not limited to this. On both sides of the channel layer in a first direction, there are source / drain layers in contact with the channel layer (i.e., the nanosheets NS). In the perspective view, the source / drain layers may be obscured by the metal contacts (Metal). The gate stack may extend along a second direction intersecting (e.g., perpendicular to) the first direction to at least partially surround the outer periphery of the channel layer (i.e., the nanosheets NS). The sidewall spacers may be located on the sidewalls of the gate stack, between the gate stack and the source / drain layers and the metal contacts (Metal). Nanosheets (NS) can be formed on top of sub-Si, and the sub-Si can be surrounded by shallow trench isolation (STI).

[0030] According to embodiments of this disclosure, the first axial direction may extend along a first direction and be located in the middle of the nanosheet NS in a second direction; the second axial direction may extend along a second direction and be located in the middle of the gate stack in the first direction.

[0031] Figure 2A A schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown in the first axial direction. Figure 2B A schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is shown along a second axis.

[0032] like Figure 2A and Figure 2B As shown, the semiconductor device of this embodiment includes a lower field-effect transistor M1 and an upper field-effect transistor M2 stacked vertically. An inter-device isolation layer may be provided between the upper field-effect transistor M2 and the lower field-effect transistor M1 for electrical isolation.

[0033] It should be noted here that although the two field-effect transistors stacked on top of each other are referred to as the "upper" field-effect transistor and the "lower" field-effect transistor, "upper" and "lower" are only relative terms. For example, in Figure 2A and Figure 2B In the flipped state shown, the "upper" field-effect transistor is located at the bottom in the diagram, while the "lower" field-effect transistor is located at the top. Here, "upper" and "lower" are defined relative to the original substrate; a position closer to the original substrate can be "lower," while a position farther from the original substrate can be "upper." Similarly, "top," "bottom," or "top surface," "bottom surface" are defined in the same way. For example, a surface of a structure close to the original substrate can be called the "bottom surface," while a surface farther from the original substrate can be called the "top surface." This definition will become clearer when considered in conjunction with the manufacturing process described below.

[0034] The upper and lower field-effect transistors each include a channel layer 101, a gate stack, and a source / drain layer. The number of channel layers in each of the upper and lower field-effect transistors can be arbitrary and is not limited herein. For example, there can be multiple channel layers 101. The multiple channel layers 101 are stacked at intervals in the vertical direction. For example, the channel layers 101 can be nanosheets extending along a first direction and parallel to each other.

[0035] The gate stack extends in a second direction intersecting the first direction and at least partially surrounds the outer periphery of the channel layer. The gate stack may include a gate dielectric layer 122, a work function layer on the gate dielectric layer 122 (e.g., the P-type work function layer 123a of the lower field-effect transistor and the N-type work function layer 123b of the upper field-effect transistor shown in the figure), and a conductive layer 126 on the work function layer. The gate dielectric layer 122 may include a high-κ dielectric material, where κ represents the dielectric constant. High-κ dielectric materials include HfO2 and HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO xThe gate stack may contain one or a combination of Ta₂O₅ or La₂O₃. The work function layer may include titanium nitride, etc. The conductive layer 126 may include a metal such as tungsten, etc. In addition, gate sidewalls 110 and inner sidewalls 113 may be formed on the opposite sidewalls of the gate stack in the first direction. The inner sidewall 113 may be located between the gate stack and the source / drain layers.

[0036] The source / drain layers can be located on opposite sides of multiple channel layers in a first direction and are connected to the multiple channel layers. For example, the source / drain layers may include an upper source / drain layer 119 of an upper field-effect transistor and a lower source / drain layer 117 of a lower field-effect transistor. For example, the upper field-effect transistor may be an N-type field-effect transistor. The material of the upper source / drain layer 119 of the upper field-effect transistor may include SiC:P (phosphorus-doped silicon carbide). The lower field-effect transistor may be a P-type field-effect transistor. The material of the lower source / drain layer 117 of the lower field-effect transistor may include SiGe:B (boron-doped silicon germanium). Furthermore, the embodiments of this disclosure are not limited thereto. In other embodiments of this disclosure, the lower source / drain layer 117 of the lower field-effect transistor may also include an all-metal silicide. However, the embodiments of this disclosure are not limited thereto. In other embodiments of this disclosure, the upper field-effect transistor may also be a P-type field-effect transistor, and the lower field-effect transistor may also be an N-type field-effect transistor. This disclosure does not limit this.

[0037] Furthermore, such as Figure 2A As shown, the semiconductor device of this disclosure also includes a contact layer 127 connected to the upper source / drain layer 119 and a contact layer 130 connected to the lower source / drain layer 117 of the lower field-effect transistor. The contact layer 127 may be in the form of a contact plug, extending vertically within the interlayer dielectric layer 120. The contact layer 130 may be attached to the bottom surface of the lower source / drain layer 117 away from the upper source / drain layer 119 (e.g., the bottom surface of the lower source / drain layer 117 on...). Figure 2A (The upper surface). Furthermore, the contact layer 130 extends from the bottom surface of the lower source / drain layer 117 to the outer sidewall of the lower source / drain layer 117, and further extends vertically on the outer sidewall. This increases the contact area between the contact layer 130 and the lower source / drain layer 117 of the lower field-effect transistor, reducing contact resistance and improving the device performance of the lower field-effect transistor.

[0038] An inter-device isolation layer may be disposed between the lower field-effect transistor M1 and the upper field-effect transistor M2. In this embodiment, the inter-device isolation layer may include a gate isolation portion 114 between the gate stack of the upper field-effect transistor and the gate stack of the lower field-effect transistor, and a source / drain isolation portion 140 between the upper source / drain layer 119 of the upper field-effect transistor and the lower source / drain layer 117 of the lower field-effect transistor. The material of the source / drain isolation portion 140 may include at least one of dielectric materials such as SiO2, SiNx, SiNO, SiCO, SiCNO, SiCN, and spinel structure materials.

[0039] According to some embodiments of this disclosure, on at least one side of the plurality of channel layers in a first direction, the contact layer 130 may further extend through the inter-device isolation layer (more specifically, the source / drain isolation portion 140) to electrically connect to the upper source / drain layer 119 of the upper field-effect transistor. For example, as Figure 2A As shown, for the channel layer 101 of the upper field-effect transistor and the lower field-effect transistor, on one side of the first direction (e.g.) Figure 2A (On the right side of the image), contact layer 130 extends through the inter-device isolation layer (more specifically, source / drain isolation portion 140) to electrically connect to the upper source / drain layer 119 of the upper field-effect transistor. Therefore, it is possible to avoid using more manufacturing processes in the back-side interconnect process of related technologies to form the contact between the lower source / drain layer 117 and the upper source / drain layer 119, saving resources required for manufacturing semiconductor devices. Of course, whether the lower source / drain layer 117 and the upper source / drain layer 119 are electrically connected (through contact layer 130) depends on the circuit layout and is not necessarily as described above. Figure 2A They are electrically connected to each other as shown.

[0040] Furthermore, the width of the lower source / drain layer 117 in the first direction can be reduced (relative to the upper source / drain layer 119), so that the outer wall of the lower source / drain layer 117 in the first direction is recessed relative to the outer wall of the upper source / drain layer 119 on the same side in the first direction. The outer wall of the portion of the contact layer 130 extending on the outer wall of the lower source / drain layer 117 (the side wall away from the channel layer 101) can be substantially aligned in the vertical direction with the outer wall of the upper source / drain layer 119 on the same side (the side wall away from the channel layer 101).

[0041] Figure 3A A schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure is shown in a first direction.

[0042] Figure 3B A schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure is shown in a second direction.

[0043] like Figure 3A and Figure 3B As shown, at least one surface of the lower source / drain layer 117 and the upper source / drain layer 119, such as the surface near the inter-device isolation layer, may have a curved profile, or a facet morphology. This is because the lower source / drain layer 117 and the upper source / drain layer 119 are grown from corresponding channel layers. A space is defined between such a surface and the inter-device isolation layer. Of course, other surfaces of the lower source / drain layer 117 and the upper source / drain layer 119 may also exhibit similar facet morphologies. Furthermore, in this embodiment, the contact layer 130 has a portion between the lower source / drain layer 117 and the inter-device isolation layer. More specifically, the contact layer 130 may extend into the space between the curved surface of the lower source / drain layer 117 and the inter-device isolation layer. In this way, the contact area between the lower source / drain layer 117 and the contact layer 130 can be increased, thereby improving the performance of the semiconductor device.

[0044] The contact layer 130 is formed between the lower source / drain layer 117 and the inter-device isolation layer in the lower field-effect transistor, and the contact layer 130 may surround the surface of the lower source / drain layer 117 of the lower field-effect transistor near the inter-device isolation layer. Figure 6A The lower middle surface, which, according to the above definition, can be called the top surface, and the side facing away from the inter-device isolation layer ( Figure 6A The upper middle surface (which, according to the above definition, can be called the bottom surface) and the sidewall in the second direction ( Figure 6A The front and back surfaces of the paper.

[0045] Depending on the growth process of the lower source / drain layer and the etching process that may be performed after growth, the space between the lower source / drain layer 117 and the source / drain isolation portion 140 may not exist, that is, the lower source / drain layer 117 and the source / drain isolation portion 140 may be connected to each other.

[0046] In addition, the interlayer dielectric layer 120 can fill the space between the curved surface of the upper source / drain layer 119 of the upper field-effect transistor and the source / drain isolation portion 140, while the contact layer 127 may not extend into this space.

[0047] This disclosure is not limited to the embodiments described herein. In other embodiments of this disclosure, on one side of the plurality of channel layers 101 in the first direction, an active / drain isolation portion 140 is formed between the lower source / drain layer 117 of the lower field-effect transistor and the upper source / drain layer 119 of the upper field-effect transistor. On the other side of the plurality of channel layers in the first direction, the lower source / drain layer 117 is connected to the upper source / drain layer 119 of the upper field-effect transistor. This will be explained below through... Figure 4A and Figure 4B Further explanation is needed.

[0048] Figure 4A A schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure is shown in a first direction.

[0049] Figure 4B A schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure is shown in a second direction.

[0050] like Figure 4A and Figure 4B As shown, on one side of the plurality of channel layers 101 in the first direction (e.g.) Figure 4A On the left side of the upper field-effect transistor, an active / drain isolation portion 140 is formed between the lower source / drain layer 117a of the lower field-effect transistor and the upper source / drain layer 119 of the upper field-effect transistor. On the other side of the plurality of channel layers 101 in the first direction (e.g., on the left side), an active / drain isolation portion 140 is formed between the lower source / drain layer 117a of the lower field-effect transistor and the upper source / drain layer 119 of the upper field-effect transistor. Figure 4A (On the right side of the image), the lower source / drain layer of the lower field-effect transistor is connected to the upper source / drain layer 119 of the upper field-effect transistor. In this example, the lower source / drain layer of the lower field-effect transistor may include a first portion 117b1 and a second portion 117b2. The first portion 117b1 may be connected to a sidewall extending in the vertical direction and connected to the plurality of channel layers 101 in the first direction, and the second portion 117b2 may extend laterally from the first portion 117b1 on the upper source / drain layer 119 of the upper field-effect transistor. Therefore, the need for more manufacturing processes to form the contact between the lower source / drain layer and the upper source / drain layer 119 through the back interconnect process in the related art can be avoided, saving the resources required to manufacture semiconductor devices.

[0051] The method for manufacturing semiconductor devices disclosed herein will be described below.

[0052] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0053] like Figure 5 As shown, this embodiment includes operations S510 to S580.

[0054] In operation S510, a stacked structure and a sacrificial gate intersecting the stacked structure are formed on the substrate.

[0055] According to an embodiment of the present invention, the sacrificial gate extends along a second direction, and the stacked structure includes a lower stacked structure and an upper stacked structure. Each of the lower and upper stacked structures includes alternately arranged channel layers and sacrificial layers, with the ends of the channel layers exposed in a first direction intersecting the second direction. For definitions of the first and second directions, please refer to the description in the above embodiments.

[0056] In operation S520, trenches are formed in the substrate on both sides of the stacked structure in the first direction, and a first dielectric layer is formed in the trenches. The thickness of the first dielectric layer is such that it covers the ends of the channel layers in the lower stacked structure, while exposing the ends of the channel layers in the upper stacked structure.

[0057] In operation S530, an upper source / drain layer is formed on the first dielectric layer on both sides of the upper stacked structure in the first direction, which is connected to the end of the channel layer in the upper stacked structure.

[0058] In operation S540, the sacrificial gate and sacrificial layer are replaced with a gate stack.

[0059] In operation S550, the substrate is removed from the back side of the substrate, and a second dielectric layer is formed in the space freed up in the first dielectric layer due to the removal of the substrate.

[0060] In operation S560, the first dielectric layer is thinned from the back side to expose the end of the channel layer in the lower stacked structure in the first direction.

[0061] In operation S570, in the space freed up due to the thinning of the first dielectric layer, a lower source / drain layer is formed on both sides of the lower stacked structure in the first direction, which is connected to the end of the channel layer in the lower stacked structure.

[0062] In operation S580, a contact layer electrically connected to the lower source / drain layer is formed in the space where the lower source / drain layer is formed.

[0063] To better understand the method for manufacturing semiconductor devices disclosed herein, the following is based on cross-sectional views along various axes during the manufacturing process of the semiconductor device, namely... Figures 6A to 41A , Figures 6B to 41B The following will describe the content of the embodiments disclosed herein. It should be noted that, as shown below... Figures 6A to 41A , Figures 6B to 41B In cases where the numbers in the titles of multiple figures are the same, the fabrication processes corresponding to those figures are the same. Conversely, if the numbers in the titles of multiple figures are the same but the letters differ, the fabrication processes corresponding to those figures are the same, but the axial directions they represent are different. For example, Figure 14A and Figure 14B These are cross-sectional views of the same preparation process along two axes.

[0064] Figures 6A to 35A , Figures 6B to 35B Corresponding use Figure 5 Manufacturing by the method shown Figure 3A and Figure 3B The diagram shows cross-sectional views of the structure obtained during the process of the device shown, along different axes.

[0065] Figures 6A to 33A, Figures 6B to 33B , Figures 36A-38A , Figures 36B-38B Corresponding use Figure 5 Manufacturing by the method shown Figure 2A and Figure 2B The diagram shows cross-sectional views of the structure obtained during the process of the device shown, along different axes.

[0066] Figures 6A to 33A , Figures 6B to 33B , Figures 39A to 41A , Figures 39B to 41B Corresponding use Figure 5 Manufacturing by the method shown Figure 4A and Figure 4B The diagram shows cross-sectional views of the structure obtained during the process of the device shown, along different axes.

[0067] refer to Figure 6A , Figure 7A , Figure 6B and Figure 7B A substrate SUB is provided. The substrate SUB may include a silicon wafer, a silicon-on-insulator (SOI) substrate, etc. Here, a silicon wafer is used as an example for description. The substrate SUB may be subjected to pretreatment operations such as well lithography, ion implantation, annealing, and cleaning in sequence. Then, a lower stacked structure, an intermediate layer 103, and an upper stacked structure are sequentially formed on the pretreated substrate SUB using an epitaxial growth process. The lower stacked structure and the upper stacked structure each include an alternately arranged channel layer 101 and a sacrificial layer 102. The channel layer 101 may include a semiconductor material, such as silicon. According to an embodiment, the channel layer 101 may be undoped or lightly doped to adjust device performance, such as threshold voltage. The sacrificial layer 102 and the intermediate layer 103 may include materials with etching selectivity relative to the channel layer 101, such as SiGe.

[0068] refer to Figure 8A and Figure 8B Sidewalls 104 can be formed. The material of sidewalls 104 can be silicon nitride, etc. In this embodiment, a mandrel 105 can be formed on the upper stacked structure, and the mandrel 105 can be patterned using a photolithography process to obtain a linear pattern extending along a first direction. The material of the mandrel 105 can be polycrystalline silicon or amorphous silicon, etc. Sidewalls 104 are formed on the sidewalls of the linear patterned mandrel 105, and the patterned mandrel 105 is removed after the sidewalls 104 are formed, so that only the sidewalls 104 remain on the stacked structure, thereby completing the fabrication of the sidewalls 104.

[0069] Based on this, refer to Figure 9A and Figure 9BThe sidewall 104 can be used as an etching mask, and an anisotropic etching process, such as vertical reactive ion etching (RIE), can be used to etch the upper stacked structure, the intermediate layer 103, the lower stacked structure, and the substrate SUB to form fins extending along a first direction on the substrate SUB. Due to the formation of the fins, grooves distributed on both sides of the fins in a second direction are formed in the substrate.

[0070] In this example, the sidewall pattern transfer (SIT) process is used to define the fin pattern. However, this disclosure is not limited to this. Other patterning schemes can be used to define the fin pattern.

[0071] refer to Figure 10A and Figure 10B In the trenches of the substrate, a dielectric material such as silicon oxide can be deposited to form shallow trench isolation (STI) 106.

[0072] refer to Figure 11A , Figure 12A , Figure 11B and Figure 12B A sacrificial gate intersecting with the fins can be formed on the STI106 using processes such as thermal oxidation and chemical vapor deposition. The sacrificial gate can consist of a gate oxide layer 107, a polysilicon layer 108, and a hard mask layer 109, arranged sequentially from bottom to top. The hard mask layer 109 can be made of nitride, carbide, or organic materials. Based on this, a gate sidewall 110 can be formed on the sidewalls of the sacrificial gate using a sidewall formation process. The material of this gate sidewall can be SiCNO, etc.

[0073] refer to Figure 13A , Figure 13B , Figure 14A as well as Figure 14B The sacrificial gate and gate sidewall 110 can be used as etching masks, for example, by anisotropic etching of the upper stacked structure, the middle layer and the lower stacked structure through a vertical RIE, so that the patterned lower stacked structure, the middle layer and the upper stacked structure have side surfaces exposed in the first direction.

[0074] Because the sacrificial layer 102 and the intermediate layer 103 (in this example, SiGe) are etch-selective with respect to the substrate SUB and the channel layer 101 (in this example, Si), selective etching of the sacrificial layer 102 and the intermediate layer 103 can be performed via the exposed side surfaces described above. During selective etching, the etching rate of the intermediate layer 103 is higher than that of the sacrificial layer 102, such that upon completion of selective etching, the intermediate layer 103 is removed while the sacrificial layer 102 is retained, with its end in the first direction recessed relative to the channel layer 101. In one embodiment of this disclosure, the intermediate layer and the sacrificial layer are made of the same material, but the proportions of their constituent elements differ, such that the etching rate of the intermediate layer is higher than that of the sacrificial layer. Based on this, different degrees of etching of the intermediate layer 103 and the sacrificial layer 102 can be achieved in the same etching process. For example, the etching selectivity ratio between the intermediate layer 103 and the sacrificial layer 102 is greater than 5:1. For example, both the sacrificial layer 102 and the intermediate layer 103 are made of SiGe. By setting the Ge content in the sacrificial layer 102 to be different from the Ge content in the intermediate layer 103, the aforementioned selective etching can be achieved, and the etching rate of the intermediate layer can be higher than that of the sacrificial layer. For example, the Ge content in the intermediate layer 103 is set to be higher than that in the sacrificial layer 102. For example, the intermediate layer 103 is SiGe with a Ge content of 50% (atomic percentage), while the sacrificial layer 102 is SiGe with a Ge content of 30% (atomic percentage). Based on this, after the intermediate layer 103 is etched, an opening 112 is formed, and the recess of the end of the sacrificial layer 102 in the first horizontal direction relative to the channel layer 101 is used as the opening 111.

[0075] refer to Figure 15A and Figure 15B The space freed up in the fin due to the selective etching of the sacrificial layer 102 and the intermediate layer 103 is filled with a dielectric material. The dielectric material can be the same as the material of the gate sidewall 110, such as SiCNO. The portion of the dielectric material filling at the end of the sacrificial layer 102 serves as the inner sidewall 113, and the portion of the dielectric material filling between the lower and upper stacked structures serves as the gate isolation portion 114 in the inter-device isolation layer. The inner sidewall 113 can have substantially the same thickness as the gate sidewall 110. Figure 15A (Scale in the first direction).

[0076] refer to Figure 16A and Figure 16BThe sacrificial gate and gate sidewalls can be used as etching masks, for example, by anisotropic etching of the substrate SUB through a vertical RIE to form trenches. These trenches are self-aligned to opposite sides of the gate stack in the first direction, and specifically, self-aligned to opposite sides of the channel layer 110 in the lower stack structure in the first direction. The etching depth must meet the back contact depth to allow for subsequent formation of the source / drain layers of the lower field-effect transistor.

[0077] refer to Figure 17A and Figure 17B An insulating dielectric material, such as SiO2, SiNx, or SiOC, is deposited in the trenches obtained above. This is followed by planarization using chemical mechanical polishing and etching back, for example, by a vertical RIE (Reverse Etching) to form a first dielectric layer 140'. The thickness of the first dielectric layer 140' is sufficient to cover the ends of the channel layers in the lower stacked structure while exposing the ends of the channel layers in the upper stacked structure. For example, after etching back, the top surface of the first dielectric layer 140' can be located at the height of the gate isolation portion 114, for example, between the top and bottom surfaces of the gate isolation portion 114. Similarly, the first dielectric layer 140' is self-aligned to opposite sides of the gate stack in the first direction, particularly to opposite sides of the channel layer 110 in the lower stacked structure in the first direction. The first dielectric layer 140' can serve as a placeholder layer for a self-aligned source / drain contact layer.

[0078] refer to Figure 18A and Figure 18B On the exposed sidewalls of the channel layer 101, source / drain materials are epitaxially grown and in-situ doped to form an upper source / drain layer 119 that connects to the end of the channel layer in the upper stacked structure. Subsequently, a rapid thermal annealing process is used to activate the source / drain impurities in the upper source / drain layer 119. As described above, the epitaxial growth can be selective epitaxial growth, using the exposed sidewalls of the channel layer 101 as seeds, and can form faceted morphologies.

[0079] refer to Figure 19A and Figure 19B A dielectric material, such as silicon oxide, is deposited and planarized to form an interlayer dielectric layer 120. Planarization can remove the mask layer 109 in the sacrificial gate to expose the polysilicon layer 108. For example, planarization can be performed by chemical mechanical polishing (CMP), and CMP can stop at the polysilicon layer 108. The dielectric material of the interlayer dielectric layer 120 can enter the void between the upper source / drain layer 119 and the first dielectric layer 140' (if present, for example, due to facet topography).

[0080] refer to Figures 20A-23A , Figures 20B to 23BBy selective etching, the sacrificial gate and sacrificial layer 102 are removed, thereby forming cavities 121_1 exposed by etching at the original locations of the polysilicon layer 108 and sacrificial layer 102, respectively, inside the gate sidewalls 110 and inner sidewalls 113. Gate stacks surrounding the channel layer 101 are formed within cavities 121_1 and 121_2. These gate stacks include a gate dielectric layer 122 and a P-type work function layer 123a. The gate dielectric layer 122 can be made of a high-κ dielectric material, where κ represents the dielectric constant. High-κ dielectric materials include HfO2 and HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x It can be one or a combination of several of Ta2O5 or La2O3. The material of the p-type work function layer 123a can be titanium nitride, etc.

[0081] refer to Figures 24A-26A and Figures 24B-26B A protective layer 124 is formed on the substrate SUB, and the protective layer 124 is etched back to the top surface located between the top and bottom surfaces of the inter-device isolation layer 114 to shield the cavity for the lower device (which will be subsequently formed into the lower field-effect transistor). The protective layer 124 protects the P-type work function layer 123a located in the cavity below the gate isolation portion 114, while exposing the P-type work function layer 123a located in the cavity above the inter-device isolation layer 114.

[0082] The P-type work function layer 123a above the gate isolation portion 114 is etched using a selective etching process. Then, an N-type work function layer 123b is formed on the gate dielectric layer 122 to facilitate the formation of different gate stacks surrounding the channel layer 101 above and below the gate isolation portion 114. The channel layer 101, gate stack, and source / drain layer 119 above the gate isolation portion 114 constitute an N-type field-effect transistor, and the channel layer 101, gate stack, and source / drain layer 117 above the gate isolation portion 114 constitute a P-type field-effect transistor, thereby obtaining a stacked field-effect transistor.

[0083] It should be understood that the above is only one embodiment of this disclosure. In the preparation process of other embodiments of this disclosure, N-type field-effect transistors or P-type field-effect transistors can be formed as needed by changing the doping type of the source / drain layers and forming corresponding work function layers. For example, the upper N-type field-effect transistor can be formed as a P-type field-effect transistor, and / or the lower P-type field-effect transistor can be formed as an N-type field-effect transistor.

[0084] After fabricating the aforementioned N-type and P-type field-effect transistors, the protective layer 124 is removed, thereby releasing the cavity located below the gate isolation portion 114. Then, conductive material is deposited in all cavities 121_1 and all cavities 121_2. The deposited conductive material can then be planarized to form a conductive layer 126, thus completing the fabrication of the gate stack. The conductive material in this embodiment may include tungsten or the like.

[0085] refer to Figure 27A and Figure 27B The interlayer dielectric layer 120 can be raised by further depositing dielectric materials such as silicon oxide to facilitate the fabrication of various interconnect structures such as contact plugs.

[0086] refer to Figure 28A and Figure 28B Contact holes can be formed in the interlayer dielectric layer 120, and conductive material can be filled into the contact holes to form contact plugs 127 that are in contact with the upper source / drain layer 119. In the figure, the top surface of the interlayer dielectric layer 120 is shown to be higher than the top surface of the contact plugs 127, which is achieved by further raising the interlayer dielectric layer 120 after the contact plugs 127 are formed so that interconnects can be formed on the contact plugs 127.

[0087] refer to Figure 29A , Figure 30A , Figure 29B and Figure 30B The device is inverted, and a carrier wafer is bonded to the bottom of the device after inversion. The substrate SUB is thinned to around STI 106 and the first dielectric layer 140' is exposed.

[0088] refer to Figure 31A , Figure 32A , Figure 31B and Figure 32B The substrate SUB is selectively etched away until the underlying gate stack is exposed, and the space released by removing the substrate SUB is filled with a dielectric material such as oxide to form a second dielectric layer 150. Figure 32B In the diagram, STI 106 and the second dielectric layer 150 (both of which are oxides in this example) are shown as "106".

[0089] refer to Figure 33A and Figure 33B The first dielectric layer 140' is thinned from the back side to expose the end of the channel layer in the lower stack structure in the first direction. The thinned first dielectric layer 140' serves as a source / drain isolation portion 140. The space freed up by the thinning of the first dielectric layer 140' (originally occupied by the first dielectric layer 140') is self-aligned to opposite sides of the gate stack in the first direction, and in particular, self-aligned to opposite sides of the channel layer 110 in the lower stack structure in the first direction.

[0090] refer to Figure 34A , Figure 35A , Figure 34B , Figure 35B In the released space, using the exposed end of the channel layer in the lower stacked structure in the first direction as a seed, an epitaxial layer is epitaxially grown and in-situ doped to form a lower source / drain layer 117. Epitaxial growth can be performed at a temperature below 600°C. A cavity 160 exposing the top surface of the lower source / drain layer 117 can be formed between the lower source / drain layer 117 and the thinned first dielectric layer, i.e., the source / drain isolation portion 140. Conductive material can be filled into the space where the lower source / drain layer 117 is formed to form a contact layer 130, thereby obtaining... Figure 3A and Figure 3B The semiconductor device shown. The conductive material filling the space, i.e., the contact layer 130, is self-aligned with the lower source / drain layer 117 formed in the space. The conductive material can fill the cavity 160 and be formed on the bottom surface of the lower source / drain layer 117 and the sidewalls in the second direction, so that the contact layer 130 can be in electrical contact with the top surface, bottom surface, and sidewalls in the second direction of the lower source / drain layer 117.

[0091] refer to Figures 36A-38A , Figures 36B-38B Using the exposed end of the channel layer in the lower stacked structure in the first direction as a seed, a lower source / drain layer 117 is grown using an epitaxial growth process (e.g., low-temperature epitaxy). In this example, the lower source / drain layer 117 may be smaller than the upper source / drain layer 119, and therefore may be recessed relative to the upper source / drain layer 119 in the first direction. In this example, the lower source / drain layer 117 may also have a faceted topography, although not shown. The lower source / drain layer 117 on one side in the first direction can be masked by, for example, photoresist 170. Then, on at least one side in the first direction (e.g., ... Figure 37A On the side where the photoresist 170 is not formed, using the lower source / drain layer 117 as a mask, the first dielectric layer (source / drain isolation portion 140) is selectively etched using, for example, a vertical RIE (Residual Etching). This etching can also etch an interlayer dielectric layer 120 (material of the interlayer dielectric layer 120 may enter the cavity) that may exist in the cavity between the upper source / drain layer 119 and the source / drain isolation portion 140, thus exposing a portion of the upper source / drain layer 119 on that side. After removing the photoresist, a contact layer 130 is formed on the exposed portions of the lower source / drain layer 117 and the upper source / drain layer 119. Therefore, on at least one side of the plurality of channel layers in the first direction, the contact layer 130 can extend through the lower source / drain layer 117 to electrically connect to the upper source / drain layer 119. This results in... Figure 2A and Figure 2BThe semiconductor device shown.

[0092] refer to Figures 39A to 41A , Figures 39B to 41B On the first side of the lower stacked structure in the first direction, photoresist 170 can be formed to shield the first dielectric layer (source / drain isolation portion 140) on that side, while on the second side of the first direction, the first dielectric layer (source / drain isolation portion 140) is exposed. The exposed first dielectric layer can be selectively etched, and the interlayer dielectric layer 120 that may exist in the cavity between the upper source / drain layer 119b and the source / drain isolation portion 140 can be etched to expose the upper source / drain layer 119b on that side, after which the photoresist can be removed. Thus, on the first side of the lower stacked structure in the first direction, a thinned first dielectric layer (source / drain isolation portion 140) is retained to cover the upper source / drain layer 119a on that side, while on the second side of the first direction, the upper source / drain layer 119b on that side is exposed. Subsequently, using the exposed upper source / drain layer 119b and the exposed ends of the channel layer in the lower stacked structure in the first direction as seeds, an epitaxial layer is epitaxially grown to form the first portion 117b1 and the second portion 117b2 of the lower source / drain layer, and a contact layer 130 is formed. The epitaxial layer is formed as a thin layer, and the formation of the lower source / drain layer also includes: completely forming the epitaxial layer as an all-metal silicide through a silicide treatment. Thus, as shown... Figure 4A and Figure 4B The semiconductor device shown.

[0093] According to embodiments of this disclosure, an upper field-effect transistor and a lower field-effect transistor stacked in a vertical direction are provided. On the back side of the device, a source / drain isolation portion is formed by self-aligning the placeholder layer of the self-aligned source / drain contact layer through thinning, and the lower source / drain layer is grown in the space freed up by low-temperature epitaxy, alleviating the high aspect ratio source / drain epitaxial challenge of the lower field-effect transistor. Furthermore, forming a self-aligned source / drain contact layer in the space freed up by the thinning of the placeholder layer of the self-aligned source / drain contact layer reduces the alignment error of the photolithography source / drain caused by wafer bonding. The process according to embodiments of this disclosure is compatible with mainstream CFET integration processes and can be applied to back contact and dielectric isolation technologies for various semiconductor devices such as FinFET, FDSOI (Fully Depleted Silicon on Insulator), and GAAFET.

[0094] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Lower and upper field-effect transistors stacked vertically; The lower field-effect transistor and the upper field-effect transistor each include: a plurality of channel layers stacked at intervals in a vertical direction; source / drain layers adjoining the channel layers on both sides in a first direction; and a gate stack extending in a second direction intersecting the first direction and at least partially surrounding the outer periphery of the channel layers; and Inter-device isolation layer between the lower field-effect transistor and the upper field-effect transistor; and A contact layer is attached to the source / drain layer of the lower field-effect transistor away from the bottom surface of the upper field-effect transistor, and extends from the bottom surface of the source / drain layer of the lower field-effect transistor to the outer sidewall of the source / drain layer of the lower field-effect transistor, and further extends vertically on the outer sidewall of the source / drain layer of the lower field-effect transistor, thereby being electrically connected to the source / drain layer of the lower field-effect transistor; The contact layer further includes a portion between the source / drain layer of the lower field-effect transistor and the device isolation layer, and / or, the outer wall of the source / drain layer of the lower field-effect transistor in the first direction is recessed in the first direction relative to the outer wall of the source / drain layer of the upper field-effect transistor on the same side in the first direction, and / or, the outer wall of the portion of the contact layer extending on the outer wall of the source / drain layer of the lower field-effect transistor is aligned vertically with the outer wall of the source / drain layer of the upper field-effect transistor on the same side.

2. The semiconductor device according to claim 1, characterized in that, The contact layer extends through the inter-device isolation layer to electrically connect to the source / drain layer of the upper field-effect transistor.

3. The semiconductor device according to claim 1, characterized in that, The device isolation layer includes a source / drain isolation portion between the source / drain layer of the upper field-effect transistor and the source / drain layer of the lower field-effect transistor; The portion of the contact layer is formed between the source / drain layer of the lower field-effect transistor and the source / drain isolation portion, and the contact layer surrounds the surface of the source / drain layer of the lower field-effect transistor near the device isolation layer, the surface opposite to the device isolation layer, and the sidewall in the second direction.

4. The semiconductor device according to claim 3, characterized in that, The source / drain isolation section is made of at least one of SiO2, SiNx, SiNO, SiCO, SiCNO, SiCN, and spinel-structured materials.

5. The semiconductor device according to claim 1, characterized in that, On one side of the plurality of channel layers in the first direction, an inter-device isolation layer is formed between the source / drain layer of the lower field-effect transistor and the source / drain layer of the upper field-effect transistor; On the other side of the plurality of channel layers in the first direction, the source / drain layer of the lower field-effect transistor is connected to the source / drain layer of the upper field-effect transistor.

6. The semiconductor device according to claim 5, characterized in that, On the other side of the plurality of channel layers in the first direction, the source / drain layer of the lower field-effect transistor includes a first portion and a second portion; wherein, The first portion extends in the vertical direction and is in contact with the sidewalls of the plurality of channel layers in the first direction; The second portion extends laterally from the first portion on the source / drain layer of the upper field-effect transistor.

7. The semiconductor device according to claim 2, characterized in that, The source / drain layers of the lower field-effect transistor consist of all-metal silicide.

8. A method for manufacturing a semiconductor device, characterized in that, The method includes: A stacked structure and a sacrificial gate intersecting the stacked structure are formed on a substrate, wherein the sacrificial gate extends along a second direction, the stacked structure includes a lower stacked structure and an upper stacked structure, the lower stacked structure and the upper stacked structure each include an alternately arranged channel layer and a sacrificial layer, and the end of the channel layer is exposed in a first direction intersecting the second direction; Trenches are formed in the substrate on both sides of the stacked structure in the first direction, and a first dielectric layer is formed in the trenches. The thickness of the first dielectric layer is such that it covers the ends of the channel layers in the lower stacked structure, while exposing the ends of the channel layers in the upper stacked structure. An upper source / drain layer is formed on the first dielectric layer on both sides of the upper stacked structure in the first direction, which is connected to the end of the channel layer in the upper stacked structure; Replace the sacrificial gate and the sacrificial layer with a gate stack; The substrate is removed from the back side of the substrate, and a second dielectric layer is formed in the space freed up in the first dielectric layer due to the removal of the substrate; The first dielectric layer is thinned from the back side to expose the end of the channel layer in the lower stack structure in the first direction; In the space freed up due to the thinning of the first dielectric layer, a lower source / drain layer is formed on both sides of the lower stacked structure in the first direction, which is connected to the end of the channel layer in the lower stacked structure. A contact layer electrically connected to the lower source / drain layer is formed in the space where the lower source / drain layer is formed. The contact layer is attached to the bottom surface of the lower source / drain layer away from the upper source / drain layer and extends from the bottom surface of the lower source / drain layer to the outer sidewall of the lower source / drain layer, and further extends vertically on the outer sidewall of the lower source / drain layer.

9. The method according to claim 8, characterized in that, Forming the lower source / drain layer includes: using the exposed end of the channel layer in the lower stacked structure in the first direction as a seed, epitaxially growing an epitaxial layer to form the lower source / drain layer.

10. The method according to claim 9, characterized in that, The epitaxial growth was carried out at a temperature below 600°C.

11. The method according to claim 9, characterized in that, Thinning the first dielectric layer involves retaining the thinned first dielectric layer on a first side of the lower stacked structure in the first direction to cover the upper source / drain layer, while exposing the upper source / drain layer on a second side in the first direction. The formation of the lower source / drain layer includes: Using the ends of the upper source / drain layer and the channel layer in the lower stack structure exposed on the second side that are exposed in the first direction as seeds, the epitaxial layer is grown epitaxially.

12. The method according to claim 9, characterized in that, The epitaxial layer is formed as a thin layer. The formation of the lower source / drain layer also includes: forming the epitaxial layer completely as an all-metal silicide through silicide treatment.

13. The method according to claim 8 or 9, characterized in that, A cavity is formed between the lower source / drain layer and the thinned first dielectric layer, exposing the surface of the lower source / drain layer near the first dielectric layer. The contact layer that forms an electrical contact with the lower source / drain layer comprises: filling the space with a conductive material, wherein the conductive material enters the cavity, thereby forming a contact layer that makes electrical contact with the surface of the lower source / drain layer near the first dielectric layer, the surface opposite to the first dielectric layer, and the sidewall in the second direction.

14. The method according to claim 13, characterized in that, The contact layer forming electrical contact with the lower source / drain layer includes: On at least one side of the lower stacked structure in the first direction, the first dielectric layer is etched to expose a portion of the upper source / drain layer on that side; A contact layer is formed on the exposed portions of the lower source / drain layer and the upper source / drain layer, such that the contact layer is electrically connected to the upper source / drain layer and the lower source / drain layer.

15. The method according to claim 14, characterized in that, The lower source / drain layer is formed to be recessed relative to the upper source / drain layer in the first direction. Etching the first dielectric layer includes: The first dielectric layer is etched using the lower source / drain layer as a mask.

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