Method of fabricating a semiconductor structure

Abstract

This invention discloses a method for fabricating a semiconductor structure, including providing a computing system; inputting a photomask pattern having a first stepped surface and a second stepped surface on two opposite sides in the vertical direction; performing a decomposition step on the photomask pattern, decomposing the photomask pattern into a plurality of alternating first stripe patterns and a plurality of second stripe patterns; horizontally expanding the width of each first stripe pattern and each second stripe pattern to form a plurality of first trimmed patterns and a plurality of second trimmed patterns; forming and outputting a merged photomask pattern to form a mask layer on a target layer; and performing an etching process on the target layer through the mask layer to form a semiconductor structure. This invention enables the subsequently output mask to have a more precise pattern and contour. Therefore, it can optimize the quality of the mask and the component reliability of the subsequently fabricated semiconductor structure.

Description

[0001] This application is a divisional application. The original application has the application number 202411087575.1 and the original application date is August 8, 2024. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This invention relates to a method for fabricating semiconductor structures, and more particularly to a method for fabricating semiconductor structures using optical proximity correction (OPC) technology. Background Technology

[0003] In the fabrication of integrated circuits, photolithography is an indispensable technology. Currently, at technology nodes of 32 nanometers and below, the resolution requirements of photolithography have exceeded the limits of existing photolithography equipment. Therefore, double patterning technique (DPT), which can increase the minimum pattern distance on existing photolithography equipment, has become a solution for 32-nanometer to 22-nanometer linewidth technologies. DPT technology involves decomposing a high-density circuit pattern into two or more lower-density circuit patterns, fabricating photomasks for each, and sequentially performing the corresponding exposure and etching processes, ultimately merging them to form the initially required high-density pattern. However, because DPT technology requires multiple exposure steps, overlap control and alignment have always been key concerns, especially when high-density circuit patterns are decomposed into two or more lower-density circuit patterns. Overlap errors or inaccurate alignment in DPT can lead to broken or connected circuit lines, causing serious open or short circuit problems. Therefore, the industry still needs to improve the manufacturing methods of semiconductor structures to overcome the aforementioned problems and produce more reliable semiconductor structures for components. Summary of the Invention

[0004] One objective of this invention is to provide a method for fabricating a semiconductor structure. This method utilizes a computing system to input a photomask pattern with a stepped surface, improving upon problems such as pattern misalignment, wasted space, or incomplete patterns easily arising from differences in arrangement and / or size between different layout patterns. This allows the subsequently output mask to have a more precise pattern and contour. Consequently, it optimizes the quality of the mask and improves the reliability of the resulting semiconductor structure.

[0005] To achieve the above objectives, an embodiment of the present invention provides a method for fabricating a semiconductor structure, comprising the following steps: A computing system is provided, and a photomask pattern is input. The photomask pattern has a first stepped surface and a second stepped surface on two opposite sides in a vertical direction. A decomposition step is performed on the photomask pattern, decomposing it into a plurality of first stripe patterns and a plurality of second stripe patterns arranged alternately in a horizontal direction perpendicular to the vertical direction. A trimming step is performed on each of the first stripe patterns and each of the second stripe patterns, increasing the width of each of the first stripe patterns and each of the second stripe patterns in the horizontal direction to form a plurality of first trimmed patterns and a plurality of second trimmed patterns, wherein each of the first trimmed patterns overlaps with an adjacent second trimmed pattern. The first trimmed patterns and the second trimmed patterns are merged to form a merged photomask pattern. The merged photomask pattern is output to form a mask layer on a target layer. An etching process is performed on the target layer through the mask layer to form the semiconductor structure.

[0006] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure fabrication method provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0007] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0008] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to a first preferred embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram illustrating the input of a first photomask pattern and a second photomask pattern in the method for fabricating a semiconductor structure according to a first preferred embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram illustrating the decomposition of the second photomask pattern in the method for fabricating a semiconductor structure according to a first preferred embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of outputting a first photomask pattern in a method for fabricating a semiconductor structure according to a first preferred embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram of the formation of a first mask layer in the method for fabricating a semiconductor structure according to a first preferred embodiment of the present invention;

[0014] Figure 6 This is a top view schematic diagram of the method for forming a second mask layer in the semiconductor structure fabrication method according to a first preferred embodiment of the present invention;

[0015] Figure 7 for Figure 6 A cross-sectional view along the tangent line A-A';

[0016] Figure 8 This is a top view schematic diagram of the semiconductor structure being formed in the semiconductor structure fabrication method according to the first preferred embodiment of the present invention; Figure 9 for Figure 8 A cross-sectional view along the tangent line A-A';

[0017] Figure 10 This is another schematic diagram illustrating the decomposition of the second photomask pattern in a method for fabricating a semiconductor structure according to other preferred embodiments of the present invention;

[0018] Figure 11 This is another schematic diagram illustrating the decomposition of the second photomask pattern in a method for fabricating a semiconductor structure according to other preferred embodiments of the present invention;

[0019] Figure 12 This is yet another schematic diagram illustrating the decomposition of the second photomask pattern in a method for fabricating a semiconductor structure according to other preferred embodiments of the present invention;

[0020] Figure 13 This is a flowchart illustrating a method for fabricating a semiconductor structure according to a second preferred embodiment of the present invention;

[0021] Figure 14 A schematic diagram of an input photomask pattern for a method of fabricating a semiconductor structure according to a second preferred embodiment of the present invention;

[0022] Figure 15 This is a schematic diagram illustrating the decomposition and refining of a photomask pattern in a method for fabricating a semiconductor structure according to a second preferred embodiment of the present invention.

[0023] The reference numerals in the attached figures are explained as follows:

[0024] 10 Semiconductor Structure

[0025] 100 substrate

[0026] 110 Target Layer

[0027] 112 Target Pattern

[0028] 114 Target Boundary

[0029] 114a First arc edge

[0030] 114b Second arc edge

[0031] 120 First photomask pattern

[0032] 130 Second photomask pattern

[0033] 132 Stepped surface

[0034] 132a First plane

[0035] 132b Second Plane

[0036] 232, 432, 532, 632 First mask patterns

[0037] 234, 434, 534, 634 Second mask patterns

[0038] 302 First photolithography mask

[0039] 304 substrate

[0040] 306 Light-blocking pattern

[0041] 320 protective layer

[0042] 322 Protective Pattern

[0043] 330, 340 mask layers

[0044] 332 Second Mask Layer

[0045] 332s curved edge

[0046] 334 First arc edge

[0047] 336 Second arc edge

[0048] 342 First mask layer

[0049] 350 First mask structure

[0050] 352 Photoresist Bottom Layer

[0051] 354 Photoresist Intermediate Layer

[0052] 356 Bottom Anti-reflective Coating

[0053] 358 Photoresist layer

[0054] 362, 364 Second photolithography mask

[0055] 366, 368 light-blocking patterns

[0056] 370 Second mask structure

[0057] 372 Photoresist Bottom Layer

[0058] 374 Photoresist Intermediate Layer

[0059] 376 Photoresist layer

[0060] 532p Protrusion

[0061] 636 Third mask pattern

[0062] 730 photomask pattern

[0063] 732 First Stepped Surface

[0064] 732a, 734a First Plane

[0065] 734 Second Stepped Surface

[0066] 732b, 734b Second Plane

[0067] 736 First strip pattern

[0068] 738 Second strip pattern

[0069] 740 First Revision Pattern

[0070] 742 Second Revision Pattern

[0071] A1, A2 center points

[0072] C1, C3 odd-numbered sequences

[0073] C2, C4 even number sequence

[0074] Spacing between P1, P2, P3, and P4

[0075] R1 section

[0076] R2 (another part)

[0077] Minimum distances for S1, S2, S3, and S4

[0078] Widths of W1, W2, W3, and W4

[0079] X parallel direction

[0080] Y-direction

[0081] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0082] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0083] Please see Figures 1 to 9 As shown, it illustrates a schematic diagram of a method for fabricating a semiconductor structure according to a preferred embodiment of the present invention. First, as Figure 1 and Figure 2 As shown, the method for fabricating the semiconductor structure in this embodiment includes, but is not limited to, the following steps: A computing system is provided (step S1), such as a computer component (not shown), and a photomask pattern is input through the computer component (step S2).

[0084] Among them, the photomask pattern includes, for example, such as Figure 2 The multiple first photomask patterns 120 and second photomask patterns 130 shown are, in this embodiment, input sequentially using a computer component. Specifically, as... Figure 2 As shown, the first photomask pattern 120 is arranged in an array, for example, along a first direction D1 and a second direction D2 that are not perpendicular to each other. Any two adjacent first photomask patterns 120 have the same spacing P1 in the vertical direction Y and the same spacing P2 in the horizontal direction X, but are not limited thereto.

[0085] The array comprises multiple odd-numbered columns C1 and even-numbered columns C2 arranged in the vertical direction Y. The first photomask patterns 120 arranged in adjacent odd-numbered columns C1 and even-numbered columns C2 are not aligned with each other in the parallel direction X, but are staggered. However, the first photomask pattern 120 arranged in either odd-numbered column C1 or even-numbered column C2 can be aligned in the parallel direction X with a first photomask pattern 120 also arranged in another odd-numbered column C1 or another even-numbered column C2. Figure 2 As shown, but not limited to.

[0086] For example Figure 2As shown, the second photomask pattern 130 covers the first photomask pattern 120 and has a stepped surface 132 in the parallel direction X. Preferably, the second photomask pattern 130 completely overlaps the portion R1 of the first photomask pattern 120 and completely exposes the other portion R2 of the first photomask pattern 120. That is, neither of the first photomask patterns 120 is partially covered by or exposed from the second photomask pattern 130. It should be noted that the stepped surface 132 of the second photomask pattern 130 further includes a plurality of non-coplanar and alternately arranged first planes 132a and a plurality of second planes 132b, wherein the minimum distances S1 and S2 between the first plane 132a or the second plane 132b in the vertical direction Y and an adjacent first photomask pattern 120 are preferably less than the spacing P1 of the adjacent first photomask patterns 120 in the vertical direction Y, so that the stepped surface 132 can extend along the contour of the first photomask pattern 120 of the portion R1, avoiding excessive coverage of the area outside the first photomask pattern 120 of the portion R1. In one embodiment, the minimum distances S1 and S2 may be the same or different from each other, and are not limited to... Figure 2 The examples shown are limited to those shown.

[0087] Next, as Figure 1 and Figure 3 As shown, the photomask pattern is decomposed to generate a secondary mask pattern (step S21). Specifically, the second photomask pattern 130 is decomposed to generate a plurality of secondary mask patterns, such that the secondary mask patterns at least partially overlap. In one embodiment, the secondary mask patterns include, for example, as shown in the figure below. Figure 3 The multiple first mask patterns 232 and multiple second mask patterns 234 shown are provided, wherein some of the first mask patterns 232 overlap with adjacent second mask patterns 234, and some of the first mask patterns 232 are adjacent to adjacent second mask patterns 234, but this is not a limitation.

[0088] The first mask pattern 232 and the second mask pattern 234 each include strip-shaped patterns extending in the vertical direction Y, such that the top surfaces of each of the first mask patterns 232 are aligned, for example. Figure 2 The first plane 132a of the stepped surface 132 is used, while the top surface of each of the second mask patterns 234 is, for example, aligned with the second plane 132b of the stepped surface 132. Thus, the first mask pattern 232 and the second mask pattern 234 can be arranged alternately in the horizontal direction X, and respectively cover the first photomask pattern 120 arranged in the odd-numbered column C1 and the even-numbered column C2.

[0089] Next, as Figure 1 ,and Figures 3 to 7 As shown, a mask layer is formed (step S3). First, as... Figures 3 to 5As shown, the computer components will... Figure 3 The first photomask pattern 120 shown is output as follows Figure 4 The first photomask 302 shown is used as the basis for subsequent exposure and development processes on the semiconductor structure 10, ultimately forming the structure as shown. Figure 5 The first mask layer 342 is shown. Specifically, as... Figure 4 As shown, the first photolithographic mask 302 includes a light-transmitting substrate 304, such as a transparent quartz substrate, and light-shielding patterns 306 formed on the substrate 304, wherein each light-shielding pattern 306 can correspond to, respectively, a light-transmitting substrate 304. Figure 3 The various first photomask patterns 120 shown have the same spacing P2 in the horizontal direction X. On the other hand, the semiconductor structure 10 includes a substrate 100, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, and a target layer 110, a protective layer 320, a mask layer 330, a mask layer 340, and a first mask structure 350, which are sequentially stacked on the substrate 100.

[0090] In one embodiment, the target layer 110 may include, for example, a conductive material, such as a low-resistivity metal material like aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), or a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. The target layer 110 may be patterned into the desired pattern in a subsequent process using photolithography. The protective layer 320 may include, for example, a dielectric material like silicon nitride, silicon oxide, or silicon oxynitride to protect the underlying target layer 110. The mask layer 330 and mask layer 340 may each include, for example, suitable mask materials, such as silicon oxide or amorphous silicon, to facilitate the transfer of the aforementioned desired pattern in subsequent processes, but are not limited thereto.

[0091] For example Figure 4As shown, the first mask structure 350 specifically includes, from bottom to top, a photoresist bottom layer 352 (e.g., including a spin-coated carbon layer), a photoresist intermediate layer 354 (e.g., including silicon oxynitride), a bottom anti-reflective coating (BAC) 356, and a photoresist layer 358, stacked sequentially. The photoresist layer 358 has a pattern corresponding to the light-shielding pattern 306 by performing an exposure and development process to transfer the light-shielding pattern 306 onto it. It should be noted that when the light-shielding pattern 306 is transferred to the photoresist layer 358 through the exposure and development process, the linewidth and spacing of the light-shielding pattern 306 will be proportionally reduced, but this is not a limitation. Then, an etching process is performed to transfer the pattern of the photoresist layer 358 onto the lower mask layer 340, forming a shape as shown below. Figure 5 The first mask layer 342 is shown, and the first mask structure 350 is completely removed.

[0092] like Figure 3 , Figures 5 to 7 As shown, the computer components will... Figure 3 The first mask pattern 232 and the second mask pattern 234, obtained by decomposing the second photomask pattern 130 shown, are output sequentially as follows: Figure 5 The second photomasks 362 and 364 shown are used to perform subsequent exposure and development processes on the semiconductor structure 10 based on the second photomasks 362 and 364, forming a structure as shown. Figure 6 and Figure 7 The second mask layer 332 is shown. Specifically, as... Figure 5 As shown, the second photolithographic masks 362 and 364 also include a light-transmitting substrate 304, and photomasks formed on the substrate 304 and respectively corresponding to the following: Figure 3 The light-shielding patterns 366 and 368 of the respective first mask patterns 232 and the respective second mask patterns 234 are shown. Furthermore, a second mask structure 370 is formed on the substrate 100. The second mask structure 370 includes a photoresist bottom layer 372 (e.g., including an organic dielectric layer), a photoresist intermediate layer 374 (e.g., including silicon oxynitride), and a photoresist layer 376, stacked sequentially from bottom to top. The photoresist layer 376 has a pattern corresponding to the light-shielding patterns 366 and 368 by performing an exposure and development process. Then, an etching process is performed to transfer the pattern of the photoresist layer 376 onto the underlying mask layer 330, forming... Figure 6 and Figure 7 The second mask layer 332 is shown, and the second mask structure 370 is completely removed.

[0093] It should be noted that, due to the influence of optical near-diffraction, when exposure and development processes are performed through the second photolithographic masks 362 and 364 respectively, [the following will occur]... Figure 5 Multiple patterns (not shown) with arcuate edges are correspondingly generated on the photoresist layer 376. Thus, when the arcuate patterns are simultaneously transferred to the second mask layer 332, a pattern resembling an arcuate edge is formed on the second mask layer 332. Figure 6 The arc-shaped edge 332s shown includes a plurality of first arc edges 334 and a plurality of second arc edges 336 protruding toward the vertical direction Y. Then, as... Figure 1 ,and Figures 6 to 9 As shown, a semiconductor structure 10 is formed through a mask layer (step S4). Figure 1 , Figures 6 to 9 As shown, through as Figure 6 and Figure 7 The first mask layer 342 and the second mask layer 332 shown perform an etching process on the underlying protective layer 320 and target layer 110, transferring the pattern of the first mask layer 342 to the protective layer 320 and target layer 110, forming as shown. Figure 8 and Figure 9 The diagram shows multiple protective patterns 322 and multiple target patterns 112 below them. The pattern of the second mask layer 332 is also transferred to the protective layer 320 and the target layer 110, and a pattern is defined on the target layer 110 as shown below. Figure 8 The target boundary 114 is shown. This forms the following... Figure 8 and Figure 9 The semiconductor structure 10 shown is then completely removed, including the first mask layer 342, the second mask layer 332, and the protective layer 320.

[0094] Please refer to this again. Figure 8 and Figure 9 As shown, the semiconductor structure 10 includes target patterns 112 arranged in an array along a first direction D1 and a second direction D2. Adjacent target patterns 112 have the same spacing P3 and P4 in both the vertical direction Y and the horizontal direction X, but are not limited thereto. Furthermore, the target patterns 112 are further arranged into multiple odd-numbered columns C3 and multiple even-numbered columns C4 in the vertical direction Y, and the odd-numbered columns C3 and even-numbered columns C4 are arranged alternately in the parallel direction X. It should be noted that the target patterns 112 arranged in adjacent odd-numbered columns C3 and even-numbered columns C4 are not aligned with each other in the parallel direction X, but are staggered. However, the target patterns 112 arranged in either odd-numbered column C3 or even-numbered column C4 can be aligned with the target patterns 112 also arranged in another odd-numbered column C3 or another even-numbered column C4 in the parallel direction X, such as... Figure 8 As shown, but not limited to.

[0095] On the other hand, the target boundary 114 extends, for example, along the contour of the target pattern 112, and includes a plurality of first arc edges 114a and a plurality of second arc edges 114b protruding in the vertical direction Y, respectively. The center points A1 and A2 of the first arc edges 114a and the second arc edges 114b are not coplanar in the horizontal direction X. It should be noted that the minimum distance S3 from the center point A1 of the first arc edge 114a to one of the target patterns 112 in the odd-numbered column C3 is less than the spacing P3. Similarly, the minimum distance S4 from the center point A2 of the second arc edge 114b to one of the target patterns 112 in the even-numbered column C4 is also less than the spacing P3. In this way, the area without the target pattern 112 can be prevented from being too large, thus affecting the space for component configuration on the semiconductor structure 10.

[0096] According to the semiconductor structure fabrication method in this embodiment, a second photomask pattern with a stepped surface is input into a computing system. This allows the stepped surface to extend along the uneven layout and contour of the first photomask pattern, thereby completely and effectively covering the corresponding first photomask pattern and avoiding incomplete or excessive coverage. Under this operation, the semiconductor structure fabrication method in this embodiment helps to improve problems such as pattern misalignment, wasted space, or incomplete patterns easily arising from differences in arrangement and / or size between different layout patterns, resulting in a more accurate pattern and contour in the subsequently output mask. Furthermore, before outputting the first and second photomask patterns, the second photomask pattern can be pre-decomposed into multiple sub-mask patterns that at least partially overlap. This allows the sub-mask patterns to better fit the aforementioned uneven layout and contour, further improving the quality of the subsequently output mask and thereby producing a semiconductor structure with optimized component reliability.

[0097] Under this premise, the semiconductor structure fabrication method in this embodiment can be used to fabricate various suitable semiconductor devices, such as dynamic random access memory (DRAM) or static random access memory (DRAM), and is suitable for fabricating highly integrated components or circuit layouts, but is not limited thereto. For example, the aforementioned first photomask pattern can be used to fabricate photomasks for memory node plugs or memory node pads, while the aforementioned second photomask pattern can be used to fabricate photomasks that define the layout boundaries of memory node plugs or memory node pads.

[0098] Those skilled in the art will understand that the specific arrangement and layout of the first photomask pattern, the specific state of the stepped surface of the second photomask pattern, and / or the specific arrangement and layout of the secondary mask pattern in this embodiment are not limited to those shown in the foregoing figures, but can be further adjusted according to the actual component requirements. For example, in other embodiments, the secondary mask pattern may also include, for instance, the following: Figure 10The first mask pattern 432 and multiple second mask patterns 434 shown are as follows: Figure 11 The first mask pattern 532 and multiple second mask patterns 534 shown, or as... Figure 12 The examples shown include the first mask pattern 632, multiple second mask patterns 634, and multiple third mask patterns 636, but are not limited to these.

[0099] Specifically, such as Figure 10 As shown, the first mask pattern 432, for example, has a rectangular pattern, which completely covers the first photomask pattern 120 in part R1, and partially exposes the first photomask pattern 120 arranged in even-numbered columns C2. The second mask patterns 434 are arranged sequentially in the horizontal direction X and partially overlap the first mask pattern 432. Thus, each of the second mask patterns 434 exactly overlaps and completely covers the first photomask pattern 120 arranged in even-numbered columns C2 and partially exposed from the first mask pattern 432. That is, through the arrangement and combination of the first mask pattern 432 and the second mask pattern 434, the top surfaces of the first mask pattern 432 and the second mask pattern 434 are effectively aligned. Figure 2 The first plane 132a and the second plane 132b of the stepped surface 132 in the middle achieve the effect of completely covering the first photomask pattern 120 of the portion R1.

[0100] On the other hand, such as Figure 11 As shown, the first mask pattern 532 includes, for example, a plurality of protrusions 532P extending in the vertical direction Y, to completely overlap and cover all the first photomask patterns 120 arranged in the even-numbered column C2. The second mask pattern 534 is arranged in the horizontal direction X, overlapping the first mask pattern 532, and alternating with the protrusions 532P of the first mask pattern 532, to completely overlap and cover the first photomask patterns 120 arranged in the odd-numbered column C1 that are partially exposed from the first mask pattern 532. In other words, through the arrangement and combination of the first mask pattern 532 and the second mask pattern 534, the top surfaces of the protrusions 532p of the first mask pattern 532 and the top surfaces of the second mask pattern 534 are effectively aligned. Figure 2 The second plane 132b and the first plane 132a of the stepped surface 132 in the middle achieve the effect of completely covering the first photomask pattern 120 of the portion R1.

[0101] On the other hand, such as Figure 12As shown, the first mask pattern 632, for example, has a rectangular pattern, which completely covers the first photomask pattern 120 in part R1, and partially exposes the first photomask patterns 120 arranged in odd-numbered columns C1 and even-numbered columns C2. The second mask pattern 634 and the third mask pattern 636 are arranged alternately in the horizontal direction X and partially overlap the first mask pattern 632, such that each second mask pattern 634 completely overlaps and covers the first photomask patterns 120 arranged in odd-numbered columns C1 and partially exposed from the first mask pattern 632, and each third mask pattern 636 completely overlaps and covers the first photomask patterns 120 arranged in even-numbered columns C2 and partially exposed from the first mask pattern 632. That is, through the arrangement and combination of the first mask pattern 632, the second mask pattern 634 and the third mask pattern 636, the top surface of the second mask pattern 634 and the top surface of the third mask pattern 636 are also effectively aligned. Figure 2 The second plane 132b and the first plane 132a of the stepped surface 132 in the middle achieve the effect of completely covering the first photomask pattern 120 of the portion R1.

[0102] Under this operation, when outputting through computer components as follows Figure 2 When the second photomask pattern 130 is shown, the first photomask pattern 432 and multiple second photomask patterns 434 obtained by decomposing the second photomask pattern 130 can be decomposed (e.g., ...). Figure 10 (as shown), or a first mask pattern 532 and multiple second mask patterns 534 (as shown). Figure 11 (as shown), or a first mask pattern 632, multiple second mask patterns 634 and multiple third mask patterns 636 (as shown). Figure 12 (As shown) It is simultaneously output as a photomask, and then subsequent exposure and development processes are performed based on the photomask, thus forming a similar image. Figure 8 and Figure 9 The semiconductor structure 10 is shown.

[0103] Those skilled in the art will readily understand that, to meet the needs of actual products, the method for fabricating the semiconductor structure in this invention may have other forms, and is not limited to the embodiments described above. For example, in another embodiment, it is also possible to pre-input the pattern when inputting it. Figure 3 The first mask pattern 232 and multiple second mask patterns 234 shown, or as... Figure 10 The first mask pattern 432 and multiple second mask patterns 434 shown, or as... Figure 11 The first mask pattern 532 and multiple second mask patterns 534 shown, or as... Figure 12The first mask pattern 632, multiple second mask patterns 634, and multiple third mask patterns 636 shown are then merged using a pattern merging step. Figure 3 The first mask pattern 232 and multiple second mask patterns 234 shown, or as... Figure 10 The first mask pattern 432 and multiple second mask patterns 434 shown, or as... Figure 11 The first mask pattern 532 and multiple second mask patterns 534 shown, or as... Figure 12 The first mask pattern 632, multiple second mask patterns 634, and multiple third mask patterns 636 shown are first merged into a photomask pattern (step S21), and then the photomask pattern is output as a photolithography mask, but this is not a limitation. Other embodiments or variations of the semiconductor structure fabrication method of the present invention will be further described below. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and will not repeat the same points. Furthermore, the same components in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0104] Please see Figures 13 to 15 As shown, it illustrates a schematic diagram of a method for fabricating a semiconductor structure in a second preferred embodiment of the present invention. First, as Figure 13 and Figure 14 As shown, a computing system is provided (step S1), such as a computer component (not shown), and a photomask pattern is input through the computer component (step S2). Specifically, the photomask pattern 730 has a first stepped surface 732 and a second stepped surface 734 on two opposite sides in the vertical direction Y, respectively. The first stepped surface 732 and the second stepped surface 734 each have alternating arrangements of multiple first planes 732a, 734a and multiple second planes 732b, 734b, so as to effectively cover or correspond to other patterns or areas with different layouts or arrangements. That is, although the first photomask pattern 120 as in the aforementioned embodiment, or similar patterns with other arrangements or layouts, is omitted in the drawings of this embodiment, those skilled in the art should easily understand that the photomask pattern 730 is input into the computer component according to the actual structural manufacturing requirements so as to correspond to the aforementioned patterns or areas, thereby enabling the aforementioned patterns or areas to be effectively covered or overlapped.

[0105] like Figures 13 to 15 As shown, the photomask pattern is decomposed to generate a striped pattern (step S51). Specifically, the photomask pattern 730 is further decomposed into a plurality of first striped patterns 736 and a plurality of second striped patterns 738 extending in the vertical direction Y, respectively. Figure 15 As shown, the top and bottom surfaces of each of the first strip patterns 736 are, for example, aligned as follows: Figure 14The first plane 732a of the first stepped surface 732 and the first plane 734a of the second stepped surface 734 are shown, while the top and bottom surfaces of each second striped pattern 738 are, for example, aligned as follows: Figure 14 The second plane 732b of the first stepped surface 732 and the second plane 734b of the second stepped surface 734 are shown. Thus, the first striped pattern 736 and the second striped pattern 738 can be arranged alternately in the horizontal direction X.

[0106] Next, for example Figure 13 and Figure 15 As shown, the striped pattern is trimmed to form a trimmed pattern (step S52). Specifically, the system is amplified as follows: Figure 15 The widths W1 and W2 of each of the first strip patterns 736 and each of the second strip patterns 738 in the horizontal direction X form as shown. Figure 15 The plurality of first trimming patterns 740 and the plurality of second trimming patterns 742 shown are configured such that each first trimming pattern 740 and each second trimming pattern 742 has a relatively large width W3 and W4, respectively. That is, the width W3 of the first trimming pattern 740 is greater than the width W1 of the first strip pattern 736, and the width W4 of the second trimming pattern 742 is greater than the width W2 of the second strip pattern 738, so that the first trimming pattern 740 can partially overlap with the adjacent second trimming pattern 742. In one embodiment, the width W1 of the first strip pattern 736 is, for example, equal to the width W2 of the second strip pattern 738, and the width W3 of the first trimming pattern 740 can also be equal to the width W4 of the second trimming pattern 742, such as... Figure 15 As shown, but not limited to. In another embodiment, the width W1 of the first strip pattern 736 may also be greater than the width W2 of the second strip pattern 738, or, after trimming the strip pattern, the width W3 of the first trimmed pattern 740 may not be equal to the width W4 of the second trimmed pattern 742, both of which can achieve the effect that the first trimmed pattern 740 can partially overlap with the adjacent second trimmed pattern 742.

[0107] Then, as Figure 13 As shown, the trimmed patterns can be merged to form a merged photomask pattern as described in the previous embodiments (step S53). That is, the first trimmed pattern 740 and the second trimmed pattern 742 are first merged into a merged photomask pattern (not shown), and then the merged photomask pattern is output. Figure 4 A mask layer is formed on the target layer 110 shown (step S6). Finally, an etching process is performed through the mask layer to form another semiconductor structure (step S7).

[0108] Overall, this invention utilizes a computing system to generate photomask patterns with stepped surfaces, improving upon problems such as pattern misalignment, wasted space, or incomplete patterns that easily arise from differences in arrangement and / or size between different layout patterns. This allows the subsequently output mask to have a more precise pattern and contour. Consequently, it optimizes the quality of the mask and the reliability of the resulting semiconductor structure components.

[0109] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide computing systems; Input a photomask pattern, wherein the photomask pattern has a first stepped surface and a second stepped surface on two opposite sides in the vertical direction, respectively; A decomposition step is performed on the photomask pattern to decompose the photomask pattern into a plurality of first strip patterns and a plurality of second strip patterns that are alternately arranged in a horizontal direction perpendicular to the vertical direction; A trimming step is performed on each of the first strip patterns and each of the second strip patterns to increase the width of each of the first strip patterns and each of the second strip patterns in the horizontal direction, forming a plurality of first trimming patterns and a plurality of second trimming patterns, wherein each of the first trimming patterns overlaps with an adjacent second trimming pattern. The first trimming pattern and the second trimming pattern are merged to form a merged photomask pattern; Output the merged photomask pattern to form a mask layer on the target layer; and The semiconductor structure is formed by etching the target layer through the mask layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first strip pattern and the second strip pattern have the same width in the horizontal direction.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The width of the first strip pattern in the horizontal direction is greater than the width of the second strip pattern in the horizontal direction.

4. The method for fabricating a semiconductor structure according to any one of claims 1-3, characterized in that, The target layer includes a dielectric material or a conductive material.

Images