Parallel address translation method and apparatus based on memory management unit, and computer device

Abstract

The disclosure provides a memory management unit-based parallel address translation method and device and computer equipment, and relates to the technical field of computers. The implementation scheme is as follows: obtaining a request for invalidation operation; performing respective address translation operations based on a preset speculation page size via at least two idle entries in parallel, and the start virtual addresses of the respective address translation operations differ by the speculation page size; in response to the real page size being equal to the speculation page size, transmitting the result of the address translation operation to a lower module; in response to the real page size being smaller than the speculation page size, sequentially performing multiple address translation operations on the virtual addresses in the speculation page size according to the real page size until all virtual addresses corresponding to the speculation page size complete address translation, and transmitting the result of the multiple address translation operations to the lower module; and in response to the real page size being greater than the speculation page size, transmitting the result obtained by the first completed address translation operation to the lower module.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, particularly to the fields of chips and memory management, and especially to a parallel address translation method, apparatus, computer device, computer-readable storage medium, and computer program product based on a memory management unit. Background Technology

[0002] Cache invalidation typically involves marking outdated or unusable data in the cache as invalid. When invalidating a large cache space in a chip, it needs to be divided into multiple subspaces based on page size, and virtual address to physical address translation is performed sequentially. However, since page sizes may change dynamically, i.e., mixed page sizes may exist, each translation must be performed serially: that is, the starting address and translation parameters of the next subspace can only be determined after the page size lookup of the previous subspace is completed. This strong dependency leads to low address translation efficiency and becomes a system performance bottleneck. Summary of the Invention

[0003] This disclosure provides a parallel address translation method, apparatus, computer device, computer-readable storage medium, and computer program product based on a memory management unit.

[0004] According to one aspect of this disclosure, a parallel address translation method based on a memory management unit is provided, wherein the memory management unit includes multiple entries for performing address translation, and the method includes: obtaining a request for invalidating a cache, the request indicating a virtual address space for which invalidation is to be performed; for the virtual address space, performing respective address translation operations in parallel based on a preset estimated page size via at least two free entries from the multiple entries, wherein the starting virtual addresses of the at least two free entries performing their respective address translation operations differ by the estimated page size, the estimated page size being determined based on any one of multiple page sizes supported by the memory management unit; wherein, during address translation... During the operation, the result of the address translation operation is determined based on a comparison between the actual page size and the estimated page size, wherein: in response to the actual page size being equal to the estimated page size, the result of the address translation operation is transmitted to the lower-level module used to perform the invalidation operation; in response to the actual page size being less than the estimated page size, multiple address translation operations are performed sequentially on the virtual addresses in the estimated page size according to the actual page size until all virtual addresses corresponding to the estimated page size have completed address translation, and the result of the multiple address translation operations is transmitted to the lower-level module; and in response to the actual page size being greater than the estimated page size, the result obtained from the first address translation operation completed among at least two free entries is transmitted to the lower-level module.

[0005] In some embodiments, the virtual address space includes a target starting virtual address, and at least two free entries include a first entry and a second entry. The parallel execution of address translation operations based on a preset estimated page size further includes: determining the initial starting virtual address of the first entry and the second entry, wherein the initial starting virtual address of the first entry is the same as the target starting virtual address, and the initial starting virtual address of the second entry is the sum of the target starting virtual address and the estimated page size.

[0006] In some embodiments, the virtual address space further includes a target length, which includes a plurality of sub-target lengths, each sub-target length corresponding to a different page size, such that the inferred page size is selected from any of the plurality of page sizes.

[0007] In some embodiments, after the first entry and the second entry have completed the address translation operation for the current sub-target length in parallel, the address translation operation for the next sub-target length is performed in parallel.

[0008] In some embodiments, the multiple page sizes include 4K, 64K and 2M, with the presumed page size preset to 64K.

[0009] In some embodiments, the memory management unit includes a filtering output module, which is used to receive the results of address translation operations transmitted by at least two free entries, and to discard the currently received result when the currently received result is the same as the previously received result.

[0010] According to one aspect of this disclosure, a parallel address translation apparatus based on a memory management unit is provided, wherein the memory management unit includes a plurality of entries for performing address translation, and the apparatus includes: a request acquisition unit configured to acquire a request for invalidating a cache, the request indicating a virtual address space for which invalidation is to be performed; and a translation execution unit configured to perform respective address translation operations in parallel for the virtual address space via at least two free entries from the plurality of entries, based on a preset estimated page size, wherein the starting virtual addresses of the at least two free entries performing their respective address translation operations differ from the estimated page size, and the estimated page size is based on any one of a plurality of page sizes supported by the memory management unit. The following steps are taken: In the address translation operation, the result of the address translation operation is determined based on a comparison between the obtained actual page size and the estimated page size, wherein: in response to the actual page size being equal to the estimated page size, the result of the address translation operation is transmitted to the lower-level module used to perform the invalidation operation; in response to the actual page size being less than the estimated page size, multiple address translation operations are performed sequentially on the virtual addresses in the estimated page size according to the actual page size until all virtual addresses corresponding to the estimated page size have completed address translation, so that the result of the multiple address translation operations is transmitted to the lower-level module; and in response to the actual page size being greater than the estimated page size, the result obtained from the first address translation operation completed among at least two free entries is transmitted to the lower-level module.

[0011] According to another aspect of this disclosure, a computer device is provided, comprising: at least one processor; and a memory having a computer program stored thereon, wherein when executed by the at least one processor, the computer program causes the at least one processor to perform the methods provided above in this disclosure.

[0012] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0013] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0014] According to one or more embodiments of this disclosure, the total time consumed for address translation operations in invalidation operations can be effectively reduced.

[0015] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0016] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0017] Figure 1 This diagram illustrates serial address translation in existing technologies.

[0018] Figure 2 This is a flowchart illustrating a parallel address translation method according to an exemplary embodiment.

[0019] Figure 3 This is a schematic diagram illustrating a memory management unit according to an exemplary embodiment.

[0020] Figure 4 This is a schematic diagram illustrating a parallel address translation method according to an exemplary embodiment.

[0021] Figure 5 This is a schematic block diagram illustrating a parallel address translation device according to an exemplary embodiment.

[0022] Figure 6 This is a block diagram illustrating an exemplary computer device that can be applied to an exemplary embodiment. Detailed Implementation

[0023] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0024] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to define the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0025] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0026] In related technologies, two methods are typically used for large-scale cache invalidation operations. One method is global invalidation based on cache identifiers. This method directly invalidates all cache lines associated with a specified cache identifier, thus avoiding virtual-to-physical address translation. However, this method has limited applicability, requiring all cached data under the target cache identifier to be in an invalidable state, which prevents selective retention of valid data. The other method is big-page mode to accelerate lookups. This method configures the memory management unit to use big-page mapping (e.g., 2MB, 1GB) to reduce the number of page table lookups during address translation, thereby reducing single invalidation latency. However, this method has the limitation of memory waste; forced big-page alignment can lead to internal fragmentation, especially for small objects or sparse access scenarios. Therefore, there is a significant serialization bottleneck when the memory management unit performs large-scale address translation. Since the current page size must be determined through a complete page table lookup, and the starting address of the next page depends on this result, address translation requests cannot be initiated in parallel, and performance drops sharply when the page table cache (TLB) is missed.

[0027] Figure 1 This diagram illustrates serial address translation in existing technologies.

[0028] For illustrative purposes, an example is shown of the process of serial address translation for a virtual address space starting at 1M and 3M in length. Within this virtual address space, the first 256K of the virtual address space (e.g., ...) is used for serial address translation. Figure 1 The “1M~1.25M” shown uses a 4K page size, and the following 768K virtual address space (such as…) Figure 1 The “1.25M~2M” shown uses a page size of 64K, and the last 2M virtual address space (such as…) Figure 1 The "2M~4M" shown uses a 2M page size. Because address translation is performed serially, a total of 77 translations are required (e.g., ...). Figure 1 The sum of "64 transformations", "12 transformations" and "1 transformation" shown.

[0029] In existing technologies, such as Figure 1The serial address translation shown exhibits a strong sequential dependency, leading to insufficient utilization of hardware resources. Furthermore, when mixed page sizes exist, the memory management unit only learns the page size during address translation, making it difficult to achieve parallel translation in mixed-page scenarios due to the inability to know the page size in advance.

[0030] Therefore, embodiments of this disclosure provide an efficient hardware-accelerated method and apparatus for virtual address to physical address translation, which is particularly suitable for address translation acceleration scenarios when performing invalidation operations on large-capacity cache spaces in chips.

[0031] Figure 2 This is a flowchart illustrating a parallel address translation method according to an exemplary embodiment.

[0032] In embodiments according to this disclosure, the memory management unit includes multiple entries for performing address translation. For example... Figure 2 As shown, the parallel address translation method includes steps S201 and S202. In step S201, a request for invalidating the cache is obtained, the request indicating the virtual address space for which invalidation is to be performed. In step S202, for the virtual address space, respective address translation operations are performed in parallel based on a preset estimated page size, through at least two free entries from a plurality of entries.

[0033] Specifically, the estimated page size is determined based on any one of several page sizes (such as 4K, 64K, and 2M) supported by the memory management unit. That is, this involves the mixed page size situation described above. In the prior art, this situation has the limitation of having to perform serial address translation because the page size cannot be known in advance. However, the embodiments of this disclosure utilize the estimated page size mechanism to overcome this inherent approach of serial address translation, providing the possibility for multiple entries to perform address translation in parallel. Accordingly, for the virtual address space to be invalidated, at least two free entries from the multiple entries of the memory management unit perform their respective address translation operations in parallel based on the estimated page size, wherein the starting virtual addresses of the at least two free entries performing their respective address translation operations differ from the estimated page size.

[0034] During the address translation operation, the actual page size can be obtained, meaning only then can we know the true page size. Accordingly, the result of the address translation operation needs to be determined based on a comparison between the obtained actual page size and the estimated page size. This involves the following three scenarios, including steps S2021, S2022, and S2023.

[0035] In step S2021, when the actual page size equals the estimated page size, it means that the address translation operation for the current page can be completed in one go. In this case, the result of the address translation operation is transmitted to the lower-level module used to perform the invalidation operation. In the example, the result of the address translation operation may include the physical address of the current page and the length of the address to be invalidated.

[0036] In step S2022, when the actual page size is smaller than the estimated page size, it means that the address translation operation for the current page cannot be completed in one go. In this case, multiple address translation operations are performed sequentially on the virtual addresses in the estimated page size according to the actual page size, until all virtual addresses corresponding to the estimated page size have completed address translation, so that the result of these multiple address translation operations can be transmitted to the next-level module.

[0037] In step S2023, when the actual page size is larger than the estimated page size, it means that different entries may be performing address translation on the same page. In this case, the result obtained by the first of at least two parallel free entries that has completed the address translation operation is transmitted to the next-level module.

[0038] Therefore, in the parallel address translation method according to embodiments of this disclosure, the inclusion of a page size estimation mechanism breaks through the inherent limitations of traditional serial address translation, enabling multiple entries to perform address translation in parallel. Accordingly, based on this estimated page size, the entire virtual address space for which invalidation operations are to be performed can be divided into multiple smaller spaces, and address translation operations can be performed in parallel through multiple entries. This reduces the total time consumed for address translation. This is particularly beneficial for applications with mixed page sizes.

[0039] Figure 3 This is a schematic diagram illustrating a memory management unit according to an exemplary embodiment.

[0040] like Figure 3 As shown, the memory management unit may include a decoding module for parsing input commands. The parsed commands can be used to allocate tasks, dividing the virtual address space to be invalidated into multiple smaller spaces, i.e., multiple parts, based on the inferred page size. Each part is then assigned to an entry to perform an address translation operation. Accordingly, each entry can receive a corresponding translation request.

[0041] The memory management unit may include multiple entries for performing address translation, such as entry 1, entry 2, ..., entry n. Each entry can send its received translation request to the virtual address translation module to perform the address translation operation, thereby obtaining its own translation result.

[0042] In some embodiments, the memory management unit may include a filtering output module. Figure 3 Taking entries 1 and 2 as examples of free entries, the filtering output module may receive the conversion results transmitted by entries 1 and 2 sequentially. Assuming the currently received conversion result from entry 2 is the same as the previously received conversion result from entry 1 (i.e., a duplicate), the conversion result from entry 2 can be directly discarded. Therefore, the filtering output module can be used to receive the address translation operation results transmitted by at least two free entries and discard the currently received result when it is a duplicate of the previously received result.

[0043] By setting a filter output module in the memory management unit, the parallel address translation of multiple entries can be verified, avoiding the transmission of the results of repeated address translation operations to the lower-level module used to perform invalidation operations when the actual page size is larger than the estimated page size.

[0044] Figure 4 This is a schematic diagram illustrating a parallel address translation method according to an exemplary embodiment.

[0045] For ease of explanation, Figure 4 The description is based on an example with two free entries (such as entry 1 and entry 2) and the memory management unit supporting three page sizes (such as 4K, 64K and 2M).

[0046] First, the memory management unit receives a request to invalidate the cache, which specifies the virtual address space to be invalidated. This virtual address space may include the target starting virtual address and the target length. Figure 4 In the illustrated embodiment, the target starting virtual address is described as 1M and the target length as 3M. ​​As an example, 64K is selected as the estimated page size.

[0047] Accordingly, entries 1 and 2 can perform their respective address translation operations in parallel based on a projected page size of 64K. That is, the starting virtual addresses of the address translation operations of entries 1 and 2 differ by 64K. For example, the initial starting virtual address of entry 1 for its address translation operation is 1M with a length of 64K, and the initial starting virtual address of entry 2 for its address translation operation is 1M+64K with a length of 64K. Therefore, in some embodiments, performing the respective address translation operations in parallel based on a preset projected page size may further include: determining the initial starting virtual addresses of the first entry and the second entry, wherein the initial starting virtual address of the first entry is the same as the target starting virtual address, and the initial starting virtual address of the second entry is the sum of the target starting virtual address and the projected page size.

[0048] Item 1 can begin the address translation operation to obtain the physical address corresponding to the virtual address, and the actual page size, such as 4K. Next, the actual page size needs to be compared with the estimated page size. It can be found that the actual page size is smaller than the estimated page size. Therefore, multiple address translation operations need to be performed on the virtual addresses within the estimated page size according to the actual page size, until all virtual addresses corresponding to the estimated page size have completed address translation, in order to transmit the results of the multiple address translation operations to the next-level module, such as... Figure 4 The virtual address space "1M~1M+64K" shown corresponds to 16 address translation operations. In parallel, entry 2 can also begin performing address translation operations. Similar to entry 1, for entry 2, as... Figure 4 The virtual address space shown, “1M+64K ~1M+128K”, will also correspond to 16 address translation operations.

[0049] After entry 1 completes the address translation operation for the virtual address space "1M~1M+64K", it will perform another address translation operation based on the estimated page size of the next 64K, such as... Figure 4 The virtual address space "1M+128K~1M+192K" shown will correspond to 16 address translation operations. In parallel, after entry 2 completes the address translation operation for the virtual address space "1M+64K~1M+128K", it will also perform an address translation operation based on the estimated page size of the next 64K, such as... Figure 4 The virtual address space “1M+192K~1M+256K” shown will also correspond to 16 address translation operations. Therefore, within the virtual address space “1M~1M+256K”, entry 1 and entry 2 perform 32 address translation operations in parallel.

[0050] Next, in such Figure 4 Within the virtual address space “1M+256K~2M” shown, entries 1 and 2 also perform address translation operations in parallel in a similar manner to the above. The difference is that the actual page size obtained this time is 64K, that is, the actual page size is equal to the estimated page size. In this case, within the virtual address space “1M+256K~2M”, entries 1 and 2 perform 6 address translation operations in parallel.

[0051] Finally, in such Figure 4Within the virtual address space "2M~4M" shown, entry 1 performs an address translation operation on the virtual address space "2M~2M+64K", and entry 2 performs an address translation operation on the virtual address space "2M+64K~2M+128K". The difference here is that the actual page size obtained is now 2M, meaning the actual page size is larger than the estimated page size. In this case, within the virtual address space "2M~4M", entries 1 and 2 perform one address translation operation in parallel. However, when the filtering output module in the memory management unit receives the results of the address translation operations of entries 1 and 2 respectively, if it finds that entry 1 has already completed the address translation operation first, the filtering output module will discard the result provided by entry 2, preventing it from being transmitted to the lower-level module used to perform the invalidation operation.

[0052] In such Figure 4 In the illustrated embodiment, the target length of the virtual address space to be invalidated is 3M. ​​This target length can include multiple sub-target lengths, namely the lengths corresponding to virtual address spaces "1M~1M+256K", the lengths corresponding to virtual address spaces "1M+256K~2M", and the lengths corresponding to virtual address spaces "2M~4M". Each sub-target length can correspond to a different page size, namely 4K, 64K, and 2M. Therefore, the inferred page size can be selected from any of the above multiple page sizes, such as 64K. In some embodiments, by selecting an appropriate page size as the inferred page size, the utilization of multiple entries in the memory management unit can be maximized to enhance the parallel translation effect.

[0053] In such Figure 4 In the illustrated embodiment, for each sub-target length, such as the length corresponding to the virtual address space "1M~1M+256K", after entries 1 and 2 have completed the address translation operation for the current sub-target length in parallel, they then perform the address translation operation for the next sub-target length in parallel, such as the length corresponding to the virtual address space "1M+256K~2M". Therefore, after the first entry and the second entry have completed the address translation operation for the current sub-target length in parallel, they then perform the address translation operation for the next sub-target length in parallel.

[0054] For example Figure 1 As shown in the serial address translation method, in the parallel address translation method according to the embodiments of this disclosure, the total translation time is reduced from 64+12+1=77 translations to 32+6+1=39 translations, which is almost half of the time consumption.

[0055] Therefore, the parallel address translation method according to embodiments of this disclosure can significantly reduce the latency caused by address translation operations during cache invalidation operations. By parallelizing the execution of virtual address translation, the total translation time is reduced. Especially when the number of entries is large, the total translation time can be reduced by a factor of two. For example, assuming the memory management unit includes 16 entries and performs invalidation operations on 8M space, if the page size is 4K, the traditional serial translation method would require a total of 2048 address translations. However, if the parallel address translation method according to embodiments of this disclosure is used, it would only require 2048 / 16 = 128 address translations, thereby greatly reducing the time consumption.

[0056] Embodiments of this disclosure also provide a parallel address translation device based on a memory management unit.

[0057] Figure 5 This is a schematic block diagram illustrating a parallel address translation device 500 according to an exemplary embodiment.

[0058] like Figure 5 As shown, the parallel address translation apparatus 500 includes a request acquisition unit 501 and a translation execution unit 502. The request acquisition unit 501 is configured to acquire a request for invalidating a cache, the request indicating a virtual address space for which invalidation is to be performed. The translation execution unit 502 is configured to perform respective address translation operations in parallel for the virtual address space, via at least two free entries from a plurality of entries, based on a preset estimated page size. The starting virtual addresses for which the at least two free entries perform their respective address translation operations differ by an estimated page size, which is determined based on any of a plurality of page sizes supported by the memory management unit.

[0059] In the address translation operation, the result of the address translation operation is determined based on a comparison between the obtained actual page size and the estimated page size, wherein: in response to the actual page size being equal to the estimated page size, the result of the address translation operation is transmitted to the lower-level module used to perform the invalidation operation; in response to the actual page size being less than the estimated page size, multiple address translation operations are performed sequentially on the virtual addresses in the estimated page size according to the actual page size until all virtual addresses corresponding to the estimated page size have completed address translation, and the result of the multiple address translation operations is transmitted to the lower-level module; and in response to the actual page size being greater than the estimated page size, the result obtained from the first address translation operation completed among at least two free entries is transmitted to the lower-level module.

[0060] The operations of the request acquisition unit 501 and the translation execution unit 502 described above can be combined with those described above. Figure 2 The operations of steps S201 and S202 are the same. Therefore, the details of each aspect will not be elaborated here.

[0061] In some embodiments, the above-mentioned at least two free entries include a first entry and a second entry. Accordingly, the translation execution unit 502 may further include an initial address determination unit 5020, configured to determine the initial starting virtual address of the first entry and the second entry respectively, wherein the initial starting virtual address of the first entry is the same as the target starting virtual address, and the initial starting virtual address of the second entry is the sum of the target starting virtual address and the estimated page size.

[0062] While specific functions have been discussed above with reference to specific modules, it should be noted that the functions of the modules discussed herein can be divided into multiple modules, and / or at least some functions of multiple modules can be combined into a single module. The specific actions performed by the modules discussed herein include the specific module itself performing the action, or alternatively, the specific module calling or otherwise accessing another component or module that performs the action (or performs the action in conjunction with the specific module). Therefore, a specific module performing an action can include the specific module performing the action itself and / or another module that performs the action, called or otherwise accessed by the specific module.

[0063] It should also be understood that the above regarding Figure 5 The described modules can be implemented in hardware or in hardware in combination with software and / or firmware. For example, these modules can be implemented as computer program code / instructions configured to execute in one or more processors and stored in a computer-readable storage medium. Alternatively, these modules can be implemented as hardware logic / circuit. For example, these modules can be implemented together in a System on Chip (SoC). An SoC may include an integrated circuit chip (which includes one or more components in a processor (e.g., a Central Processing Unit (CPU), microcontroller, microprocessor, digital signal processor (DSP), etc.), memory, one or more communication interfaces, and / or other circuitry) and may optionally execute received program code and / or include embedded firmware to perform functions.

[0064] According to one aspect of this disclosure, a computer device is provided, including a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0065] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0066] According to one aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0067] In the following text, combined with Figure 6 Illustrative examples describing such computer devices, non-transitory computer-readable storage media, and computer program products.

[0068] Figure 6 An example configuration of a computer device 600 that can be used to implement the methods described herein is shown.

[0069] Computer device 600 can be a variety of different types of devices. Examples of computer device 600 include, but are not limited to: desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablet computers, cellular or other wireless phones (e.g., smartphones), notebook computers, mobile stations), wearable devices (e.g., glasses, watches), entertainment devices (e.g., entertainment appliances, set-top boxes communicatively coupled to a display device, game consoles), televisions or other display devices, automotive computers, and so on.

[0070] Computer device 600 may include at least one processor 602, memory 604, multiple communication interfaces 606, display device 608, other input / output (I / O) devices 610, and one or more mass storage devices 612 capable of communicating with each other, such as via system bus 614 or other suitable connections.

[0071] Processor 602 may be a single processing unit or multiple processing units, and all processing units may include single or multiple computing units or multiple cores. Processor 602 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operating instructions. Among other capabilities, processor 602 may be configured to acquire and execute computer-readable instructions stored in memory 604, mass storage device 612, or other computer-readable media, such as program code of operating system 616, program code of application program 618, program code of other program 620, etc.

[0072] Memory 604 and mass storage device 612 are examples of computer-readable storage media for storing instructions that are executed by processor 602 to perform the various functions described above. For example, memory 604 may generally include both volatile and non-volatile memory (e.g., RAM, ROM, etc.). Furthermore, mass storage device 612 may generally include hard disk drives, solid-state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CDs, DVDs), storage arrays, network-attached storage, storage area networks, etc. Both memory 604 and mass storage device 612 may be collectively referred to herein as memory or computer-readable storage media, and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code, which may be executed by processor 602 as a specific machine configured to perform the operations and functions described in the examples herein.

[0073] Multiple programs can be stored on mass storage device 612. These programs include operating system 616, one or more application programs 618, other programs 620, and program data 622, and they can be loaded into memory 604 for execution. Examples of such application programs or program modules may include, for example, Figure 2 The computer program logic (e.g., computer program code or instructions) of the methods shown and / or other embodiments described herein.

[0074] Although Figure 6 The modules 616, 618, 620, and 622, or portions thereof, are illustrated as being stored in memory 604 of computer device 600; however, modules 616, 618, 620, and 622 may be implemented using any form of computer-readable medium accessible by computer device 600. As used herein, “computer-readable medium” includes at least two types of computer-readable media: computer-readable storage media and communication media.

[0075] Computer-readable storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD, or other optical storage devices, magnetic cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or any other non-transmission medium that can be used to store information for access by computer devices. In contrast, communication media can embody computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms. Computer-readable storage media as defined herein do not include communication media.

[0076] One or more communication interfaces 606 are used for exchanging data with other devices, such as via a network, direct connection, etc. Such communication interfaces can be one or more of the following: any type of network interface (e.g., a network interface card (NIC)), wired or wireless (such as IEEE 802.11 Wireless LAN (WLAN)) wireless interface, Wi-MAX interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth. TM Interfaces, near field communication (NFC) interfaces, etc. Communication interface 606 can facilitate communication across various network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. Communication interface 606 can also provide communication with external storage devices (not shown) such as storage arrays, network-attached storage, storage area networks, etc.

[0077] In some examples, a display device 608, such as a monitor, may be included for displaying information and images to the user. Other I / O devices 610 may be devices that receive various inputs from the user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and so on.

[0078] The technologies described herein can be supported by these various configurations of computer device 600, and are not limited to specific examples of the technologies described herein. For example, the functionality can also be implemented wholly or partially on a “cloud” using a distributed system. A cloud includes and / or represents a platform for resources. The platform abstracts the underlying functionality of the cloud’s hardware (e.g., servers) and software resources. Resources may include applications and / or data that can be used when performing computational processing on a server remote from computer device 600. Resources may also include services provided via the Internet and / or via subscriber networks such as cellular or Wi-Fi networks. The platform can abstract resources and functionality to connect computer device 600 to other computer devices. Therefore, the implementation of the functionality described herein can be distributed throughout the cloud. For example, the functionality can be implemented partly on computer device 600 and partly through a platform that abstracts the functionality of the cloud.

Claims

1. A parallel address translation method based on a memory management unit, characterized in that, The memory management unit includes multiple entries for performing address translation, and the method includes: Obtain a request for invalidating the cache, the request indicating the virtual address space where the invalidation operation is to be performed; For the virtual address space, each address translation operation is performed in parallel based on a preset estimated page size via at least two free entries from the plurality of entries, wherein the starting virtual addresses of the at least two free entries performing their respective address translation operations differ from the estimated page size, and the estimated page size is determined based on any one of a plurality of page sizes supported by the memory management unit; In the address translation operation, the result of the address translation operation is determined based on a comparison between the obtained actual page size and the estimated page size, wherein: In response to the actual page size being equal to the estimated page size, the result of the address translation operation is transmitted to the lower-level module for performing the invalidation operation; In response to the actual page size being smaller than the estimated page size, multiple address translation operations are performed sequentially on the virtual addresses within the estimated page size according to the actual page size, until all virtual addresses corresponding to the estimated page size have completed address translation, so as to transmit the results of the multiple address translation operations to the lower-level module; and In response to the actual page size being greater than the estimated page size, the result obtained by the first of the at least two free entries that has completed the address translation operation is transmitted to the lower-level module.

2. The method according to claim 1, characterized in that, The virtual address space includes a target starting virtual address, and the at least two free entries include a first entry and a second entry. The parallel execution of address translation operations based on a preset inferred page size further includes: Determine the initial starting virtual address for each of the first entry and the second entry, wherein the initial starting virtual address of the first entry is the same as the target starting virtual address, and the initial starting virtual address of the second entry is the sum of the target starting virtual address and the estimated page size.

3. The method according to claim 2, characterized in that, The virtual address space also includes a target length, which includes multiple sub-target lengths, each corresponding to a different page size, such that the inferred page size is selected from any of the multiple page sizes.

4. The method according to claim 3, characterized in that, After the first entry and the second entry have completed the address translation operation for the current sub-target length in parallel, the address translation operation for the next sub-target length is performed in parallel.

5. The method according to claim 3, characterized in that, The multiple page sizes include 4K, 64K, and 2M, and the estimated page size is preset to 64K.

6. The method according to any one of claims 1 to 5, characterized in that, The memory management unit includes a filtering output module, which is used to receive the results of the address translation operation transmitted by each of the at least two free entries, and discard the currently received result when the currently received result is the same as the previously received result.

7. A parallel address translation device based on a memory management unit, characterized in that, The memory management unit includes multiple entries for performing address translation, and the apparatus includes: The request retrieval unit is configured to retrieve a request for invalidating a cache, the request indicating the virtual address space where the invalidation operation is to be performed; The translation execution unit is configured to perform its respective address translation operations in parallel with respect to the virtual address space via at least two free entries of the plurality of entries, based on a preset estimated page size, wherein the starting virtual addresses of the at least two free entries for performing their respective address translation operations differ from the estimated page size, and the estimated page size is determined based on any one of a plurality of page sizes supported by the memory management unit. In the address translation operation, the result of the address translation operation is determined based on a comparison between the obtained actual page size and the estimated page size, wherein: In response to the actual page size being equal to the estimated page size, the result of the address translation operation is transmitted to the lower-level module for performing the invalidation operation; In response to the actual page size being smaller than the estimated page size, multiple address translation operations are performed sequentially on the virtual addresses within the estimated page size according to the actual page size, until all virtual addresses corresponding to the estimated page size have completed address translation, so as to transmit the results of the multiple address translation operations to the lower-level module; and In response to the actual page size being greater than the estimated page size, the result obtained by the first of the at least two free entries that has completed the address translation operation is transmitted to the lower-level module.

8. A computer device, characterized in that, The computer device includes: At least one processor; A memory having a computer program stored thereon, wherein, when executed by the at least one processor, the computer program causes the at least one processor to perform the method of any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-6.

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