A quantum circuit conversion method, system, electronic device, and storage medium

Abstract

This invention discloses a quantum circuit conversion method, system, electronic device, and storage medium, relating to the field of quantum circuit conversion technology. The method includes: extracting feature vectors of logical quantum circuits based on initial qubit mapping; inputting these feature vectors into a pre-trained decision tree to obtain recommended parameters for the circuit conversion algorithm. This decision tree is constructed from a training set, where the feature vector of each sample corresponds to its optimal parameters, i.e., the parameters that minimize the number of physical circuit gates; configuring the circuit conversion algorithm using the recommended parameters to convert the logical circuits into physical circuits, ensuring that all two-qubit gates satisfy the quantum computer's connectivity graph constraints and are functionally equivalent. This invention enables adaptive parameter configuration through feature vectors and a decision tree, effectively improving circuit conversion quality, significantly reducing the number of physical circuit gates, and improving quantum program execution efficiency while ensuring functional equivalence and connectivity.

Description

Technical Field

[0001] This invention relates to the field of quantum circuit conversion technology, and in particular to a quantum circuit conversion method, system, electronic device, and storage medium. Background Technology

[0002] When designing quantum programs, it is usually assumed that two-qubit gate operations can be performed between any pair of qubits. However, practical quantum computers have strict connectivity constraints on two-qubit gates. Therefore, before a quantum computer executes a quantum program, the input logical quantum circuit must be converted into an executable physical quantum circuit that meets the hardware connectivity constraints. This process requires the introduction of redundant quantum gates. The converted physical quantum circuit must not only satisfy the connectivity constraints of the quantum computer but also be functionally equivalent to the original logical quantum circuit. Although a logical circuit usually corresponds to multiple feasible physical circuit implementations, the degree of redundancy introduced by different implementations varies significantly. Therefore, the core objective of the circuit conversion algorithm is to find a physical circuit solution with as little redundancy as possible.

[0003] Existing line conversion algorithms generally include a large number of adjustable parameters to control key factors such as search strategies and cost function weights during the conversion process. The current mainstream practice in the industry is to pre-set these parameters to fixed values ​​based on experience and then apply them to the conversion process of all input lines. This static parameter configuration method can guarantee the implementation of the conversion function to a certain extent, but its parameter selection does not consider the impact of the structural characteristics of different logic lines on the different behavior of the algorithm.

[0004] This fixed parameter setting leads to a significant performance penalty for the algorithm because the optimal parameter configuration often differs for input circuits with varying structures. For example, some circuits with local connectivity characteristics may require parameter configurations that emphasize local search, while circuits with global interaction characteristics may require parameter settings that focus on global optimization. Empirical fixed parameter practices cannot adapt to the changing characteristics of different circuits, preventing the conversion algorithm from consistently generating the optimal physical circuit, thus limiting the execution efficiency of quantum programs on real hardware.

[0005] To overcome the performance limitations imposed by fixed parameter settings in existing technologies, there is an urgent need for an intelligent conversion method capable of adaptively adjusting parameters based on the characteristics of the input line. This invention is proposed against this technological backdrop, aiming to achieve dynamic optimization of parameter settings through a data-driven approach, thereby significantly improving the overall performance of the line conversion algorithm. Summary of the Invention

[0006] The technical problem to be solved by this invention is to address the shortcomings of existing technologies, and specifically provides a quantum circuit conversion method, system, electronic device, and storage medium, as detailed below:

[0007] 1) In a first aspect, the present invention provides a quantum circuit conversion method, the specific technical solution of which is as follows:

[0008] Based on the initial qubit mapping, the feature vector of the logic quantum circuit to be converted is extracted;

[0009] The feature vector of the logic quantum circuit to be converted is input into a pre-trained decision tree to obtain the recommended parameters of the circuit conversion algorithm. The pre-trained decision tree is constructed based on the training set, which contains the feature vectors of multiple logic quantum circuit samples and the optimal parameter values ​​of the circuit conversion algorithm corresponding to each sample. The optimal parameter values ​​are the parameters that minimize the number of gates in the physical quantum circuit obtained after conversion.

[0010] Configure the parameters of the circuit conversion algorithm to the recommended parameters, and use the configured circuit conversion algorithm to convert the logical quantum circuit to be converted to generate a physical quantum circuit. In the physical quantum circuit, the physical quantum bit pairs operated by all two-qubit gate operations are elements of the edges in the quantum computer's connected graph, and the physical quantum circuit is functionally equivalent to the logical quantum circuit to be converted.

[0011] The beneficial effects of the quantum circuit conversion method provided by this invention are as follows:

[0012] By extracting the feature vectors of the logical quantum circuits to be converted and adaptively recommending optimal parameters for the circuit conversion algorithm using a pre-trained decision tree model, precise matching between parameter configuration and input circuit characteristics is achieved. This data-driven parameter adjustment mechanism effectively overcomes the shortcomings of existing technologies where fixed parameter settings cannot adapt to different circuit structure characteristics, and can dynamically select the most suitable parameter values ​​for logical quantum circuits with different characteristics. By configuring the parameters of the circuit conversion algorithm with those recommended by the decision tree, the optimization effect of the circuit conversion process can be significantly improved, and the number of quantum gates in the generated physical quantum circuit can be effectively reduced. This directly reduces the depth and complexity of the physical quantum circuit, and reduces the time and resource overhead required for execution. Ultimately, this method significantly improves the quality and efficiency of circuit conversion while ensuring that the physical quantum circuit is completely functionally equivalent to the original logical quantum circuit and satisfies the quantum computer connectivity graph constraints, laying a solid foundation for the efficient execution of quantum programs on real hardware.

[0013] Based on the above scheme, the quantum circuit conversion method of the present invention can be further improved as follows.

[0014] Furthermore, the process of determining the optimal parameter values ​​in the training set includes:

[0015] For each logical quantum circuit sample, all parameter values ​​are traversed in the parameter value set of the circuit conversion algorithm. Each parameter value is used to convert the logical quantum circuit sample to obtain the corresponding physical quantum circuit. The parameter value that minimizes the number of gates in the physical quantum circuit is selected as the optimal parameter value for the logical quantum circuit sample.

[0016] The beneficial effects of adopting the above-mentioned further scheme are as follows: For each logical quantum circuit sample, by comprehensively traversing all possible parameter configurations in the parameter value set and actually executing the circuit conversion process, the impact of each parameter value on the conversion result can be objectively and accurately evaluated. By selecting the parameter value that minimizes the number of gates in the physical quantum circuit as the optimal parameter value, the accuracy and reliability of the training sample labeling are ensured. This method provides precise supervision signals for the decision tree model, enabling the model to learn the true mapping relationship between circuit features and optimal parameters. The training set constructed based on these rigorously experimentally determined optimal parameter values ​​can effectively improve the prediction accuracy and generalization ability of the decision tree model, thereby laying a solid foundation for subsequent parameter recommendation and ultimately achieving overall optimization of circuit conversion quality.

[0017] Furthermore, the configured circuit conversion algorithm is used to convert the logical quantum circuit to be converted, generating a physical quantum circuit, including:

[0018] Each quantum gate in the logical quantum circuit to be converted is processed sequentially. For a single-qubit gate in the logical quantum circuit to be converted, the single-qubit gate is directly added to the physical quantum circuit. For a two-qubit gate in the logical quantum circuit to be converted, the current qubit mapping of the two qubit gates is updated by introducing one or more swapping gate operations, and the swapping gate operations are added to the physical quantum circuit until the two qubit gates satisfy the restrictions of the quantum computer's connected graph under the updated qubit mapping. Then, the physical operations corresponding to the two qubit gates are added to the physical quantum circuit.

[0019] The initial qubit mapping is defined as both the initial state of the current qubit mapping used when processing the first single-qubit gate and the initial state of the current qubit mapping used when processing the first two-qubit gate.

[0020] The beneficial effects of adopting the above-mentioned further scheme are as follows: by sequentially processing each quantum gate in the logical quantum circuit and distinguishing between different processing strategies for single and double qubit gates, both the orderliness of the conversion process and targeted optimization are maintained. When processing two-qubit gates, by dynamically introducing swap gate operations and updating the current qubit mapping in real time, it is ensured that each two-qubit gate can be executed under the condition of satisfying the connectivity graph constraints of the quantum computer. In particular, the initial state of the current qubit mapping when processing the first single-qubit gate and the first two-qubit gate is uniformly set as the initial qubit mapping, ensuring the benchmark consistency and repeatability of the conversion process. This method can minimize redundant operations through the optimal swap gate introduction strategy while ensuring that the physical quantum circuit is completely equivalent to the original logical quantum circuit, effectively controlling the total number of gates in the physical quantum circuit, thereby improving the execution efficiency of the quantum program on real hardware.

[0021] Furthermore, the characteristic vector of the logic quantum circuit to be converted includes at least one of the following: the number of gates, gate density, number of layers, average layer size, maximum layer size, minimum layer size, and information entropy of the logic quantum circuit to be converted.

[0022] The feature vector of the quantum logic circuit to be converted also includes: the in-layer gate density of the specified layer of the quantum logic circuit to be converted, the maximum in-layer gate distance of the specified layer, the minimum in-layer gate distance of the specified layer, and the number of in-layer gates of the specified layer, wherein the number of specified layers is determined by a predefined truncation threshold.

[0023] The beneficial effects of adopting the above-mentioned further scheme are as follows: By incorporating global features such as the number of gates, gate density, and number of layers, the overall scale and topological characteristics of the logical quantum circuit can be comprehensively characterized. Simultaneously, by introducing local features such as the gate density and maximum / minimum distance between gates within a specified layer, the local connectivity and structural distribution of each layer of the circuit can be precisely reflected. This feature representation method combining global and local features enables the decision tree model to more comprehensively and accurately understand the structural characteristics of the input circuit. Controlling the number of specified layers through a predefined truncation threshold ensures both controllable feature vector dimensions and consistency in feature representation across circuits of different depths. This carefully designed feature vector provides the decision tree model with rich and standardized input information, thereby significantly improving the accuracy and adaptability of the circuit conversion algorithm parameter recommendation.

[0024] 2) In a second aspect, the present invention also provides a quantum circuit conversion system, the specific technical solution of which is as follows:

[0025] It includes a feature vector acquisition module, a recommendation parameter acquisition module, and a transformation module;

[0026] The feature vector acquisition module is used to: extract the feature vector of the logic quantum circuit to be converted based on the initial quantum bit mapping;

[0027] The recommended parameter acquisition module is used to: input the feature vector of the logic quantum circuit to be converted into a pre-trained decision tree to obtain the recommended parameters of the circuit conversion algorithm. The pre-trained decision tree is constructed based on the training set, which contains the feature vectors of multiple logic quantum circuit samples and the optimal parameter values ​​of the circuit conversion algorithm corresponding to each sample. The optimal parameter values ​​are the parameters that minimize the number of gates in the physical quantum circuit obtained after conversion.

[0028] The conversion module is used to: configure the parameters of the circuit conversion algorithm to the recommended parameters, and use the configured circuit conversion algorithm to convert the logical quantum circuit to be converted to generate a physical quantum circuit. In the physical quantum circuit, the physical quantum bit pairs operated by all two-qubit gate operations are elements of the edges in the quantum computer's connected graph, and the physical quantum circuit is functionally equivalent to the logical quantum circuit to be converted.

[0029] Based on the above scheme, the quantum circuit conversion system of the present invention can be further improved as follows.

[0030] Furthermore, it also includes an optimal parameter value determination module, which is used for:

[0031] For each logical quantum circuit sample, all parameter values ​​are traversed in the parameter value set of the circuit conversion algorithm. Each parameter value is used to convert the logical quantum circuit sample to obtain the corresponding physical quantum circuit. The parameter value that minimizes the number of gates in the physical quantum circuit is selected as the optimal parameter value for the logical quantum circuit sample.

[0032] Furthermore, the conversion module is specifically used for:

[0033] Each quantum gate in the logical quantum circuit to be converted is processed sequentially. For a single-qubit gate in the logical quantum circuit to be converted, the single-qubit gate is directly added to the physical quantum circuit. For a two-qubit gate in the logical quantum circuit to be converted, the current qubit mapping of the two qubit gates is updated by introducing one or more swapping gate operations, and the swapping gate operations are added to the physical quantum circuit until the two qubit gates satisfy the restrictions of the quantum computer's connected graph under the updated qubit mapping. Then, the physical operations corresponding to the two qubit gates are added to the physical quantum circuit.

[0034] The initial qubit mapping is defined as both the initial state of the current qubit mapping used when processing the first single-qubit gate and the initial state of the current qubit mapping used when processing the first two-qubit gate.

[0035] Furthermore, the characteristic vector of the logic quantum circuit to be converted includes at least one of the following: the number of gates, gate density, number of layers, average layer size, maximum layer size, minimum layer size, and information entropy of the logic quantum circuit to be converted.

[0036] The feature vector of the quantum logic circuit to be converted also includes: the in-layer gate density of the specified layer of the quantum logic circuit to be converted, the maximum in-layer gate distance of the specified layer, the minimum in-layer gate distance of the specified layer, and the number of in-layer gates of the specified layer, wherein the number of specified layers is determined by a predefined truncation threshold.

[0037] 3) In a third aspect, the present invention also provides an electronic device, the electronic device including a processor coupled to a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to enable the electronic device to implement any of the above-mentioned quantum circuit conversion methods.

[0038] 4) In a fourth aspect, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the above-described quantum circuit conversion methods.

[0039] It should be noted that the beneficial effects of the technical solutions of the second to fourth aspects of the present invention and their corresponding possible implementations can be found in the above description of the technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below:

[0041] Figure 1 This is a schematic flowchart of a quantum circuit conversion method according to an embodiment of the present invention;

[0042] Figure 2 This is one of the schematic diagrams of a quantum circuit structure;

[0043] Figure 3 This is the second schematic diagram of a quantum circuit structure;

[0044] Figure 4 Example diagram of a connected graph for a quantum computer;

[0045] Figure 5 This is a schematic diagram of quantum bit mapping;

[0046] Figure 6 This is one of the schematic diagrams of a logic quantum circuit;

[0047] Figure 7 This is the second schematic diagram of a logic quantum circuit;

[0048] Figure 8 This is a schematic diagram of a decision tree;

[0049] Figure 9 This is a schematic diagram of the structure of a quantum circuit conversion system according to an embodiment of the present invention;

[0050] Figure 10 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0051] The principles and features of the present invention are described below. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0052] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0053] like Figure 1 As shown, a quantum circuit conversion method according to an embodiment of the present invention includes the following steps:

[0054] S1. Based on the initial qubit mapping, extract the feature vector of the logic quantum circuit to be converted;

[0055] The feature vector of the quantum logic circuit to be converted includes at least one of the following: number of gates, gate density, number of layers, average layer size, maximum layer size, minimum layer size, and information entropy. The feature vector of the quantum logic circuit to be converted also includes: the in-layer gate density of a specified layer, the maximum in-layer gate distance of a specified layer, the minimum in-layer gate distance of a specified layer, and the number of in-layer gates of a specified layer. The number of specified layers is determined by a predefined cutoff threshold.

[0056] The specific implementation process for extracting the feature vector of the logic quantum circuit to be converted is as follows: the feature vector is initialized as an empty vector to store the feature values ​​obtained in subsequent calculations. The construction of the feature vector aims to comprehensively describe the structural characteristics and topological properties of the logic quantum circuit to be converted under a given initial qubit mapping.

[0057] The process involves counting the number of quantum gates in the quantum circuit to be converted, including single-qubit gates and two-qubit gates. The number of gates reflects the overall size of the quantum circuit. The gate density is calculated as the ratio of the sum of distances between all two-qubit gates in the initial qubit mapping to the total number of gates. Specifically, for each two-qubit gate, the distance is defined as the shortest path length in the quantum computer's connectivity graph between the two physical qubits corresponding to the two logical qubits affected by that gate in the initial qubit mapping. The gate density reflects the average topological span of the two-qubit gates in the quantum circuit. Following the definition of a quantum circuit layer, all quantum gates in the quantum circuit are shifted as far to the left as possible and assigned to different layers. The total number of layers is then counted as the layer number, representing the depth of the quantum circuit. The average number of quantum gates in each layer is calculated as the average layer size. Specifically, the number of gates in each layer is first calculated, and then the arithmetic mean of these numbers is obtained. Find the maximum number of quantum gates in all layers of the logical quantum circuit to be converted, as the maximum layer size; find the minimum number of quantum gates in all layers of the logical quantum circuit to be converted, as the minimum layer size; calculate the entropy, i.e., the information entropy, based on the probability that each logical qubit in the logical quantum circuit to be converted appears in all two-qubit gates. Assuming that the logical quantum circuit to be converted has n logical qubits, for each logical qubit, calculate the probability of it appearing in all two-qubit gates of the logical quantum circuit to be converted. Then, the formula for calculating information entropy is:

[0058]

[0059] Information entropy can reflect the uniformity of the use of qubits in the logic quantum circuit to be converted.

[0060] For any given layer, the ratio of the sum of the distances between all two-qubit gates within that layer under the initial qubit mapping to the number of gates in that layer is taken as the in-layer gate density. This characteristic reflects the average topological span of two-qubit gates within a given layer. For any given layer, the maximum distance between all two-qubit gates within that layer under the initial qubit mapping is taken as the maximum in-layer gate distance. For any given layer, the minimum distance between all two-qubit gates within that layer under the initial qubit mapping is taken as the minimum in-layer gate distance. The number of in-layer gates for any given layer refers to the number of quantum gates in that layer.

[0061] The number of specified layers is determined by a predefined truncation threshold, specifically:

[0062] A predefined positive integer is used as a truncation threshold, representing the maximum number of layers to consider during feature extraction. This threshold is typically set empirically or experimentally to ensure the feature vector captures the local structure of the circuit without causing computational redundancy due to excessive layers. During feature extraction, the system iterates through the layer indices of the logical quantum circuit, starting from layer 1 and continuing until the truncation threshold is reached. For each layer index, the system checks if the layer exists in the logical quantum circuit; if it does, it calculates the layer's intra-layer features, including intra-layer gate density, maximum intra-layer gate distance, minimum intra-layer gate distance, and number of intra-layer gates, and adds these values ​​to the feature vector. If the actual number of layers in the logical quantum circuit is less than the truncation threshold, the system fills the feature vector with default values ​​(e.g., 0) for non-existent layers to ensure dimensionality consistency and algorithm stability. Thus, the number of specified layers is strictly controlled by the predefined truncation threshold, ensuring that the feature vector always contains a fixed number of layer-related features regardless of the actual number of layers in the logical quantum circuit, providing standardized input for subsequent decision tree models. This process is implemented through a programming loop, with clear logic and technical feasibility, ensuring the efficiency and reliability of feature extraction.

[0063] In this context, a designated layer refers to a logical quantum circuit selected during feature extraction to compute layer-specific features. Quantum circuit layers are columns partitioned according to a quantum gate left-shifting rule, with each layer containing a set of quantum gates that can be executed in parallel. During feature extraction, the designated layer indices start from 1 and proceed up to a predefined truncation threshold. These layers capture local topological properties and structural variations of the circuit, such as intra-layer gate density and intra-layer gate distance, thus providing a finer-grained circuit description. By analyzing designated layers, the algorithm can better adapt to quantum circuits of varying complexity, improving the accuracy of parameter recommendations.

[0064] The predefined truncation threshold is a positive integer parameter set before algorithm execution to determine the maximum number of specified layers considered in feature extraction. This threshold is typically selected based on historical data or experimental optimization to balance feature expressiveness and computational complexity. The truncation threshold limits the dimensionality of the feature vector, preventing feature redundancy or overfitting due to excessive layers, while ensuring effective processing of deep circuits. In implementation, the truncation threshold is passed as an input parameter to the feature extraction function, directly controlling the traversal range of specified layers, thereby ensuring the consistency and repeatability of the feature extraction process.

[0065] S2. Input the feature vector of the logic quantum circuit to be converted into the pre-trained decision tree to obtain the recommended parameters of the circuit conversion algorithm. The pre-trained decision tree is constructed based on the training set, which contains the feature vectors of multiple logic quantum circuit samples and the optimal parameter values ​​of the circuit conversion algorithm corresponding to each sample. The optimal parameter values ​​are the parameters that minimize the number of gates in the physical quantum circuit obtained after conversion.

[0066] The feature vector of the quantum logic circuit to be converted is input into a pre-trained decision tree to obtain the recommended parameters for the circuit conversion algorithm. The specific implementation process is as follows:

[0067] S20. Load the pre-trained decision tree. The pre-trained decision tree is a machine learning model built through the historical training process. Each non-leaf node in its tree structure corresponds to a line feature used to divide the data. Each branch represents a value range of the feature, while each leaf node stores a specific line conversion algorithm parameter value.

[0068] S21. After obtaining the feature vector of the logic quantum circuit to be converted, traverse the decision tree starting from the root node. At each non-leaf node, read the feature identifier corresponding to that node, and then extract the corresponding feature value from the input feature vector based on the identifier. Compare this actual feature value with the branch conditions of the current node, and select the corresponding branch path based on the comparison result. This process continues recursively until a leaf node is reached. Reaching a leaf node specifically means: starting from the root node of the decision tree, based on the specific values ​​of each feature in the feature vector of the input logic quantum circuit to be converted, performing branch selection according to the feature judgment conditions set at each non-leaf node, traversing downwards layer by layer, and finally reaching the terminal node when no further branching is possible. This terminal node is the leaf node, and the parameter value stored in it is the final output recommended parameter.

[0069] S22. After reaching the leaf node, read the parameter values ​​stored in that node. These parameter values ​​are the recommended parameters of the line conversion algorithm recommended by the decision tree for the current input line feature vector.

[0070] Circuit conversion algorithms are computational processes that convert logical quantum circuits into physical quantum circuits. These algorithms take logical quantum circuits, initial qubit mappings, a quantum computer connectivity graph, and a set of adjustable parameters as input. Their output is a functionally equivalent physical quantum circuit that conforms to the connectivity constraints of the target quantum hardware. The core of this conversion process lies in intelligently introducing swap gate operations to dynamically adjust the qubit mappings, ensuring that all two-qubit gates in the logical circuit can be executed on adjacent physical qubit pairs in the physical circuit. Common circuit conversion algorithms include SABRE, which typically contain multiple configurable parameters whose values ​​significantly affect the quality and efficiency of the final generated physical circuit.

[0071] The recommended parameters for the circuit conversion algorithm refer to the optimal parameter configuration output by a pre-trained decision tree model for a specific logical quantum circuit to be converted. Essentially, these recommended parameters are optimal parameter values ​​learned from historical data. Specifically, during the training phase of the decision tree, by testing a large number of logical quantum circuit samples, the optimal parameter value is determined for each sample, minimizing the number of gates in the converted physical quantum circuit. The decision tree model learns the mapping relationship between circuit features and these optimal parameter values. Therefore, when a new logical quantum circuit is input, the parameters predicted by the decision tree based on its extracted feature vectors are recommended parameters derived from historical best practices, aiming to achieve or approach optimal performance for the current circuit conversion.

[0072] S3. Configure the parameters of the circuit conversion algorithm to the recommended parameters, and use the configured circuit conversion algorithm to convert the logical quantum circuit to be converted, generating a physical quantum circuit. Specifically, this includes:

[0073] S30. Sequentially process each quantum gate in the logical quantum circuit to be converted. For a single-qubit gate in the logical quantum circuit to be converted, directly add the single-qubit gate to the physical quantum circuit. For a two-qubit gate in the logical quantum circuit to be converted, update the current qubit mapping of the two-qubit gate by introducing one or more swapping gate operations, and add the swapping gate operations to the physical quantum circuit until the two-qubit gate satisfies the quantum computer connectivity graph constraint under the updated qubit mapping. Then, add the physical operations corresponding to the two-qubit gate to the physical quantum circuit. Specifically:

[0074] S300. Initialize the current qubit mapping to the given initial qubit mapping and create an empty physical quantum circuit to store the output result. Then, process the quantum gates one by one according to their order of appearance in the logic quantum circuit to be converted. For each quantum gate, first determine its type. If the current processing is a single-qubit gate, directly determine the physical qubit that the gate operates on based on the current qubit mapping, and then add the corresponding single-qubit gate operation to the physical quantum circuit. This process does not change the current qubit mapping.

[0075] S301. If the current operation involves a two-qubit gate, a complex conversion process is required. First, check whether the two-qubit gate satisfies the connectivity restrictions of the quantum computer's graph under the current qubit mapping, i.e., determine whether the two physical qubits affected by the gate are directly connected in the connectivity graph. If the restrictions are met, the corresponding two-qubit gate operation is directly added to the physical quantum circuit. If the restrictions are not met, a swap gate operation needs to be introduced to adjust the qubit mapping.

[0076] S302. Calculate the sequence of swap gates to be introduced, which progressively adjusts the current qubit mapping to a state that makes the target two-qubit gate executable. For each swap gate to be introduced, first add the swap gate operation to the physical quantum circuit, then update the current qubit mapping to reflect the changes brought about by the swap operation. This process is repeated until the target two-qubit gate satisfies the connectivity constraints under the current qubit mapping.

[0077] S303. Add the physical operations corresponding to the two-qubit gates that meet the constraints to the physical quantum circuit, and continue processing the next quantum gate in the logic quantum circuit to be converted. The entire process ensures that the final physical quantum circuit is functionally equivalent to the original logic quantum circuit to be converted, and that all two-qubit gate operations comply with the connectivity constraints of the quantum computer.

[0078] For example, the logic quantum circuit to be converted contains three logic qubits. The order of the quantum gates in the circuit is: one acting on... Single-qubit gate Next is a two-qubit gate. In the quantum computer connectivity graph, physical qubits It is linearly connected, i.e., the set of edges This means that two-qubit gates can only be used in adjacent physical bit pairs. or Execution on top. Initial qubit mapping. Defined as , , Therefore, let's set the current qubit mapping as the initial mapping. Create an empty physical quantum circuit. When dealing with the first quantum gate At that time, it is determined that the gate is a single-qubit gate. Based on the current qubit mapping... logical qubit Corresponding physical qubit Directly perform physical operations Added to physical quantum circuits The current qubit mapping remains unchanged and is still in the middle. At this point, the physical quantum circuit Include: When dealing with the second quantum gate At that time, it is determined that the gate is a two-qubit gate. Based on the current qubit mapping... The physical operation corresponding to this door is Check the edges. Does it exist in the connected graph of a quantum computer? Yes, it exists. Physical operations are directly performed because the connectivity constraint is satisfied. Added to physical quantum circuits In the middle. At this moment, the physical quantum circuit Include: Assume the next gate in the quantum circuit to be converted is Dealing with the third quantum gate At that time, it is determined that the gate is a two-qubit gate. Based on the current qubit mapping... The physical operation corresponding to this door is Check the edges. Does it exist in the connected graph of a quantum computer? In this case, they do not exist because they are not directly connected. A sequence of swap gates must be computed to adjust the mapping. A feasible strategy is to find the shortest path. From arrive The shortest path is This can be achieved by introducing a or To achieve this. Assume the algorithm chooses to introduce... Switch gate operation Added to physical quantum circuits Application After that, the new mapping for:

[0079] (Unchanged, because) Mapped to (Not involved in the exchange);

[0080] (turn out to be Mapped to ,and After the swap, it is now mapped to );

[0081] (turn out to be Mapped to ,and After the swap, it is now mapped to );

[0082] Now, regarding the door The corresponding physical operation is Check the edges. Does it exist in If so, and connectivity constraints are satisfied, then physical operations will be performed. Added to physical quantum circuits In the middle. At this moment, the physical quantum circuit Include: .

[0083] Through the above sequential processing, the logical quantum circuit to be converted is transformed into a physical quantum circuit. The final physical quantum circuit is then obtained. All two-qubit gates , and All of these act on the edges allowed in the connected graph of the quantum computer. or Although a redundancy was introduced. It's a door, but it guarantees the physical quantum circuitry. Functionally, it is completely equivalent to the original quantum circuit to be converted. This example clearly demonstrates how hardware connectivity limitations can be overcome by dynamically adjusting the qubit mapping.

[0084] Quantum gates are the fundamental operational units in quantum computing, performing computational functions by transforming the states of qubits. Based on the number of qubits involved, quantum gates can be divided into single-qubit gates and two-qubit gates. Single-qubit gates change the state of only one qubit, such as Hadamard and Pauli gates; two-qubit gates change the state of two qubits simultaneously, such as controlled NOT gates and commutation gates. In quantum circuits, each quantum gate has a definite mathematical representation and physical implementation, serving as a fundamental component for constructing quantum algorithms.

[0085] The swapping gate operation is a special type of two-qubit gate that swaps the quantum states of two qubits. Mathematically, the swapping gate can be precisely represented in matrix form, and its effect is to completely interchange the quantum states of the two qubits. During circuit switching, the swapping gate operation is introduced into the physical quantum circuit as a redundant gate. By changing the relative positions between the qubits, the qubit mapping is adjusted, thus enabling a two-qubit gate that originally did not meet the connectivity constraint to satisfy the execution conditions under the new mapping.

[0086] The quantum computer connectivity graph is a mathematical model that uses graph theory to describe the connections between physical qubits in a quantum computer. This graph is represented as G equal to V and E, where V is the set of physical qubits, and E is the set of edges representing pairs of qubits that can directly perform two-qubit gate operations. Two-qubit gate operations can only be performed between physical qubit pairs directly connected by edges in the graph. This connectivity constraint is a crucial characteristic of practical quantum hardware and a core problem that circuit switching algorithms need to address.

[0087] Physical operations refer to the quantum gate operations actually executed in the physical quantum circuitry. These operations must conform to the hardware constraints of the target quantum computer. Each physical operation corresponds to a specific physical qubit, and a two-qubit physical operation can only be performed on physical qubit pairs that are directly connected in the quantum computer's connectivity graph. Physical operations are functionally equivalent to logical operations, but due to hardware connectivity limitations, additional swap gate operations may need to be introduced into the physical circuitry to ensure that all two-qubit operations can be legally executed.

[0088] The initial qubit map refers to both the initial state of the current qubit map used when processing the first single-qubit gate and the initial state of the current qubit map used when processing the first two-qubit gate. For example, the initial qubit map... Create an empty physical quantum circuit and set the initial state of the current qubit mapping to this initial qubit mapping. When processing the first quantum gate in a logical quantum circuit sequentially, i.e., the single-qubit gate... At that time, the current state of the qubit mapping it relies on is the same state set during initialization, that is, the initial qubit mapping. Based on this mapping, logical qubits can be retrieved. Corresponding to physical qubits Then physical operation Added to the physical quantum circuit. Crucially, processing a single qubit gate does not alter the current qubit mapping. Therefore, after the first gate is processed, the current qubit mapping retains its initial state. Next, we begin processing the next gate in the logical quantum circuit, namely the first two-qubit gate. At this point, the current qubit mapping used for checking and operations is the state after processing the previous gate. Since the previous gate was a single-qubit gate, it did not change the mapping state. Therefore, the current qubit mapping is completely consistent with the initial state and the state when processing the first single-qubit gate; it is still the initial qubit mapping. Based on this mapping, determine The corresponding physical operation should be Upon verification, the operation complies with the limitations of the connected graph in a quantum computer. Therefore, it was directly performed... It is added to the physical quantum circuit. Processing an executable two-qubit gate does not change the current qubit mapping; therefore, after processing the first two-qubit gate, the current qubit mapping remains unchanged. This initial state.

[0089] In this context, the physical qubit pairs operated by all two-qubit gate operations in the physical quantum circuit are elements of the edges in the quantum computer's connected graph, and the physical quantum circuit is functionally equivalent to the logic quantum circuit to be converted.

[0090] In a quantum computer's connected graph, an element of an edge refers to a specific member of the edge set, namely an undirected edge directly connecting two specific physical qubits. This edge represents the physical channel through which the hardware topology of the target quantum computer allows the execution of two-qubit gate operations. Specifically, quantum hardware can only actually perform two-qubit logic operations, such as NOT gates or swapping gates, between a pair of physical qubits if they are directly connected by such an edge. For example, in a linearly connected graph of three qubits, the edge elements might include edges connecting v0 and v1 and v1 and v2. This means that two-qubit gates can only be executed on v0 and v1 or v1 and v2, and not directly between v0 and v2 which are not directly connected. Therefore, all physical qubit pairs that act on two-qubit gate operations in a physical quantum circuit must strictly correspond to the elements of these edges to ensure that the generated circuit can run on real, constrained hardware.

[0091] Functional equivalence means that the physical quantum circuit obtained after conversion and the logical quantum circuit to be converted, although they may differ in specific gate sequences and qubit mappings, achieve completely identical input-to-output quantum state transformations. This implies that for any possible initial quantum state input, the final quantum state produced after the two circuits are executed should theoretically be exactly the same, ensuring that the classical computation results obtained based on that quantum state are identical. The realization of functional equivalence typically requires rigorous mathematical proof or circuit equivalence verification to ensure that all introduced redundant switching gate operations are ultimately compensated or canceled by subsequent gate operations, thus not changing the net effect of the entire computation process. This is the fundamental criterion for evaluating the correctness of circuit conversion algorithms, guaranteeing that the user-designed quantum program can be executed accurately and without error on actual physical devices.

[0092] Optionally, in the above technical solution, the process of determining the optimal parameter values ​​in the training set includes:

[0093] For each logical quantum circuit sample, all parameter values ​​are iterated through in the parameter value set of the circuit conversion algorithm. Each parameter value is used to convert the logical quantum circuit sample to obtain the corresponding physical quantum circuit. The parameter value that minimizes the number of gates in the physical quantum circuit is selected as the optimal parameter value for the logical quantum circuit sample. Specifically:

[0094] 1) Obtain a predefined set of parameter values, which contains all configurable parameter combinations to be tested for the circuit conversion algorithm. For each logical quantum circuit sample in the training set, the system initializes a temporary variable to record the optimal parameters and the corresponding number of physical quantum circuit gates.

[0095] 2) Begin iterating through each parameter value in the parameter value set. For the currently tested parameter value, the system calls the circuit conversion algorithm, using this parameter value as an input parameter. The circuit conversion algorithm executes the specific circuit conversion process based on the currently tested parameter value, the logical quantum circuit sample, the initial qubit mapping, and the quantum computer connectivity graph, ultimately generating a corresponding physical quantum circuit.

[0096] 3) After obtaining the physical quantum circuit, its quality needs to be evaluated. The core indicator of the evaluation is the total number of gates in the physical quantum circuit. The system will accurately count the number of all quantum gates in the physical quantum circuit, including all original logic gates introduced during the circuit conversion process and redundant swapped gates added to satisfy connectivity.

[0097] 4) After the statistics are completed, the system compares the number of physical quantum circuit gates obtained under the current parameter value with the minimum number of gates recorded in the temporary variable. If the current parameter value results in a smaller number of gates, or if this is the first parameter value tested, the system updates the temporary variable, records the current parameter value as the current optimal parameter value, and records the corresponding number of gates as the new minimum number of gates.

[0098] 5) Repeat the above steps until all parameter values ​​in the parameter value set have been tested. After the iteration is complete, the parameter value recorded in the temporary variable that minimizes the number of physical quantum circuit gates is officially determined as the optimal parameter value for that logic quantum circuit sample. This optimal parameter value is then combined with the feature vector of the logic quantum circuit sample to form a complete training data point for subsequent decision tree training. The entire process is implemented through programming loops and conditional judgments, ensuring that each parameter value is tested fairly and automatically selecting the parameter configuration with the best performance.

[0099] The following embodiments further illustrate a quantum circuit conversion method of the present invention. The present invention uses a pre-trained decision tree to adjust the algorithm parameters according to the current input logic circuit before each circuit conversion algorithm run, thereby achieving optimal matching of the algorithm parameters to the input circuit. It can be divided into four parts: (1) feature extraction of the input logic circuit; (2) training of the decision tree; (3) parameter adjustment of the circuit conversion algorithm by the decision tree; and (4) the main function of the quantum circuit conversion problem parameter enhancement algorithm based on the decision tree. The present invention can adaptively adjust the parameters of any circuit conversion algorithm containing preset parameters line by line, effectively improving the performance of the algorithm. Specifically:

[0100] (1) Feature extraction of the input logic circuit:

[0101] Input: A quantum circuit to be converted Initial mapping Cutoff threshold ;

[0102] Output: A corresponding input eigenvectors ;

[0103] Before introducing the specific steps of feature extraction, the following features need to be defined:

[0104] ① Number of quantum circuit gates (Size): Input Number of middle gates;

[0105] ② Quantum circuit gate density (Density): ,in, express: and These represent the quantum circuits to be converted. The Middle The and the first One quantum bit. Represents an action on a qubit and Control NOT gate operation. Represents a mapping of qubits. The shortest path length in the quantum computer's connectivity graph for the physical qubits corresponding to the two logical qubits acted upon by the control NOT gate. express Representing logical quantum circuits The total number of quantum gates contained in it.

[0106] ③ The first quantum circuit Layer Density: ,in, This means summing the distances between all two-qubit gates (specifically, control-NOT gates) in the i-th layer of a logic quantum circuit under a given qubit mapping. Represents the total number of all quantum gates in the i-th layer of a logical quantum circuit.

[0107] ④ Number of quantum circuit layers (LayerNum): as defined above Number of middle layers;

[0108] ⑤ The first quantum circuit Maximum Layer Density: ;

[0109] ⑥ The first quantum circuit Minimum distance between floor doors (MinLayerDensity): ;

[0110] ⑦ The first quantum circuit Number of Layers (LayerSize): ;

[0111] ⑧ Average layer size (AveSize) of quantum circuits: ,in, This represents the total number of layers in a logic quantum circuit from 1 to 1. A set of integer indices. Representing logical quantum circuits The Middle The number of quantum gates contained in the layer. Representing logical quantum circuits The total number of layers obtained after dividing according to the left shift rule;

[0112] ⑨ The maximum layer of a quantum circuit: ;

[0113] ⑩ The minimum layer of a quantum circuit: ;

[0114] ⑪ Information entropy (Info) of quantum circuits: ,in for The number of qubits in the memory, For qubits exist The probability of occurrence of CNOT gates.

[0115] The specific steps are as follows:

[0116] ① Initialization It is an empty vector;

[0117] ② , , , , join in ;

[0118] ③ , in turn , , join in ;

[0119] ④ Return .

[0120] Specifically, an empty feature vector is first created as a container. Then, the system calculates a series of global statistical features of the logic quantum circuit, including the total number of gates in the circuit. In the initial mapping Gate density below Average layer size Maximum layer size Minimum layer size and information entropy These feature values ​​are then added sequentially to the feature vector. These global features characterize the scale, connectivity requirements, and structural complexity of the line at a holistic level. After adding global features, the layer-specific feature extraction stage begins. This is done based on a predefined truncation threshold. Traverse each level from level 1 to level t, i.e., process In this case, for each specified layer index i, calculate multiple local features within that layer, including the layer gate density, which reflects the average connectivity requirement within the layer. The most extreme connectivity within a floor, i.e., the longest distance between floor doors. Shortest distance to the floor door and the size of the floor, i.e., the number of doors. These layer-specific features are sequentially appended to the end of the feature vector, providing detailed information about the local structure of the circuit. Finally, the system returns this constructed multidimensional feature vector, which integrates the global attributes and local details of the circuit, providing standardized input data for subsequent decision tree models.

[0121] (2) Training of decision trees:

[0122] Input: Target quantum computer connection diagram Target line conversion algorithm Target line conversion algorithm parameter value set Initial qubit mapping of logic quantum circuits Existing decision tree training algorithms (Train, truncation threshold) Test set size ;

[0123] Output: The completed decision tree, i.e., the pre-trained decision tree;

[0124] The specific implementation steps are as follows:

[0125] ① Randomly generated The number of layers is The logic circuit sequence;

[0126] ② ;

[0127] ③ ;

[0128] ④ Return .

[0129] Specifically, a dataset needs to be generated for training. This step involves creating variables. To complete, Represents a containing A collection of _n_ logical quantum circuits. These logical quantum circuits are randomly generated, and the number of layers in each circuit is limited to _n_. This set C forms the sample base needed to train the decision tree. Creating the training dataset. The training dataset By processing sets Each logical quantum circuit sample in To build. For each First, call the feature extraction function. To calculate the line Secondly, through process optimization To determine the optimal parameter p corresponding to this line, this optimal parameter... This refers to the parameter value, within a given set of parameters, that minimizes the number of gates (Size) in the physical quantum circuit output by the QCT circuit conversion algorithm. Ultimately, the training dataset... From all these feature vectors The pairing is formed with the corresponding optimal parameters. This indicates that the decision tree obtained after training is the pre-trained decision tree. Indicates the use of the training dataset The training process for constructing a pre-trained decision tree.

[0130] (3) Decision tree parameter adjustment for line switching algorithm (ParaAdjust):

[0131] Input: Target quantum computer connection diagram Target line conversion algorithm Initial qubit mapping of logical quantum circuits Decision tree Logic circuit truncation threshold ;

[0132] Output: For logic circuits Line conversion algorithm Recommended parameters ;

[0133] The specific implementation steps are as follows:

[0134] ① ;

[0135] ② ;

[0136] ③ Return .

[0137] Specifically, calling the feature extraction function This function processes the input logic quantum circuit to be converted. It is based on the initial qubit mapping. and cutoff threshold Feature vectors that comprehensively describe the structural characteristics of logical quantum circuits (LC) are extracted. These feature vectors contain both global statistical features and layer-specific features, providing a data foundation for subsequent parameter recommendation. The obtained feature vectors are then input into a pre-trained decision tree. In the middle, execute the prediction function Pre-trained decision trees Starting from the root node, the decision tree traverses downwards layer by layer according to the specific values ​​of each feature in the feature vector, following the branch conditions of the tree structure. Each internal node corresponds to a feature judgment, and the appropriate branch path is selected based on the feature value, until a leaf node is reached. The parameter value stored in this leaf node is the recommended parameter output by the decision tree for the current input path. This recommended parameter, predicted by the decision tree, is then... The result is returned. The entire process implements adaptive parameter selection based on line characteristics, assigning appropriate line conversion algorithm parameters to different logical quantum lines without manual intervention, thereby optimizing the conversion effect. Among these, This means that the logic circuit, initial mapping, and truncation threshold are processed by the feature extraction function to generate the corresponding feature vector. This means inputting feature vectors into a pre-trained decision tree model and assigning the model's predicted values ​​to the parameters. . This indicates that the prediction process of the decision tree model is performed by taking the feature vector as input. This indicates that the pre-trained decision tree model selects the recommended parameters for the line switching algorithm based on the input feature vector.

[0138] (4) Main function of the parameter enhancement algorithm for quantum circuit switching problem based on decision tree:

[0139] Input: Target quantum computer connection diagram Target line conversion algorithm Target line conversion algorithm parameter value set Initial qubit mapping of logic quantum circuits Pre-trained decision tree (Train) and truncation threshold Test set size Logic circuit ;

[0140] Output: The physical circuit after conversion ;

[0141] The specific implementation steps are as follows:

[0142] ① ;

[0143] ② ;

[0144] ③ ;

[0145] ④ Return .

[0146] Specifically, call the decision tree training function. This function receives the connection diagram of the target quantum computer. Target line conversion algorithm Parameter value set Initial qubit mapping Pre-trained decision tree (Train) and truncation threshold and test set size As input, a training dataset is generated, and a decision tree model capable of recommending optimal parameters based on line features is trained on this dataset. The output of this function, the trained decision tree model, is assigned to the variable. Calling the function This function utilizes the decision tree model obtained in the previous step. Combined with the specific logical quantum circuit to be converted Connection diagram Initial mapping and cutoff threshold It performs feature extraction and decision tree prediction. Its ultimate goal is to predict the current path. Calculate the line conversion algorithm A recommended parameter The recommended parameters determined in the previous step. Along with logical quantum circuits Initial qubit mapping And quantum computer connection diagram Together they are passed to the line conversion algorithm The algorithm performs the actual conversion operation accordingly, and its output is the converted physical quantum circuit that meets hardware constraints. This result is assigned to variables. The generated physical quantum circuit PC is returned as the result of the entire main function. At this point, a complete quantum circuit conversion process integrating adaptive parameter adjustment has been executed. This means that the decision tree training function is called to generate and return a pre-trained decision tree based on the given quantum computer connection diagram, circuit conversion algorithm, parameter set, and other inputs. Instructions: Call the parameter tuning function, utilize the pre-trained decision tree model and the features of the current logic quantum circuit, calculate and return the recommended parameters for that circuit. . Indicates: Call the line conversion algorithm, using recommended parameters. The logical quantum circuit is transformed to generate and return a physical quantum circuit that conforms to hardware constraints. .

[0147] The technical terms used in this invention are explained as follows:

[0148] 1) Quantum bit: A quantum bit is the basic unit for storing data in a quantum computer. Quantum programs perform specific functions by performing corresponding operations on quantum bits.

[0149] 2) Quantum Gates: Quantum gates can change the state of their operating qubits, thereby realizing specific quantum operations. Based on the number of operating qubits, quantum gates can be divided into single-qubit gates and two-qubit gates. A single-qubit gate operates on only one specific qubit and can only change the state of that qubit; a two-qubit gate operates on two qubits and can change the states of both qubits. Two common two-qubit gates are the controlled NOT gate and the swapping gate. In this invention, using... Indicates the effect on A typical single-qubit gate on a qubit is used Indicates the effect on and A general two-qubit gate on a qubit. In addition, this invention also requires the use of two special two-qubit gates: a swapping gate and a controlled NOT gate. One acts on... and The swapping gate and the controlled NOT gate on a qubit can be used respectively. and express.

[0150] 3) Quantum circuits: Quantum circuits are a common method for describing quantum programs, typically consisting of qubits and a series of quantum gates. Figure 2 The quantum circuit shown contains two qubits. , Each line represents a corresponding qubit, and module A represents... Module B represents Module C represents Users do not consider the execution limitations of quantum computers when designing quantum circuits. Therefore, before executing the quantum program described by the quantum circuit in a quantum computer, the user-designed quantum circuit needs to undergo a series of transformations. The transformed circuit must satisfy the execution limitations of the corresponding quantum computer while being functionally equivalent to the input circuit. This invention refers to the user-designed quantum circuit as a logic quantum circuit (denoted as...). The resulting quantum circuit after conversion is called a physical quantum circuit (denoted as ). ).

[0151] 4) Layers of quantum circuits:

[0152] For a quantum circuit, if we shift all the gates as far to the left as possible, we can group the gates in the same column into a single layer. Figure 3 The quantum circuit shown contains three layers, with quantum gates in layers 0, 1, and 2 respectively. , , .

[0153] 5) Logical qubits and physical qubits: In this invention, the qubits in a logical quantum circuit are referred to as logical qubits. Indicates the number is Logical qubits; qubits in physical quantum circuits are called physical qubits, and are used as... Indicates the number is The physical qubits in a physical quantum circuit correspond one-to-one with the actual qubits in a quantum computer.

[0154] 6) Quantum Computer Connectivity Graph: In some quantum computers, the connectivity between physical bits is restricted, specifically meaning that gate transformations between two qubits can only be performed between specific pairs of physical bits. This restriction can be represented by a quantum computer connectivity graph. A quantum computer connectivity graph can be described as an undirected graph, denoted as […]. ,in This represents the set of nodes in the graph. Describe the set of edges. This represents an edge in a connected graph. In this context, nodes represent physical qubits, and edges represent the connectivity of qubits. A gate transformation between two qubits can only be performed between physical qubits directly connected by an edge. Figure 4 In the example, Therefore, it can only be done in physical bits. , Perform a gate transformation between two qubits , , and The corresponding gate transformation cannot be performed between them.

[0155] 7) Quantum Bit Mapping: When running quantum programs in a quantum computer, it is necessary to map the qubits in the logical quantum circuits to physical qubits; this process is called qubit mapping. Furthermore, a given qubit mapping can be changed by introducing swap gates into the physical circuits. For example, in... Figure 5 In this context, the initial state of the qubit mapping is: Mapped to , Mapped to , Mapped to By introducing physical quantum circuits It can map and transform qubits into Mapped to , Mapped to , Mapped to Symbols can be used. Represents a mapping of a qubit. express The physical qubit corresponding to the logical qubit under this mapping. ( )or Representing a quantum bit mapping Introducing an edge into a connected graph The corresponding switch or The resulting new qubit mapping. For example, in Figure 5 middle, , , .

[0156] 8) Distance of a two-qubit operation: For any two-qubit operation in a logic quantum circuit... A diagram of a quantum computer architecture A quantum bit mapping The operation of these two qubits distance Defined in this invention Middle node and The shortest distance between them. For example, for... Figure 4 The structural diagram shown and Figure 5 The quantum bit mapping shown on the left quantum operations distance ,because = , = ,and and exist The shortest path in is Its length is 2.

[0157] 9) Executability of quantum gates in logical quantum circuits: If a given quantum bit is mapped... Below, a two-qubit quantum gate in a logical quantum circuit (assuming it operates on the qubit). The above satisfies (1) it is located at the 0th layer in the logic quantum circuit; (2) If so, the quantum gate is called executable.

[0158] 10) Quantum Gate Transformation: Quantum gate transformation refers to the process of continuously altering the qubit mapping by introducing a series of redundant swapping gate operations into the physical quantum circuit, so that the correspondence of a two-qubit gate in the logical quantum circuit satisfies the quantum computer connectivity constraint, i.e., obtaining... Additionally, for a gate in a logical quantum circuit (e.g.) A mapping of a quantum bit Its corresponding term in physical quantum circuits is called .

[0159] For example, for Figure 4 The quantum computer connectivity graph shown assumes that the initial qubits are mapped as follows: The two-qubit gate in the logic quantum circuit that needs to be converted is To satisfy the connectivity restrictions, only a limited number of swapping gates can be introduced into physical quantum circuits. and .because , ,at this time The corresponding physical circuit is And because ,therefore It does not satisfy the connectivity graph constraint of a quantum computer. If a connection is introduced into the physical circuitry... Then the quantum bit mapping becomes , ,at this time The corresponding physical circuit is And because ,at this time This satisfies the connectivity constraints of a quantum computer. In summary, the initial qubit mapping is... At that time, the above The conversion process requires introducing [something] into the physical circuit. and It is important to note that the transition process of a quantum gate is usually not unique; for example, in the above example, by introducing... and It can be achieved in the same way. The conversion.

[0160] 11) Quantum circuit conversion: Quantum circuit conversion refers to the process of constructing a physical quantum circuit based on a given computer connectivity graph, logical quantum circuit, and an initial qubit mapping. The output physical quantum circuit is required to be functionally equivalent to the input logical quantum circuit, and the two qubit gates in it must satisfy the constraints of the computer connectivity graph.

[0161] The specific method for quantum circuit switching is to perform the switching in the physical quantum circuit for each two-qubit gate in the logical quantum circuit (usually in left-to-right order) by introducing redundant swap gates. For Figure 6 The logic quantum circuit shown and Figure 4 The diagram shows the connected graph of the quantum computer, and assumes that the initial qubits are mapped as follows: Perform quantum circuit conversion on it. First, convert the control NOT gate on the left. The conversion process of this gate requires the introduction of physical quantum circuits. Update the qubit mapping to , Then introduce Secondly, the control NOT gate on the right. Perform the conversion, because at this time Correspondence in physical circuits The connectivity constraints for quantum computers have already been met, so it is only necessary to introduce [something] into the physical quantum circuitry. The final physical quantum circuit output from the entire quantum circuit conversion process is as follows: Figure 7 As shown.

[0162] The entire process of invoking the quantum circuit conversion is denoted as follows in this invention: ,in For input logic quantum circuits, For the initial qubit mapping, This is the connected graph corresponding to the target quantum computer. The physical quantum circuit for output. The values ​​are assigned to the algorithm's parameters.

[0163] It should be noted that the core of this invention is to design a method to adaptively adjust the parameters of existing line conversion algorithms in order to improve their performance. Therefore, there are no restrictions on the specific implementation method of the mapping, and theoretically any optimization algorithm can be used, such as SABRE.

[0164] 12) Decision Tree: A decision tree is a tree-like data structure that can classify input data according to preset features. Each non-leaf node in the tree represents a specific feature, and each branch represents a value of that feature; the leaf nodes in the tree represent a definite classification result. The input of a decision tree is data to be predicted, and the output is a classification prediction based on that data. Figure 8 This is a decision tree used to determine whether a job applicant passes an interview. The decision tree contains three features: major studied, university attended, and average score. The final output is a binary classification. The elements in the set.

[0165] This invention represents the calling process of a decision tree as follows: ,in This represents a tree structure that conforms to the definition above. This represents a feature input vector.

[0166] 13) Decision Tree Training: Decision tree training is a recursive, heuristic process of feature selection and tree construction. The input to this process is a training set, denoted as... },in For the feature vector of the sample, Label it as a category. This represents the size of the training set. The goal of this process is to build a decision tree model with strong generalization ability, ensuring that the model outputs the correct class prediction for the input samples. This process starts from the root node and iterates through the sample set contained in the current node. The analysis proceeds. An optimal splitting feature is selected using a specific criterion (e.g., information gain). Based on the value of this optimal feature, the current sample set is divided into several non-empty subsets, and these subsets are assigned to new child nodes. For each child node, using its corresponding sample subset as training data, the feature selection and node splitting process is recursively repeated until a stopping condition is met (e.g., all samples in the current node belong to the same category, or there are no more features available for splitting). This training process can be denoted as follows in this method: .

[0167] It should be noted that this invention does not restrict the specific method for training the decision tree; theoretically, any optimization algorithm can be used, such as ID3.

[0168] Although the steps have been numbered in the above embodiments, they are only specific embodiments given by the present invention. Those skilled in the art can adjust the execution order of the steps according to the actual situation, which is also within the protection scope of the present invention. It can be understood that some embodiments may include some or all of the above embodiments.

[0169] like Figure 9 As shown, a quantum circuit conversion system 200 according to an embodiment of the present invention includes a feature vector acquisition module 201, a recommended parameter acquisition module 202, and a conversion module 203;

[0170] The feature vector acquisition module 201 is used to: extract the feature vector of the logic quantum circuit to be converted based on the initial quantum bit mapping;

[0171] The recommended parameter acquisition module 202 is used to: input the feature vector of the logic quantum circuit to be converted into a pre-trained decision tree to obtain the recommended parameters of the circuit conversion algorithm. The pre-trained decision tree is constructed based on the training set, which contains the feature vectors of multiple logic quantum circuit samples and the optimal parameter values ​​of the circuit conversion algorithm corresponding to each sample. The optimal parameter value is the parameter that minimizes the number of gates in the physical quantum circuit obtained after conversion.

[0172] The conversion module 203 is used to: configure the parameters of the circuit conversion algorithm to the recommended parameters, and use the configured circuit conversion algorithm to convert the logical quantum circuit to be converted to generate a physical quantum circuit. In the physical quantum circuit, the physical quantum bit pairs operated by all two-qubit gate operations are elements of the edges in the quantum computer's connected graph, and the physical quantum circuit is functionally equivalent to the logical quantum circuit to be converted.

[0173] Optionally, the above technical solution further includes an optimal parameter value determination module, which is used for:

[0174] For each logical quantum circuit sample, all parameter values ​​are traversed in the parameter value set of the circuit conversion algorithm. Each parameter value is used to convert the logical quantum circuit sample to obtain the corresponding physical quantum circuit. The parameter value that minimizes the number of gates in the physical quantum circuit is selected as the optimal parameter value for the logical quantum circuit sample.

[0175] Optionally, in the above technical solution, the conversion module 203 is specifically used for:

[0176] Each quantum gate in the logical quantum circuit to be converted is processed sequentially. For a single-qubit gate in the logical quantum circuit to be converted, the single-qubit gate is directly added to the physical quantum circuit. For a two-qubit gate in the logical quantum circuit to be converted, the current qubit mapping of the two qubit gates is updated by introducing one or more swapping gate operations, and the swapping gate operations are added to the physical quantum circuit until the two qubit gates satisfy the restrictions of the quantum computer's connected graph under the updated qubit mapping. Then, the physical operations corresponding to the two qubit gates are added to the physical quantum circuit.

[0177] The initial qubit mapping is defined as both the initial state of the current qubit mapping used when processing the first single-qubit gate and the initial state of the current qubit mapping used when processing the first two-qubit gate.

[0178] Optionally, in the above technical solution, the feature vector of the logic quantum circuit to be converted includes at least one of the following: the number of gates, gate density, number of layers, average layer size, maximum layer size, minimum layer size, and information entropy of the logic quantum circuit to be converted.

[0179] The feature vector of the quantum logic circuit to be converted also includes: the in-layer gate density of the specified layer of the quantum logic circuit to be converted, the maximum in-layer gate distance of the specified layer, the minimum in-layer gate distance of the specified layer, and the number of in-layer gates of the specified layer, wherein the number of specified layers is determined by a predefined truncation threshold.

[0180] It should be noted that the beneficial effects of the quantum circuit conversion system 200 provided in the above embodiments are the same as those of the quantum circuit conversion method described above, and will not be repeated here. Furthermore, the system provided in the above embodiments is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the system can be divided into different functional modules according to the actual situation to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, and will not be repeated here.

[0181] An electronic device according to an embodiment of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements any of the above-mentioned quantum circuit conversion methods. That is, an electronic device according to an embodiment of the present invention may include, but is not limited to: a processor and a memory; the memory is used to store the computer program; the processor is used to execute the quantum circuit conversion method shown in any embodiment of the present invention by calling the computer program.

[0182] In one alternative embodiment, an electronic device is provided, such as Figure 10 As shown, Figure 10 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0183] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0184] Bus 4002 may include a path for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 10 The bus 4002 is represented by only one thick line, but this does not mean that there is only one bus or one type of bus.

[0185] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto.

[0186] The memory 4003 stores application code (computer program) for executing the present invention, and its execution is controlled by the processor 4001. The processor 4001 executes the application code stored in the memory 4003 to implement the content shown in the foregoing method embodiments.

[0187] Among them, electronic devices can also be terminal devices, which can be any device that can install applications, including at least one of smartphones, tablets, laptops, desktop computers, smart speakers, smartwatches, smart TVs, and smart in-vehicle devices.

[0188] It should be noted that, Figure 10 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0189] An embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the above-described quantum circuit conversion methods.

[0190] Alternatively, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0191] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform any of the aforementioned quantum circuit conversion methods.

[0192] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0193] It should be understood that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0194] The computer-readable storage medium provided in this invention can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EEPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0195] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the method shown in the above embodiments.

[0196] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0197] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and represent a limitation on a specific order or sequence. Where appropriate, the order of use for similar objects can be interchanged so that the embodiments of this application described herein can be implemented in an order other than that shown or described.

[0198] Those skilled in the art will recognize that this invention can be implemented as a system, method, or computer program product. Therefore, this invention can be specifically implemented in the following forms: it can be entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." Furthermore, in some embodiments, this invention can also be implemented as a computer program product contained in one or more computer-readable media, which includes computer-readable program code.

[0199] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A quantum circuit switching method, characterized in that, include: Based on the initial qubit mapping, the feature vector of the logic quantum circuit to be converted is extracted; The feature vector of the logic quantum circuit to be converted is input into a pre-trained decision tree to obtain the recommended parameters of the circuit conversion algorithm. The pre-trained decision tree is constructed based on a training set, which contains feature vectors of multiple logic quantum circuit samples and the optimal parameter values ​​of the circuit conversion algorithm corresponding to each sample. The optimal parameter values ​​are those that minimize the number of gates in the physical quantum circuit obtained after conversion. The parameters of the circuit conversion algorithm are configured as the recommended parameters, and the configured circuit conversion algorithm is used to convert the logical quantum circuit to be converted to generate a physical quantum circuit. In the physical quantum circuit, the physical quantum bit pairs operated by all two-qubit gate operations are elements of the edges in the quantum computer's connected graph, and the physical quantum circuit is functionally equivalent to the logical quantum circuit to be converted. The configured circuit conversion algorithm is used to convert the logical quantum circuit to be converted, generating a physical quantum circuit, including: Each quantum gate in the quantum circuit to be converted is processed sequentially. For a single-qubit gate in the quantum circuit to be converted, the single-qubit gate is directly added to the physical quantum circuit. For a two-qubit gate in the quantum circuit to be converted, the current qubit mapping of the two qubit gates is updated by introducing one or more swap gate operations, and the swap gate operations are added to the physical quantum circuit until the two qubit gates satisfy the restrictions of the quantum computer connectivity graph under the updated qubit mapping. Then, the physical operations corresponding to the two qubit gates are added to the physical quantum circuit. The initial qubit mapping refers to both the initial state of the current qubit mapping used when processing the first single-qubit gate and the initial state of the current qubit mapping used when processing the first two-qubit gate.

2. The quantum circuit conversion method according to claim 1, characterized in that, The process of determining the optimal parameter values ​​in the training set includes: For each logical quantum circuit sample, all parameter values ​​are traversed in the parameter value set of the circuit conversion algorithm, and each parameter value is used to convert the logical quantum circuit sample to obtain the corresponding physical quantum circuit. The parameter value that minimizes the number of gates in the physical quantum circuit is selected as the optimal parameter value of the logical quantum circuit sample.

3. A quantum circuit conversion method according to claim 1 or 2, characterized in that, The feature vector of the quantum logic circuit to be converted includes at least one of the following: number of gates, gate density, number of layers, average layer size, maximum layer size, minimum layer size, and information entropy. The feature vector of the quantum logic circuit to be converted further includes: the in-layer gate density corresponding to the specified layer of the quantum logic circuit to be converted, the maximum in-layer gate distance corresponding to the specified layer, the minimum in-layer gate distance corresponding to the specified layer, and the number of in-layer gates corresponding to the specified layer, wherein the number of the specified layer is determined by a predefined truncation threshold.

4. A quantum circuit conversion system, characterized in that, It includes a feature vector acquisition module, a recommendation parameter acquisition module, and a transformation module; The feature vector acquisition module is used to: extract the feature vector of the logic quantum circuit to be converted based on the initial quantum bit mapping; The recommended parameter acquisition module is used to: input the feature vector of the logic quantum circuit to be converted into a pre-trained decision tree to obtain the recommended parameters of the circuit conversion algorithm. The pre-trained decision tree is constructed based on a training set, which contains feature vectors of multiple logic quantum circuit samples and the optimal parameter values ​​of the circuit conversion algorithm corresponding to each sample. The optimal parameter values ​​are the parameters that minimize the number of gates in the physical quantum circuit obtained after conversion. The conversion module is used to: configure the parameters of the circuit conversion algorithm to the recommended parameters, and use the configured circuit conversion algorithm to convert the logical quantum circuit to be converted to generate a physical quantum circuit, wherein the physical quantum bit pairs operated by all two-qubit gate operations in the physical quantum circuit are elements of the edges in the quantum computer's connected graph, and the physical quantum circuit is functionally equivalent to the logical quantum circuit to be converted. The conversion module is specifically used for: Each quantum gate in the quantum circuit to be converted is processed sequentially. For a single-qubit gate in the quantum circuit to be converted, the single-qubit gate is directly added to the physical quantum circuit. For a two-qubit gate in the quantum circuit to be converted, the current qubit mapping of the two qubit gates is updated by introducing one or more swap gate operations, and the swap gate operations are added to the physical quantum circuit until the two qubit gates satisfy the restrictions of the quantum computer connectivity graph under the updated qubit mapping. Then, the physical operations corresponding to the two qubit gates are added to the physical quantum circuit. The initial qubit mapping refers to both the initial state of the current qubit mapping used when processing the first single-qubit gate and the initial state of the current qubit mapping used when processing the first two-qubit gate.

5. A quantum circuit conversion system according to claim 4, characterized in that, It also includes an optimal parameter value determination module, which is used for: For each logical quantum circuit sample, all parameter values ​​are traversed in the parameter value set of the circuit conversion algorithm, and each parameter value is used to convert the logical quantum circuit sample to obtain the corresponding physical quantum circuit. The parameter value that minimizes the number of gates in the physical quantum circuit is selected as the optimal parameter value of the logical quantum circuit sample.

6. A quantum circuit conversion system according to claim 5, characterized in that, The feature vector of the quantum logic circuit to be converted includes at least one of the following: number of gates, gate density, number of layers, average layer size, maximum layer size, minimum layer size, and information entropy. The feature vector of the quantum logic circuit to be converted further includes: the in-layer gate density corresponding to the specified layer of the quantum logic circuit to be converted, the maximum in-layer gate distance corresponding to the specified layer, the minimum in-layer gate distance corresponding to the specified layer, and the number of in-layer gates corresponding to the specified layer, wherein the number of the specified layer is determined by a predefined truncation threshold.

7. An electronic device, characterized in that, The invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements a quantum circuit conversion method according to any one of claims 1 to 3.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements a quantum circuit conversion method according to any one of claims 1 to 3.

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