Integral module phase interpolator circuit with strong robustness and wide frequency adaptability

Abstract

The application discloses an integral module phase interpolator circuit with strong robustness and wide frequency adaptability, comprising a phase interpolator array, a switch bias voltage self-adaptive adjustment circuit, a current type analog-digital converter, a binary code to thermometer code decoder and a phase interpolator output driving circuit; the phase interpolator output driving circuit is connected with the current type analog-digital converter, the phase interpolator array and the switch bias voltage self-adaptive adjustment circuit, and the binary code to thermometer code decoder is connected with the phase interpolator array, and the circuit can realize high-precision adjustment on an output phase.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and relates to an integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability. Background Technology

[0002] In applications such as high-performance digital communication, radar systems, precision measurement, and high-precision clock synchronization, phase-locked loops (PLLs) serve as core time-frequency control modules, widely used for critical functions such as frequency synthesis, phase tracking, and clock recovery. To support higher-resolution frequency adjustments and meet the requirements of multi-rate protocols, spectrum compression, and high-order modulation in communication systems for frequency accuracy and phase stability, fractional-N PLLs are increasingly being used. This type of structure achieves higher frequency resolution by refining the division ratio; however, the ΣΔ modulation structure used internally often introduces fractional modulation noise, which is superimposed on the output signal, leading to increased phase jitter, especially noticeable in high-speed, wideband systems.

[0003] To effectively suppress the aforementioned error sources and improve phase-locked loop (PLL) accuracy, modern high-performance PLL systems have gradually introduced phase interpolator (PI) modules to achieve sub-cycle-level phase adjustment capabilities. The phase interpolator generates a finely controllable intermediate phase by weighted superposition of multiple reference phase signals, thereby achieving interpolation positioning of the output clock edge between two reference clocks. This mechanism not only significantly improves time resolution but also effectively reduces the loss of PLL accuracy due to quantization errors, making it a key supporting module for building high-performance, low-jitter, and wide-frequency adaptive PLL architectures.

[0004] As the core circuit for achieving continuously adjustable phase, the performance of the high-precision phase interpolator directly determines the phase linearity, output jitter, and frequency regulation capability of the entire phase-locked loop system. Traditional PI structures often face problems such as current jump interference during control code switching, nonlinear errors caused by non-ideal matching, and gain fluctuations over a wide frequency range, making it difficult to simultaneously meet the requirements of high-speed and high-precision control. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide an integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability, which can achieve high-precision adjustment of the output phase.

[0006] To achieve the above objectives, this invention discloses an integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability, comprising two-phase clock input signals PI_INφ1 and PI_INφ2 for the phase interpolator, a current-mode digital-to-analog converter control word I_SINK<15:0>, a phase interpolator control word PI_CTRL<7:0>, a phase interpolator cell control word PI_CELL_CTRL<255:0>, a current-mode analog-to-digital converter enable signal ENN_IDAC, a phase interpolator output reset signal ENN_SWITCH_OUT, a sampling switch pulse signal SAMPLE_PULSE, a phase interpolator output clock signal PI_OUT, a phase interpolator array, a switch bias voltage adaptive adjustment circuit, a current-mode analog-to-digital converter, a binary code to thermometer code decoder, and a phase interpolator output drive circuit; The phase interpolator output drive circuit is connected to the current-mode analog-to-digital converter, the phase interpolator array, and the switch bias voltage adaptive adjustment circuit. The binary code to thermometer code decoder is connected to the phase interpolator array. The two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator are connected to the phase interpolator array. The current-mode digital-to-analog converter control word I_SINK<15:0> is connected to the current-mode analog-to-digital converter. The phase interpolator control word PI_CTRL<7:0> is connected to the binary code to thermometer code decoder. The bit interpolator unit control word PI_CELL_CTRL<255:0> is connected to the phase interpolator array, the current-mode analog-to-digital converter enable signal ENN_IDAC is connected to the current-mode analog-to-digital converter, the phase interpolator output reset signal ENN_SWITCH_OUT is connected to the phase interpolator output drive circuit, the sampling switch pulse signal SAMPLE_PULSE is connected to the switch bias voltage adaptive adjustment circuit, and the phase interpolator output clock signal PI_OUT is connected to the phase interpolator output drive circuit.

[0007] The further improvement of the integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability described in this invention lies in: Furthermore, the phase interpolator array is composed of 256 identical phase interpolator units PI_CELL

[255] -PI_CELL[0] connected in parallel.

[0008] Furthermore, each phase interpolator unit includes NMOS transistors M0, M1, and M2, as well as a 2-to-1 multiplexer MUX; The source of NMOS transistor M0 is connected to the drain of NMOS transistor M1, the gate of NMOS transistor M0 is connected to the bias voltage NVB1, and the drain of NMOS transistor M0 is connected to the drain of NMOS transistor M3 in the phase interpolator output drive circuit I5. The source of NMOS transistor M1 is connected to the drain of NMOS transistor M2, and the gate of NMOS transistor M1 is connected to the bias voltage NVB0. The source of the NMOS transistor M2 is grounded, and the gate of the NMOS transistor M2 is connected to the output of the 2-to-1 multiplexer MUX. The input of the 2-to-1 multiplexer MUX is connected to the two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator.

[0009] Furthermore, the adaptive adjustment circuit for the switch bias voltage includes a sampling switch NMOS transistor M4, a sampling capacitor C1, and a threshold voltage boosting operational amplifier circuit. The threshold voltage boosting operational amplifier circuit includes NMOS transistors M5, M6, M7, M8, M9, M12, PMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, a capacitor C2, and a resistor R1. The source of NMOS transistor M4 is connected to the gate of NMOS transistor M8, the gate of NMOS transistor M4 is connected to the sampling switch pulse signal SAMPLE_PULSE, and the drain of NMOS transistor M4 is connected to the drain of NMOS transistor M3 in the phase interpolator output drive circuit. The upper plate of the sampling capacitor C1 is connected to the source of the NMOS transistor M4, and the lower plate of the sampling capacitor C1 is grounded. The source of NMOS transistor M5 is grounded, the gate of NMOS transistor M5 is connected to the drain of NMOS transistor M5, and the drain of NMOS transistor M5 is connected to the gate of NMOS transistor M6. The source of NMOS transistor M6 is grounded, the gate of NMOS transistor M6 is connected to the drain of NMOS transistor M6, and the drain of NMOS transistor M6 is connected to the source of NMOS transistor M8. The source of NMOS transistor M7 is grounded, the gate of NMOS transistor M7 is connected to the gate of NMOS transistor M6, and the drain of NMOS transistor M7 is connected to the gate of NMOS transistor M9. The source of NMOS transistor M8 is connected to the source of NMOS transistor M9, and the drain of NMOS transistor M8 is connected to the drain of PMOS transistor M10. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M6, and the drain of NMOS transistor M9 is connected to the drain of PMOS transistor M11. The source of the PMOS transistor M10 is connected to VDD, the gate of the PMOS transistor M10 is connected to the source of the PMOS transistor M10, and the drain of the PMOS transistor M10 is connected to the gate of the PMOS transistor M11. The source of the PMOS transistor M11 is connected to VDD; The two ends of the resistor R1 are connected to the drain of the PMOS transistor M11 and the lower plate of the capacitor C2, respectively. The upper plate of capacitor C2 is connected to VDD, and the lower plate of capacitor C2 is connected to the gate of NMOS transistor M12. The source of NMOS transistor M12 is connected to the drain of NMOS transistor M7, the gate of NMOS transistor M12 is connected to the gate of NMOS transistor M3, and the drain of NMOS transistor M12 is connected to VDD.

[0010] Furthermore, the input terminal of the current-mode analog-to-digital converter is connected to the current-mode digital-to-analog converter control word I_SINK<15:0> and the current-mode analog-to-digital converter enable signal ENN_IDAC, and the output terminal of the current-mode analog-to-digital converter is connected to the drain of NMOS transistor M3 in the phase interpolator output drive circuit.

[0011] Furthermore, the input terminal of the binary code to thermometer code decoder is connected to the phase interpolator control word PI_CTRL<7:0>, and the output terminal of the binary code to thermometer code decoder is connected to the control terminal PI_CELL

[255] -PI_CELL[0] of the two-to-one multiplexer MUX in each phase interpolator unit as the phase interpolator unit control word PI_CELL_CTRL<255:0>.

[0012] Furthermore, the phase interpolator output drive circuit I5 includes an NMOS transistor M3, a reset PMOS transistor M13, a reset logic inverter INV0, and a threshold adjustment inverter INV1-2. The source of NMOS transistor M3 is connected to the input terminal of inverter INV1, the gate of NMOS transistor M3 is connected to the gate of NMOS transistor M12, and the drain of NMOS transistor M3 is connected to the output terminal of current-mode analog-to-digital converter I3. The source of the PMOS transistor M13 is connected to VDD, the gate of the PMOS transistor M13 is connected to the output terminal of the inverter INV0, and the drain of the PMOS transistor M13 is connected to the input terminal of the inverter INV1. The input terminal of the inverter INV0 is connected to the phase interpolator output reset signal ENN_SWITCH_OUT; The output of inverter INV1 is connected to the input of inverter INV2, and the output of inverter INV2 is connected to the phase interpolator to output the clock signal PI_OUT.

[0013] Furthermore, the bias voltage of the switching transistor in the phase interpolator output drive circuit is generated by negative feedback through sampling the output node voltage of the phase interpolator array, so as to achieve high linearity of interpolation.

[0014] Furthermore, the phase interpolator output drive circuit uses several inverters with non-standard thresholds to perform step-by-step threshold fine-tuning to obtain a CMOS clock signal output with a standard threshold.

[0015] Furthermore, the phase interpolator array in Region-III inserts the phase. for:

[0016] in, This represents the total operating current. The total capacitance to ground at the output node of the current-mode analog-to-digital converter I3. The phase difference between the two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator. The clock periods of the two-phase clock input signals PI_INφ1 and PI_INφ2 for the phase interpolator. The flip threshold of the phase interpolator output drive circuit. For control words.

[0017] The present invention has the following beneficial effects: The integral-mode phase interpolator circuit described in this invention, characterized by strong robustness and wide frequency adaptability, eliminates the need for two logic level conversions (CMOS-CML-CMOS) for the input and output clocks, as is required with current-mode phase interpolators. This overcomes the phase error caused by linear encoding in current-mode phase interpolators and the limitations of voltage-mode phase interpolators, which rely heavily on fine-tuning the input clock slew rate during high-precision phase interpolation of CMOS logic clock signals. This slew rate naturally introduces encoding-related nonlinearities, degrading interpolation accuracy and linearity. Furthermore, the integral-mode phase interpolator circuit utilizes a current-mode analog-to-digital converter to control the operating current of the phase interpolator array, thereby controlling the current integration rate. A switch bias voltage generation circuit controls the threshold level of the NMOS switch, significantly expanding the circuit's frequency applicability. Since the entire adaptive calibration process is a background negative feedback analog loop, the entire circuit exhibits high robustness. Threshold adjustment of the inverter path restores the clock signal of the normal CMOS logic after phase interpolation, driving subsequent general-purpose CMOS logic circuits. A binary code-to-thermometer code decoder is used to mitigate phase nonlinearity caused by encoding correlation and layout mismatch. This invention can operate stably under input clock conditions over a wide frequency range, ensuring the operational stability of the integrating-mode phase interpolator while effectively maintaining its high accuracy and linearity in phase adjustment. Through joint optimization of the core current source, current integration path, and control decoding logic, the interpolator can adapt to various operating modes from low speed to high speed, meeting the stringent requirements of wideband phase-locked loop systems for sub-cycle phase adjustment. Attached Figure Description

[0018] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a structural diagram of the present invention; Figure 2 A schematic diagram of the time-domain waveforms of an integral-mode phase interpolator. Figure 3 This is a schematic diagram of the time-domain waveform of the main control signal.

[0019] Among them, I1 is a phase interpolator array, I2 is a switch bias voltage adaptive adjustment circuit, I3 is a current-mode analog-to-digital converter, I4 is a binary code to thermometer code decoder, and I5 is a phase interpolator output drive circuit. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0022] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0024] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0025] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0027] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0028] refer to Figure 1The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability described in this invention includes a phase interpolator array I1, a switch bias voltage adaptive adjustment circuit I2, a current-mode analog-to-digital converter I3, a binary code to thermometer code decoder I4, and a phase interpolator output drive circuit I5. The phase interpolator output drive circuit I5 is connected to the current-mode analog-to-digital converter I3, the phase interpolator array I1, and the switch bias voltage adaptive adjustment circuit I2. The binary code to thermometer code decoder I4 is connected to the phase interpolator array I1. The two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator are connected to the phase interpolator array I1. The current-mode analog-to-digital converter control word I_SINK<15:0> is also included. The current-mode analog-to-digital converter I3 is connected to the phase interpolator control word PI_CTRL<7:0>, which is connected to the binary code to thermometer code decoder I4. The phase interpolator unit control word PI_CELL_CTRL<255:0> is connected to the phase interpolator array I1. The current-mode analog-to-digital converter enable signal ENN_IDAC is connected to the current-mode analog-to-digital converter I3. The phase interpolator output reset signal ENN_SWITCH_OUT is connected to the phase interpolator output drive circuit I5. The sampling switch pulse signal SAMPLE_PULSE is connected to the switch bias voltage adaptive adjustment circuit I2. The phase interpolator output clock signal PI_OUT is connected to the phase interpolator output drive circuit I5.

[0029] The phase interpolator array I1 is composed of 256 identical phase interpolator units PI_CELL

[255] -PI_CELL[0] connected in parallel. Each phase interpolator unit includes an NMOS transistor M0, an NMOS transistor M1, an NMOS transistor M2 and a 2-to-1 multiplexer MUX. The source of the NMOS transistor M0 is connected to the drain of the NMOS transistor M1, the gate of the NMOS transistor M0 is connected to the bias voltage NVB1, and the drain of the NMOS transistor M0 is connected to the drain of the NMOS transistor M3 in the phase interpolator output drive circuit I5. The source of NMOS transistor M1 is connected to the drain of NMOS transistor M2, the gate of NMOS transistor M1 is connected to the bias voltage NVB0, and the drain of NMOS transistor M1 is connected to the source of NMOS transistor M0.

[0030] The source of NMOS transistor M2 is grounded, the gate of NMOS transistor M2 is connected to the output of a 2-to-1 multiplexer MUX, and the drain of NMOS transistor M2 is connected to the source of NMOS transistor M1.

[0031] The input terminal of the 2-to-1 multiplexer MUX is connected to the two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator, and the output terminal of the 2-to-1 multiplexer MUX is connected to the gate of the NMOS transistor M2.

[0032] The adaptive adjustment circuit I2 for the switch bias voltage includes a sampling switch NMOS transistor M4, a sampling capacitor C1, and a threshold voltage boosting operational amplifier circuit. The threshold voltage boosting operational amplifier circuit includes NMOS transistors M5, M6, M7, M8, M9, M12, PMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, and M10, a capacitor C2, and a resistor R1. The source of NMOS transistor M4 is connected to the gate of NMOS transistor M8, the gate of NMOS transistor M4 is connected to the sampling switch pulse signal SAMPLE_PULSE, and the drain of NMOS transistor M4 is connected to the drain of NMOS transistor M3 in the phase interpolator output drive circuit I5.

[0033] The upper plate of the sampling capacitor C1 is connected to the source of the NMOS transistor M4, and the lower plate of the sampling capacitor C1 is grounded.

[0034] The source of NMOS transistor M5 is grounded, the gate of NMOS transistor M5 is connected to the drain of NMOS transistor M5, and the drain of NMOS transistor M5 is connected to the gate of NMOS transistor M6.

[0035] The source of NMOS transistor M6 is grounded, the gate of NMOS transistor M6 is connected to the drain of NMOS transistor M6, and the drain of NMOS transistor M6 is connected to the source of NMOS transistor M8.

[0036] The source of NMOS transistor M7 is grounded, the gate of NMOS transistor M7 is connected to the gate of NMOS transistor M6, and the drain of NMOS transistor M7 is connected to the gate of NMOS transistor M9.

[0037] The source of NMOS transistor M8 is connected to the source of NMOS transistor M9, the gate of NMOS transistor M8 is connected to the source of NMOS transistor M4, and the drain of NMOS transistor M8 is connected to the drain of PMOS transistor M10.

[0038] The source of NMOS transistor M9 is connected to the drain of NMOS transistor M6, the gate of NMOS transistor M9 is connected to the drain of NMOS transistor M7, and the drain of NMOS transistor M9 is connected to the drain of PMOS transistor M11.

[0039] The source of the PMOS transistor M10 is connected to VDD, the gate of the PMOS transistor M10 is connected to the source of the PMOS transistor M10, and the drain of the PMOS transistor M10 is connected to the gate of the PMOS transistor M11.

[0040] The source of the PMOS transistor M11 is connected to VDD, and the gate of the PMOS transistor M11 is connected to the gate of the PMOS transistor M10.

[0041] The two ends of the resistor R1 are connected to the drain of the PMOS transistor M11 and the lower plate of the capacitor C2, respectively.

[0042] The upper plate of capacitor C2 is connected to VDD, and the lower plate of capacitor C2 is connected to the gate of NMOS transistor M12.

[0043] The source of NMOS transistor M12 is connected to the drain of NMOS transistor M7, the gate of NMOS transistor M12 is connected to the gate of NMOS transistor M3, and the drain of NMOS transistor M12 is connected to VDD.

[0044] The input terminal of the current-mode analog-to-digital converter I3 is connected to the current-mode digital-to-analog converter control word I_SINK<15:0>, the enable terminal of the current-mode analog-to-digital converter I3 is connected to ENN_IDAC, and the output terminal of the current-mode analog-to-digital converter I3 is connected to the drain of the NMOS transistor M3 in the phase interpolator output drive circuit I5.

[0045] The input of the binary code to thermometer code decoder I4 is connected to the phase interpolator control word PI_CTRL<7:0>, and the output of the binary code to thermometer code decoder I4 is connected to the control words PI_CELL_CTRL<255:0> of the phase interpolator unit, respectively, and connected to the control terminals PI_CELL

[255] -PI_CELL[0] of the two-to-one multiplexer MUX in each phase interpolator unit.

[0046] The phase interpolator output drive circuit I5 includes an NMOS transistor M3, a reset PMOS transistor M13, a reset logic inverter INV0, and threshold adjustment inverters INV1-2. The source of the NMOS transistor M3 is connected to the input terminal of the inverter INV1, the gate of the NMOS transistor M3 is connected to the gate of the NMOS transistor M12, and the drain of the NMOS transistor M3 is connected to the output terminal of the current-mode analog-to-digital converter I3.

[0047] The source of the PMOS transistor M13 is connected to VDD, the gate of the PMOS transistor M13 is connected to the output terminal of the inverter INV0, and the drain of the PMOS transistor M13 is connected to the input terminal of the inverter INV1.

[0048] The input terminal of the inverter INV0 is connected to the phase interpolator output reset signal ENN_SWITCH_OUT, and the output terminal of the inverter INV0 is connected to the gate of the PMOS transistor M13.

[0049] The input terminal of inverter INV1 is connected to the source of NMOS transistor M3, the output terminal of inverter INV1 is connected to the input terminal of inverter INV2, and the output terminal of inverter INV2 is connected to the phase interpolator to output the clock signal PI_OUT.

[0050] The working principle of this invention is as follows: like Figure 1 As shown, the current-mode analog-to-digital converter I3 controls the total operating current of the phase interpolator array I1 through the current-mode digital-to-analog converter control word I_SINK<15:0>. Let the magnitude of the total operating current be... The controllable output current of the current-mode analog-to-digital converter I3 is... The quiescent operating current of the current-mode analog-to-digital converter I3 is Then we have: (1) like Figure 2 As shown, the phase interpolator array I1 in Region-II is controlled by the phase interpolator unit control word PI_CELL_CTRL<255:0>. The current intensity discharges the charge pre-stored at the output node of the current-mode analog-to-digital converter I3; the phase interpolator array I1 in Region-III is fixed. The current intensity is used to discharge the remaining charge at the output node of the current-mode analog-to-digital converter I3. Assume the output node of the current-mode analog-to-digital converter has a pre-stored charge of [value missing] in Region-I. The output node of the current-mode analog-to-digital converter I3 discharges charge in Region-II. The output node of the current-mode analog-to-digital converter I3 discharges charge in Region-III. The output node of the current-mode analog-to-digital converter I3 has a remaining charge of [missing information] in Region-III. The total capacitance to ground at the output node of the current-mode analog-to-digital converter I3 is The phase difference between the two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator is The clock periods of the two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator are: The phase interpolator array I1 inserts phase in Region-III as follows: The flip threshold of the phase interpolator output drive circuit I5 is Then we have: (2) (3) (4) (5) (6) Combining equations (2), (3), (4), (5), and (6), we obtain: (7) Phase interpolator array I1 inserts phase and control words in Region-III The above calculations, which exhibit a standard linear relationship, are all performed under the premise that the phase interpolator output drive circuit I5 flips during Region-III. The actual design incorporates a switch bias voltage adaptive adjustment circuit I2 and an NMOS transistor M3 to ensure the stability of this premise. By controlling the NMOS transistor M4 to sample the voltage signal at the output node of the current-mode analog-to-digital converter I3 during the end phase of Region-II when PI_CTRL<7:0>=0x00 during the phase in which the phase interpolator does not perform phase interpolation, the sampling switch pulse signal SAMPLE_PULSE controls the NMOS transistor M4 to sample the voltage signal at the end of Region-II when PI_CTRL<7:0>=0x00. Furthermore, the threshold voltage is raised to obtain the pseudo-differential amplifier negative feedback adjustment. This ensures that the flip state of the phase interpolator output drive circuit I5 always occurs in Region-III, guaranteeing the linearity and accuracy of the phase interpolation. Based on the clock frequencies of the two-phase clock input signals PI_INφ1 and PI_INφ2 of the input phase interpolator, the current-mode digital-to-analog converter control word I_SINK<15:0> is adjusted in real time. Specifically, the operation is as follows: When the input clock frequency is high, the output current of the current-mode analog-to-digital converter I3 is appropriately increased through the current-mode digital-to-analog converter control word I_SINK<15:0>; when the input clock frequency is low, the output current of the current-mode analog-to-digital converter I3 is appropriately decreased through the current-mode digital-to-analog converter control word I_SINK<15:0>, thereby ensuring the wide-range applicability of the integrating-mode phase interpolator circuit.

[0051] The high-level input voltage of inverter INV1 satisfies The low-level input voltage of inverter INV2 satisfies The interpolation result of the phase interpolator output drive circuit I5 is ensured to occur in the preset phase interval, namely the Region-III interval, by using a non-CMOS standard flip threshold drive circuit.

[0052] In the binary-to-thermometer code decoder I4, digital control codes are typically used to drive the current source array or select delay paths in the control code generation circuit of the phase interpolator to achieve high linearity and high resolution phase step control. Traditionally, directly using binary control codes for circuit switching control easily introduces code-switching glitch, especially when there are multiple bit flips between adjacent codes, which can easily cause sudden current changes and thus exacerbate output phase jitter. To reduce the above interference and improve control linearity, this invention uses a binary-to-thermometer code decoder I4 to decode the input binary control signal into a monotonically increasing thermometer code output. This encoding method ensures that only one bit changes between any two adjacent control codes, thereby significantly reducing transient current disturbances caused by digital flips and improving the phase stability of the interpolator. Furthermore, thermometer codes possess inherent monotonicity and symmetry, allowing for the use of regular, symmetrical current cell array structures in layout design. This facilitates matching layouts, thereby reducing non-ideal errors caused by layout mismatches and improving the robustness and consistency of circuits under variations in process, voltage, and temperature (PVT).

[0053] It should be noted that the present invention has the following characteristics: Based on the principle of current integration, this invention achieves high-precision adjustment of the output phase through an adjustable working current source, an adaptive bias switch, and a current unit controlled by a thermometer code. Compared with the traditional direct control type phase interpolator structure, this invention introduces a current integration mechanism to achieve smooth and continuous phase transitions, effectively suppressing transient interference caused by control code switching.

[0054] This invention employs an on-chip integrated binary-to-thermometer (B2T) decoder to monotonically control the current source array, improving phase control linearity while enhancing layout symmetry and mismatch robustness. The interpolator core unit further supports configurable current range and adjusts the operating state of the switching transistors through an adaptive bias voltage loop based on load conditions, enabling stable, low-jitter, high-resolution phase interpolation in various operating modes from low-speed to high-speed and from narrowband to wideband.

[0055] The integral-modulus phase interpolator circuit proposed in this invention combines high precision, high linearity, low jitter, wide bandwidth adaptability, and good process robustness. It is particularly suitable for high-speed digital communication, fractional-N PLL, all-digital PLL, and high-resolution clock synthesis systems, and has important engineering application value for improving the overall performance of PLL systems.

[0056] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0057] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

[0058] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the present invention. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. An integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability, characterized in that, This includes the two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator, the current-mode digital-to-analog converter control word I_SINK<15:0>, the phase interpolator control word PI_CTRL<7:0>, the phase interpolator cell control word PI_CELL_CTRL<255:0>, the current-mode analog-to-digital converter enable signal ENN_IDAC, the phase interpolator output reset signal ENN_SWITCH_OUT, the sampling switch pulse signal SAMPLE_PULSE, the phase interpolator output clock signal PI_OUT, the phase interpolator array (I1), the switch bias voltage adaptive adjustment circuit (I2), the current-mode analog-to-digital converter (I3), the binary code to thermometer code decoder (I4), and the phase interpolator output drive circuit (I5). The phase interpolator output drive circuit (I5) is connected to the current-mode analog-to-digital converter (I3), the phase interpolator array (I1), and the switch bias voltage adaptive adjustment circuit (I2). The binary code to thermometer code decoder (I4) is connected to the phase interpolator array (I1). The two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator are connected to the phase interpolator array (I1). The current-mode digital-to-analog converter control word I_SINK<15:0> is connected to the current-mode analog-to-digital converter (I3). The phase interpolator control word PI_CTRL<7:0> is connected to the binary code to thermometer code decoder (I2). The phase interpolator unit control word PI_CELL_CTRL<255:0> is connected to the phase interpolator array (I1), the current-mode analog-to-digital converter enable signal ENN_IDAC is connected to the current-mode analog-to-digital converter (I3), the phase interpolator output reset signal ENN_SWITCH_OUT is connected to the phase interpolator output drive circuit (I5), the sampling switch pulse signal SAMPLE_PULSE is connected to the switch bias voltage adaptive adjustment circuit (I2), and the phase interpolator output clock signal PI_OUT is connected to the phase interpolator output drive circuit (I5). The adaptive adjustment circuit for the switch bias voltage (I2) includes a sampling switch NMOS transistor M4, a sampling capacitor C1, and a threshold voltage boosting operational amplifier circuit. The threshold voltage boosting operational amplifier circuit includes NMOS transistors M5, M6, M7, M8, M9, M12, PMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, capacitor C2, and resistor R1. The source of NMOS transistor M4 is connected to the gate of NMOS transistor M8, the gate of NMOS transistor M4 is connected to the sampling switch pulse signal SAMPLE_PULSE, and the drain of NMOS transistor M4 is connected to the drain of NMOS transistor M3 in the phase interpolator output drive circuit (I5). The upper plate of the sampling capacitor C1 is connected to the source of the NMOS transistor M4, and the lower plate of the sampling capacitor C1 is grounded. The source of NMOS transistor M5 is grounded, the gate of NMOS transistor M5 is connected to the drain of NMOS transistor M5, and the drain of NMOS transistor M5 is connected to the gate of NMOS transistor M6. The source of NMOS transistor M6 is grounded, the gate of NMOS transistor M6 is connected to the drain of NMOS transistor M6, and the drain of NMOS transistor M6 is connected to the source of NMOS transistor M8. The source of NMOS transistor M7 is grounded, the gate of NMOS transistor M7 is connected to the gate of NMOS transistor M6, and the drain of NMOS transistor M7 is connected to the gate of NMOS transistor M9. The source of NMOS transistor M8 is connected to the source of NMOS transistor M9, and the drain of NMOS transistor M8 is connected to the drain of PMOS transistor M10. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M6, and the drain of NMOS transistor M9 is connected to the drain of PMOS transistor M11. The source of the PMOS transistor M10 is connected to VDD, the gate of the PMOS transistor M10 is connected to the source of the PMOS transistor M10, and the drain of the PMOS transistor M10 is connected to the gate of the PMOS transistor M11. The source of the PMOS transistor M11 is connected to VDD; The two ends of the resistor R1 are connected to the drain of the PMOS transistor M11 and the lower plate of the capacitor C2, respectively. The upper plate of capacitor C2 is connected to VDD, and the lower plate of capacitor C2 is connected to the gate of NMOS transistor M12. The source of NMOS transistor M12 is connected to the drain of NMOS transistor M7, the gate of NMOS transistor M12 is connected to the gate of NMOS transistor M3, and the drain of NMOS transistor M12 is connected to VDD.

2. The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability according to claim 1, characterized in that, The phase interpolator array (I1) is composed of 256 identical phase interpolator units PI_CELL[255]-PI_CELL[0] connected in parallel.

3. The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability according to claim 2, characterized in that, Each phase interpolator unit includes an NMOS transistor M0, an NMOS transistor M1, an NMOS transistor M2, and a 2-to-1 multiplexer MUX; The source of NMOS transistor M0 is connected to the drain of NMOS transistor M1, the gate of NMOS transistor M0 is connected to the bias voltage NVB1, and the drain of NMOS transistor M0 is connected to the drain of NMOS transistor M3 in the phase interpolator output drive circuit (I5). The source of NMOS transistor M1 is connected to the drain of NMOS transistor M2, and the gate of NMOS transistor M1 is connected to the bias voltage NVB0. The source of the NMOS transistor M2 is grounded, and the gate of the NMOS transistor M2 is connected to the output of the 2-to-1 multiplexer MUX. The input of the 2-to-1 multiplexer MUX is connected to the two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator.

4. The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability according to claim 1, characterized in that, The input terminal of the current-mode analog-to-digital converter (I3) is connected to the current-mode digital-to-analog converter control word I_SINK<15:0> and the current-mode analog-to-digital converter enable signal ENN_IDAC, and the output terminal of the current-mode analog-to-digital converter (I3) is connected to the drain of NMOS transistor M3 in the phase interpolator output drive circuit (I5).

5. The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability according to claim 3, characterized in that, The input of the binary code to thermometer code decoder (I4) is connected to the phase interpolator control word PI_CTRL<7:0>, and the output of the binary code to thermometer code decoder (I4) is connected to the phase interpolator unit control word PI_CELL_CTRL<255:0> and the control terminals PI_CELL[255]-PI_CELL[0] of the two-to-one multiplexer MUX in each phase interpolator unit respectively.

6. The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability according to claim 3, characterized in that, The phase interpolator output drive circuit (I5) includes an NMOS transistor M3, a reset PMOS transistor M13, a reset logic inverter INV0, and a threshold adjustment inverter INV1-2. The source of NMOS transistor M3 is connected to the input terminal of inverter INV1, the gate of NMOS transistor M3 is connected to the gate of NMOS transistor M12, and the drain of NMOS transistor M3 is connected to the output terminal of current-mode analog-to-digital converter I3. The source of the PMOS transistor M13 is connected to VDD, the gate of the PMOS transistor M13 is connected to the output terminal of the inverter INV0, and the drain of the PMOS transistor M13 is connected to the input terminal of the inverter INV1. The input terminal of the inverter INV0 is connected to the phase interpolator output reset signal ENN_SWITCH_OUT; The output of inverter INV1 is connected to the input of inverter INV2, and the output of inverter INV2 is connected to the phase interpolator to output the clock signal PI_OUT.

7. The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability according to claim 1, characterized in that, High linearity of interpolation is achieved by negative feedback generated from the output node voltage of the phase interpolator array (I1) to produce the bias voltage of the switching transistor in the phase interpolator output drive circuit (I5).

8. The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability according to claim 1, characterized in that, The phase interpolator output drive circuit (I5) uses several inverters with non-standard thresholds to perform step-by-step threshold fine-tuning to obtain a CMOS clock signal output with a standard threshold.

9. The integral-mode phase interpolator circuit with strong robustness and wide frequency adaptability according to claim 1, characterized in that, The interpolation phase of the phase interpolator array (I1) in Region-III for: in, This represents the total operating current. The total capacitance to ground at the output node of the current-mode analog-to-digital converter (I3) is [not specified]. The phase difference between the two-phase clock input signals PI_INφ1 and PI_INφ2 of the phase interpolator. The clock periods of the two-phase clock input signals PI_INφ1 and PI_INφ2 for the phase interpolator. The flip threshold of the phase interpolator output drive circuit (I5) is used. For control words.

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