Method for shortening the miller platform in an igbt drive circuit

Abstract

This invention discloses a method for shortening the Miller plateau in an IGBT driver circuit. A PWM signal is input to a slow rising edge detection circuit module SRED. The output signal SR of SRED and the rising edge detection signal RE of the edge detection circuit module ED are both connected to an AND gate in the GM_P path. The AND gate in the GM_P path is connected in series with a NOT gate to convert the PWM signal from "low" to "high," generating a control signal GM_P. Simultaneously, a PWM signal is input to a slow falling edge detection circuit module SFED. The output signal SF of SFED and the falling edge detection signal FE of the edge detection circuit module ED are both connected to an AND gate in the GM_N path, generating a control signal GM_N. The control signals GM_P and GM_N enhance the output capability of the driver integrated circuit during the Miller plateau period, shortening the duration of the Miller plateau voltage.

Description

Technical Field

[0001] This invention relates to IGBT drive circuits, and in particular to a method for shortening the Miller plateau in an IGBT drive circuit. Background Technology

[0002] The Miller plateau is a plateau in the gate voltage of power semiconductor devices (such as MOSFETs / IGBTs) during switching, as shown in the attached diagram. Figure 1 , 2 As shown, in the IGBT drive circuit, the pulse width modulation (PWM) signal controls the IGBT to turn on and off. However, its gate voltage (VG) will have a voltage plateau during the rise / fall process due to the influence of Miller capacitance, namely the "Miller plateau". The existence of this plateau is related to the limited driving capability of the driver IC, which reduces the circuit response speed, increases switching losses, and affects the service life of the IGBT and the reliability of the system.

[0003] Therefore, shortening the duration of the Miller plateau voltage can improve the switching performance of the IGBT. Summary of the Invention

[0004] Purpose of the invention: The purpose of this invention is to provide a method for shortening the Miller plateau in an IGBT drive circuit. This purpose is achieved through circuit design, thereby improving the switching performance of the IGBT.

[0005] Technical Solution: A method for shortening the Miller plateau in an IGBT driver circuit. The PWM signal is input to a slow rising edge detection circuit module SRED. The output signal SR of SRED and the rising edge detection signal RE of the edge detection circuit module ED are both connected to an AND gate in the GM_P path. The AND gate in the GM_P path is connected in series with a NOT gate to convert the PWM signal from "low" to "high," generating a control signal GM_P. Simultaneously, the PWM signal is input to a slow falling edge detection circuit module SFED. The output signal SF of SFED and the falling edge detection signal FE of the edge detection circuit module ED are both connected to an AND gate in the GM_N path, generating a control signal GM_N. The control signals GM_P and GM_N enhance the output capability of the driver integrated circuit during the Miller plateau period, shortening the duration of the Miller plateau voltage.

[0006] Furthermore, the edge detection circuit module ED is as follows:

[0007] Set up comparator CMP1. The non-inverting input of comparator CMP1 is connected to the gate of IGBT to obtain the gate voltage VG signal. The inverting input is connected to the rising edge threshold voltage VTH1. Comparator CMP1 is connected to the operating power supply and ground GND. Comparator CMP1 outputs voltage V1.

[0008] Set up comparator CMP2. The non-inverting input of comparator CMP2 is connected to the gate of IGBT to obtain the gate voltage VG signal. The inverting input is connected to the falling edge threshold voltage VTH2. Comparator CMP2 is connected to the operating power supply and ground GND. The output voltage of comparator CMP2 is V2.

[0009] Voltages V1 and V2 are XORed to form the rising edge detection and falling edge detection edge detection circuit module ED signal and PWM signal, respectively. The rising edge detection signal RE and falling edge detection signal FE are output to monitor the edge changes of gate voltage VG. Among them, the AND gate of the falling edge detection signal FE path is connected to the NOT gate to change the PWM signal from "low" to "high".

[0010] Furthermore, the slow rising edge detection circuit module SRED is configured as follows: the comparator CMP3 is configured such that the threshold current IthH and the monitoring current ISH generated by the IGBT gate through the current mirror are both connected to the non-inverting input of the comparator CMP3. When the upward slope of the gate voltage VG is too large, the monitoring current ISH exceeds the threshold current IthH, the output of the comparator CMP3 changes from high to low, and the slow rising edge SR control is triggered.

[0011] The slow falling edge detection circuit module SFED is configured as follows: the comparator CMP4 is set up, and the threshold current IthL and the monitoring current ISL generated by the IGBT gate through the current mirror are both connected to the non-inverting input of the comparator CMP4. When the downward slope of the gate voltage VG is too large, the monitoring current ISL exceeds the threshold current IthL, the output of the comparator CMP4 changes from high to low, and the slow falling edge SF control is triggered.

[0012] Furthermore, the current mirror circuit uses capacitor rectification to monitor the slope change of the gate voltage VG signal.

[0013] Furthermore, in the slow rising edge detection circuit module SRED, capacitor C1 is used for rectification in the current mirror circuit; in the slow falling edge detection circuit module SFED, capacitor C2 is used for rectification in the current mirror circuit.

[0014] Beneficial effects: By designing a circuit that combines edge detection and slope monitoring, this invention accurately captures edge and slope changes in the gate voltage VG signal, dynamically enhancing the output capability of the driver integrated circuit. Compared to traditional fixed drive schemes, the Miller plateau duration during the IGBT turn-on / turn-off phase is shortened, reducing switching losses, extending device lifespan, and improving circuit reliability. Attached Figure Description

[0015] Figure 1 This is the overall logic control circuit of the method of the present invention;

[0016] Figure 2 for Figure 1 Waveform diagram of the circuit;

[0017] Figure 3 For the edge detection circuit module ED logic control circuit;

[0018] Figure 4 for Figure 3 Waveform diagram of the circuit;

[0019] Figure 5 The SRED logic control circuit is for the slow rising edge detection circuit module.

[0020] Figure 6 for Figure 5 Waveform diagram of the circuit;

[0021] Figure 7 For the slow falling edge detection circuit module SFED logic control circuit;

[0022] Figure 8 for Figure 7 Waveform diagram of the circuit. Detailed Implementation

[0023] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0024] A method for shortening the Miller plateau in an IGBT driver circuit is proposed. This method involves edge detection and slope monitoring of the gate voltage VG to shorten the Miller plateau. The overall logic control circuit is shown in the attached figure. Figure 1 As shown, the PWM signal is input to the slow rising edge detection circuit module SRED. The output signal SR of the slow rising edge detection circuit module SRED and the rising edge detection signal RE output from the edge detection circuit module ED are both connected to an AND gate in the GM_P path. The AND gate in the GM_P path is connected in series with an NOT gate to convert the PWM signal "low" to "high" for matching logic, generating the control signal GM_P. At the same time, the PWM signal is input to the slow falling edge detection circuit module SFED. The output signal SF of the slow falling edge detection circuit module SFED and the falling edge detection signal FE output from the edge detection circuit module ED are both connected to an AND gate in the GM_N path, generating the control signal GM_N. The control signals GM_P and GM_N enhance the output capability of the driver integrated circuit during the Miller plateau period and shorten the duration of the Miller plateau voltage.

[0025] Edge detection circuit module ED, as shown in the attached image Figure 3 As shown:

[0026] Set up comparator CMP1. Connect the non-inverting input (+) of comparator CMP1 to the IGBT gate to obtain the gate voltage VG signal. Connect the inverting input (-) to the set rising edge threshold voltage VTH1. Connect comparator CMP1 to the operating power supply and ground GND to ensure that comparator CMP1 works normally. When the gate voltage VG signal rises to the rising edge threshold voltage VTH1, comparator CMP1 flips and outputs voltage V1.

[0027] Comparator CMP2 is configured such that its non-inverting input (+) is connected to the IGBT gate to obtain the gate voltage VG signal, and its inverting input (-) is connected to the set falling edge threshold voltage VTH2. Comparator CMP2 is connected to the operating power supply and ground GND to ensure that comparator CMP2 works normally. When the gate voltage VG signal drops to the falling edge threshold voltage VTH2, comparator CMP2 flips and outputs voltage V2.

[0028] Voltages V1 and V2 are XORed to form the rising edge detection signal ED and falling edge detection signal PWM signal in the edge detection circuit module. The falling edge detection signal FE is then ANDed with the AND gate in series with the NOT gate, converting the PWM signal from "low" to "high" for matching logic. This outputs the rising edge detection signal RE and the falling edge detection signal FE, respectively. The signal waveforms are shown in the attached diagram. Figure 4 As shown, the edge changes of the gate voltage VG are monitored to achieve accurate capture of the edge changes of the gate voltage VG signal.

[0029] As attached Figure 5 , 6 As shown, the slow rising edge detection circuit module SRED is configured as follows: the comparator CMP3 is set, and the threshold current IthH and the monitoring current ISH generated by the IGBT gate through the current mirror are both connected to the non-inverting input (+) of the comparator CMP3. According to the gate voltage VG input of the IGBT gate, when the upward slope of the gate voltage VG is too large, the monitoring current ISH exceeds the threshold current IthH, the output of the comparator CMP3 changes from high to low, and the slow rising edge SR control is triggered.

[0030] As attached Figure 7 , 8 As shown, the slow falling edge detection circuit module SFED is configured as follows: the comparator CMP4 is set, and the threshold current IthL and the monitoring current ISL generated by the IGBT gate through the current mirror are both connected to the non-inverting input (+) of the comparator CMP4. According to the gate voltage VG input of the IGBT gate, when the downward slope of the gate voltage VG is too large, the monitoring current ISL exceeds the threshold current IthL, the output of the comparator CMP4 changes from high to low, and the slow falling edge SF control is triggered.

[0031] The current mirror circuit uses capacitor rectification to monitor the slope change of the gate voltage VG signal. The monitored current generated by the current mirror is compared with the threshold current to determine the magnitude of the slope. For example, in the slow rising edge detection circuit module SRED, capacitor C1 is used for rectification in the current mirror circuit; in the slow falling edge detection circuit module SFED, capacitor C2 is used for rectification. The capacitance values ​​of capacitors C1 and C2 are selected according to the rectification requirements, for example, 10pF.

[0032] Slow rising edge detection circuit and slow falling edge detection circuit are used to identify abnormal gate voltage VG slope and provide trigger signals to drive the output capability of the integrated circuit during the strong Miller plateau.

[0033] Through append Figure 2 visible:

[0034] When there is no slope monitoring (blue VG signal, RE signal, FE signal): During the rise / fall of the gate voltage VG signal, the Miller plateau (constant voltage stage) lasts for a long time and is not triggered by control signals GM_P and GM_N;

[0035] When slope monitoring is active (red VG signal, RE signal, FE signal): When the gate voltage VG signal rises to the rising edge threshold voltage VTH1, RE is triggered, triggering the slow rising edge SR control. The slow rising edge detection circuit module SRED detects the slope abnormality, the control signal GM_P takes effect, the output of the driver integrated circuit is enhanced, and the gate voltage VG quickly moves away from the rising edge Miller plateau; When the gate voltage VG signal falls to the falling edge threshold voltage VTH2, FE is triggered, triggering the slow falling edge SF control. The slow falling edge detection circuit module SFED detects the slope abnormality, the control signal GM_N takes effect, the output of the driver integrated circuit is enhanced, and the gate voltage VG quickly moves away from the falling edge Miller plateau.

Claims

1. A method of shortening the Miller plateau in an IGBT drive circuit, characterized by: The PWM signal is input to the slow rising edge detection circuit module SRED. The output signal SR of the slow rising edge detection circuit module SRED and the rising edge detection signal RE output by the edge detection circuit module ED are both connected to an AND gate in the GM_P path. The AND gate in the GM_P path is connected in series with an NOT gate to convert the PWM signal from "low" to "high" and generate the control signal GM_P. At the same time, the PWM signal is input to the slow falling edge detection circuit module SFED. The output signal SF of the slow falling edge detection circuit module SFED and the falling edge detection signal FE output by the edge detection circuit module ED are both connected to an AND gate in the GM_N path to generate the control signal GM_N. The output capability of the drive integrated circuit during the Miller platform period is enhanced by the control signals GM_P and GM_N, and the duration of the Miller platform voltage is shortened.

2. The method of shortening the Miller plateau in an IGBT drive circuit according to claim 1, characterized in that: The edge detection circuit module ED is: Set up comparator CMP1. The non-inverting input of comparator CMP1 is connected to the gate of IGBT to obtain the gate voltage VG signal. The inverting input is connected to the rising edge threshold voltage VTH1. Comparator CMP1 is connected to the operating power supply and ground GND. Comparator CMP1 outputs voltage V1. Set up comparator CMP2. The non-inverting input of comparator CMP2 is connected to the gate of IGBT to obtain the gate voltage VG signal. The inverting input is connected to the falling edge threshold voltage VTH2. Comparator CMP2 is connected to the operating power supply and ground GND. The output voltage of comparator CMP2 is V2. Voltages V1 and V2 are XORed to form the rising edge detection and falling edge detection edge detection circuit module ED signal and PWM signal, respectively. The rising edge detection signal RE and falling edge detection signal FE are output to monitor the edge change of gate voltage VG. Among them, the AND gate of the falling edge detection signal FE path is connected to the NOT gate to convert the PWM signal "low" to "high".

3. The method for shortening the Miller plateau in the IGBT drive circuit according to claim 1, characterized in that: The slow rising edge detection circuit module SRED is configured as follows: the comparator CMP3 is set up, and the threshold current IthH and the monitoring current ISH generated by the IGBT gate through the current mirror are both connected to the non-inverting input of the comparator CMP3. When the upward slope of the gate voltage VG is too large, the monitoring current ISH exceeds the threshold current IthH, the output of the comparator CMP3 changes from high to low, and the slow rising edge SR control is triggered. The slow falling edge detection circuit module SFED is configured as follows: the comparator CMP4 is set up, and the threshold current IthL and the monitoring current ISL generated by the IGBT gate through the current mirror are both connected to the non-inverting input of the comparator CMP4. When the downward slope of the gate voltage VG is too large, the monitoring current ISL exceeds the threshold current IthL, the output of the comparator CMP4 changes from high to low, and the slow falling edge SF control is triggered.

4. The method for shortening the Miller plateau in the IGBT drive circuit according to claim 3, characterized in that: The current mirror circuit uses capacitor rectification to monitor the slope change of the gate voltage VG signal.

5. The method for shortening the Miller plateau in the IGBT drive circuit according to claim 4, characterized in that: In the Slow Rising Edge Detection Circuit Module SRED, capacitor C1 is used for rectification in the current mirror circuit; in the Slow Falling Edge Detection Circuit Module SFED, capacitor C2 is used for rectification in the current mirror circuit.

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