Log hierarchical synchronization system based on ARM-MCU heterogeneous system

Abstract

The application relates to a log hierarchical synchronization system based on an ARM-MCU heterogeneous system and belongs to the technical field of embedded systems, wherein the system comprises the following: an MCU slave machine is connected with an FPGA module through an LVDS bus, the FPGA module is connected with an ARM host machine through an Ethernet, the MCU slave machine is used for sending generated logs to the FPGA module and storing the logs containing key events through a ring buffer, the FPGA module is used for encapsulating the logs to obtain UDP messages and sending the UDP messages to the ARM host machine, the ARM host machine is used for analyzing the UDP messages to obtain the logs, obtaining system time, writing the logs and the system time into a log file, and hierarchically storing the logs based on priorities of the logs, and the system provided by the application can record time stamps uniformly by the ARM, avoids the problem of time asynchronization, records and manages the logs uniformly by the ARM end, supports million-level log recording, and can save complete logs of system running.

Description

Technical Field

[0001] This invention relates to the field of embedded system technology, and in particular to a log hierarchical synchronization system based on an ARM-MCU heterogeneous system. Background Technology

[0002] Currently, the industrial IoT field generally adopts a distributed architecture with ARM architecture master and multiple MCU slaves. With the development of Industry 5.0, new requirements are put forward for fault diagnosis of distributed systems. It is necessary to support the collaborative logging of 8-16 MCU nodes to record the operating status of each MCU, which requires a large amount of physical storage.

[0003] In existing log management systems, the MCU is limited by its on-chip Flash capacity (typically <256KB), making it unable to store complete historical logs. Traditional TF card expansion solutions increase hardware costs by over 30%. When using UART serial port to transmit logs, the error rate is as high as 10⁻³ (actual measured data), and the main processor's interrupt load increases by over 40%. Local clock deviations in various devices cause log timestamp errors, potentially leading to millisecond-level misjudgments of critical event sequence in scenarios such as power systems.

[0004] Existing MCU devices have limited local storage space, making it impossible to save complete system operation logs. Using serial port log transmission would consume a lot of MCU host resources, and cross-device log timestamps are difficult to synchronize. Furthermore, MCU performance is limited, and due to hardware resource constraints, it is impossible to record complete system operation logs. Summary of the Invention

[0005] In view of this, it is necessary to provide a log hierarchical synchronization system based on ARM-MCU heterogeneous systems to solve the problem of how to record the complete log of a distributed system and realize log synchronization.

[0006] To address the aforementioned problems, this invention provides a log hierarchical synchronization system based on an ARM-MCU heterogeneous system, comprising: MCU slave, FPGA module and ARM master; The MCU slave is connected to the FPGA module via an LVDS bus, and the FPGA module is connected to the ARM host via an Ethernet connection. The MCU slave is used to send the generated logs to the FPGA module and store the logs containing key events through a circular buffer; The FPGA module is used to encapsulate the logs into UDP packets and send the UDP packets to the ARM host; The ARM host is used to parse the UDP packets to obtain the logs and the system time, write the logs and the system time into a log file, and store the logs hierarchically based on their priority.

[0007] In one possible implementation, the ARM host is specifically used for: Logs containing emergency events are stored in a memory queue, while regular logs are stored in eMMC storage.

[0008] In one possible implementation, the ARM host is further used for: The log and system time are written to the local disk, and then written to the log server via the syslog protocol.

[0009] In one possible implementation, the ARM host is further used for: The system time is converted into a string, and the system time and the log are concatenated and written to the log file.

[0010] In one possible implementation, the ARM host communicates with the host computer via the TCP protocol; the host computer is used to send a log read command to the ARM host, and the log read command is used to obtain the log.

[0011] In one possible implementation, the ARM host includes: The SCPI parsing module is used to parse the read log command and read the critical error log based on the read log command.

[0012] In one possible implementation, the UDP message includes: Synchronization header, type, target identifier, source identifier, current frame length, application layer data, and synchronization tail.

[0013] In one possible implementation, the MCU slave is specifically used for: Collect sensor data and generate logs based on the sensor data; The MCU slave device is also used to send fault and abnormal configuration parameters during MCU slave device operation to the ARM host via log upload.

[0014] In one possible implementation, the ARM master uses a Cortex-A7 processor; the MCU slave uses an STM32F407.

[0015] The beneficial effects of this invention are as follows: The log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided by this invention generates logs through the MCU slave device and sends the logs to the FPGA module. The FPGA module encapsulates the logs into UDP packets and sends the UDP packets to the ARM host. The ARM host parses the UDP packets to obtain the logs and the system time. The logs and system time are written to a log file and stored hierarchically according to priority. The logs uploaded by the MCU do not record the time; the timestamps are uniformly recorded by the ARM, avoiding the problem of time synchronization. The ARM end uniformly records and manages the logs, which can support millions of log records, thus saving a complete log of system operation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of an embodiment of the log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided by the present invention; Figure 2 A schematic diagram of the log protocol format provided by this invention; Figure 3 This is a schematic diagram of the system module structure provided by the present invention; Figure 4 A schematic diagram of the software communication structure provided by the present invention; Figure 5 This is one of the flowcharts of the log processing module software provided by the present invention; Figure 6 This is the second flowchart of the log processing module software provided by the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] In the description of the embodiments of the present invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0020] The terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a technical feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] This invention provides a log hierarchical synchronization system based on an ARM-MCU heterogeneous system, which will be described in detail below.

[0023] Figure 1 This is a schematic diagram of an embodiment of the log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided by the present invention, as shown below. Figure 1 As shown, the log hierarchical synchronization system based on the ARM-MCU heterogeneous system includes: MCU slave 110, FPGA module 120 and ARM master 130; The MCU slave 110 is connected to the FPGA module 120 via an LVDS bus, and the FPGA module 120 is connected to the ARM host 130 via an Ethernet. The MCU slave 110 is used to send the generated logs to the FPGA module 120 and store the logs containing key events through a circular buffer; The FPGA module 120 is used to encapsulate the log to obtain a UDP packet and send the UDP packet to the ARM host 130; The ARM host 130 is used to parse the UDP packets to obtain the logs and the system time, write the logs and the system time into a log file, and store the logs hierarchically based on their priority.

[0024] like Figure 1As shown, there can be multiple MCU slave devices. The MCU slave devices are connected to the FPGA module via a Low-Voltage Differential Signaling (LVDS) bus. The FPGA module is connected to the ARM host via Ethernet. After the data from the slave devices arrives at the FPGA module, it is uniformly encapsulated into network frames by the FPGA module and sent to the host. The ARM host parses the log frames and records the logs, which improves the system scalability.

[0025] The MCU slave device can process the data collected by the sensor and generate logs in real time, and send the generated logs to the FPGA module. The logs uploaded by the MCU do not record the time.

[0026] A circular buffer is an efficient data structure that uses a logical design where the beginning and end of the buffer are connected. It can temporarily store continuously generated data (such as logs collected by sensors, real-time data streams, etc.).

[0027] The MCU slave uses a circular buffer to store critical events (capacity optimized to 2KB).

[0028] After receiving the logs sent by the MCU slave, the FPGA module encapsulates the logs into UDP packets according to the User Datagram Protocol (UDP) format and sends the UDP packets to the ARM host.

[0029] The ARM host obtains logs by parsing UDP packets and retrieves the system time. After converting the system time into a string, it concatenates the system time and log information together and writes it to a log file for hierarchical storage.

[0030] In other words, the logs uploaded by the MCU slave device do not record the time; the timestamp is uniformly recorded by the ARM host, which avoids the problem of time asynchrony. Furthermore, the ARM end centrally records and manages the logs, supporting millions of log records, thus ensuring the preservation of a complete system operation log.

[0031] The ARM host stores logs in a hierarchical manner based on their priority. The ARM host can prioritize logs according to their real-time nature and importance, ensuring that critical logs (such as system errors and security events) are synchronized first, while secondary logs (such as debugging information) can be processed later.

[0032] In summary, the log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided in this embodiment of the invention generates logs through the MCU slave device and sends the logs to the FPGA module. The FPGA module encapsulates the logs into UDP packets and sends the UDP packets to the ARM host. The ARM host parses the UDP packets to obtain the logs and the system time. The logs and system time are written to a log file and stored hierarchically according to priority. The logs uploaded by the MCU do not record the time; the timestamps are uniformly recorded by the ARM, avoiding the problem of time asynchrony. The ARM end uniformly records and manages the logs, supporting millions of log records, thus saving a complete log of system operation.

[0033] In some embodiments of the present invention, the ARM host is specifically used for: Logs containing emergency events are stored in a memory queue, while regular logs are stored in eMMC storage.

[0034] The ARM host can prioritize and store logs in a hierarchical manner, enabling priority-based database management. Emergency events are stored in an in-memory queue to ensure rapid response and reliable retrieval. Regular logs are stored in eMMC storage for efficient management of massive amounts of routine logs.

[0035] The log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided in this embodiment of the invention enables the ARM host to ensure rapid response and reliable querying of emergency events, as well as efficient management of massive amounts of regular logs, achieving optimal configuration of the log system under resource constraints through hierarchical storage.

[0036] In some embodiments of the present invention, the ARM host is further used for: The logs and system time are written to the local disk, and then written to the log server via the syslog protocol.

[0037] While the ARM host writes logs to the local disk, it also transmits the logs to the log server via the syslog protocol and writes them to the log server.

[0038] The log hierarchical synchronization system based on ARM-MCU heterogeneous system provided in this embodiment of the invention ensures that logs are not lost when the network is interrupted or the log server fails by writing logs to the local disk. Logs can be directly queried locally, and logs can be written to the log server through the syslog protocol, thereby realizing centralized management of logs from multiple devices.

[0039] In some embodiments of the present invention, the ARM host is further used for: The system time is converted into a string, and the system time and the log are concatenated and written to the log file.

[0040] The ARM host obtains logs and system time by parsing UDP packets.

[0041] After converting the system time to a string, the system time and the corresponding string in the log are concatenated together and written to the log file for hierarchical storage.

[0042] In some embodiments of the present invention, the ARM host communicates with the host computer via the TCP protocol; the host computer is used to send a log read instruction to the ARM host, and the log read instruction is used to obtain the log.

[0043] In some embodiments of the present invention, the ARM host includes: The SCPI parsing module is used to parse the read log command and read the critical error log based on the read log command.

[0044] The host PC and the ARM host communicate via TCP protocol. For critical error logs, they can be obtained through commands. The ARM host integrates a Standard Commands for Programmable Instruments (SCPI) parsing module.

[0045] The PC communicates with the ARM host via the TCP protocol and sends a log read command via TCP, which can retrieve one system log entry at a time.

[0046] All logs from the ARM host are written to a log file for storage. For critical error logs, these logs are placed in a critical error log queue (queue length 20000), which the PC retrieves via the SCPI command.

[0047] In some embodiments of the present invention, the UDP message includes: Synchronization header, type, target identifier, source identifier, current frame length, application layer data, and synchronization tail.

[0048] Figure 2 This is a schematic diagram of the log protocol format provided by the present invention, such as... Figure 2 As shown, the data frame structure of a UDP packet includes: synchronization header (0xAABBCC), type, destination identifier, source identifier, current frame length, application layer data, and synchronization tail (0xDDEEFF).

[0049] The destination identifier and source identifier are used to indicate the destination address and source address, respectively. The source identifier is used to distinguish the slave address. UDP packets can also include an expandable 32-bit CRC checksum.

[0050] The slave device's logs are uploaded in string format according to the protocol. The application layer data format is as follows: :PSS[n]:MCU:LOG <type> , <message> Type: ERR and INF Message: errorcode,"error_description;device-dependent;date" For example: -200,"execution error;torque safety limit exceeded;1996 / 0 / 15 13:22:51.01".

[0051] Error codes can be found in Table 1, which shows the correspondence between log error codes, error levels, and log descriptions.

[0052] Table 1

[0053] In some embodiments of the present invention, the MCU slave is specifically used for: Collect sensor data and generate logs based on the sensor data; The MCU slave device is also used to send fault and abnormal configuration parameters during MCU slave device operation to the ARM host via log upload.

[0054] In some embodiments of the present invention, the ARM master uses a Cortex-A7 processor; the MCU slave uses an STM32F407.

[0055] The MCU slave corresponds to the slave node, which uses an STM32F407 MCU (256KB SRAM) and deploys a ring buffer log acquisition module.

[0056] The ARM host corresponds to the master control node, which uses an ARM Cortex-A7 processor (Linux 5.10 kernel) and is responsible for global log management.

[0057] The communication media include an Ethernet backup channel and an FPGA module LVDS communication link.

[0058] Figure 3 This is a schematic diagram of the system module structure provided by the present invention, such as... Figure 3 As shown, the analog board represents the slave device, and multiple boards can be added. In this embodiment of the invention, the slave device address numbers are specified as 1~10, and the ARM master address is 0.

[0059] This address is used for Figure 2 The protocol shown illustrates this: for slave-to-master communication, i.e., when the MCU slave transmits log information to the ARM master, the destination address is filled with 0, and the source identifier is filled with the address of the analog board.

[0060] The three-level log caching mechanism provided by this invention is as follows: MCU side: manages a 2KB circular buffer, with dynamic adjustment of the sampling rate (10-100Hz).

[0061] On the ARM side: Implement log priority-based database sharding (urgent events are stored in an in-memory queue, and regular logs are stored in eMMC storage).

[0062] While writing logs to the local disk, the ARM side also transmits the logs to the log server via the syslog protocol and writes them to the log server.

[0063] Figure 4 This is a schematic diagram of the software communication structure provided by the present invention, such as... Figure 4 As shown, the MCU slave is connected to the FPGA module via the LVDS bus, and the FPGA module is connected to the ARM host via Ethernet. After the data from the slave reaches the FPGA module, it is uniformly encapsulated into network frames by the FPGA module and sent to the host. The host parses the log frames and records the logs. The system has strong scalability.

[0064] The simulation board data is encapsulated into frames by the FPGA module and sent to the ARM host in the form of UDP.

[0065] The PC and ARM host communicate via TCP. For critical error logs, they can be retrieved via commands. The ARM host integrates an SCPI command parsing module. The PC connects to the ARM host via TCP and sends a read log command via TCP, which can retrieve one system log at a time.

[0066] The communication format between the slave MCU and the master ARM host, such as Figure 2 As shown. All logs from the ARM host are written to a log file for storage. For critical error logs, these logs are placed in a critical error log queue (queue length 20000), which the PC retrieves via commands.

[0067] For example, the log processing flow of the log hierarchical synchronization system based on ARM-MCU heterogeneous system provided by the present invention includes slave process and master process.

[0068] In the slave device process, the slave device's logs are uploaded as strings according to the format specified in the protocol. The data format is as follows: :PSS[n]:MCU:LOG <type> , <message>; Type: ERR and INF; Message: error code,"error_description;device-dependent;date".

[0069] In the master-slave process, the ARM master receives network packets from the slave and determines the frame type. Here, the frame type is defined as -200. If the received packet has a frame type of -200, it will enter the receive queue. The function of enqueuing is to quickly save the log information to the local cache. Figure 5 One of the flowcharts for the log processing module software provided by this invention is shown below, illustrating the enqueueing process. Figure 5 As shown.

[0070] The dequeue process takes place in a separate thread, and the flowchart for dequeueing is shown below. Figure 6 As shown, Figure 6 The second flowchart of the log processing module software provided by this invention shows that the purpose of this thread is to parse the queue information. After the ARM host parses the error log information, it will obtain the system time, convert the time into a string, concatenate it with the log information, and write it to the log file. For serious error logs, they will enter the serious error log queue cache. The PC can obtain the log information through commands.

[0071] The log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided by this invention has the following beneficial effects: (1) Efficient data synchronization and improved real-time performance: Through a hierarchical log mechanism, the system can prioritize logs based on their importance and real-time requirements, ensuring that critical logs (such as system errors and security events) are synchronized first, while secondary logs (such as debugging information) can be processed later. This hierarchical strategy significantly reduces unnecessary communication overhead and improves the overall efficiency of the system.

[0072] (2) Optimization of clock synchronization across heterogeneous cores: the logs uploaded by the slave MCU do not record the time, but are timestamped by the host after receiving the log information.

[0073] (3) Enhanced reliability: The hierarchical log synchronization method can combine verification mechanisms (such as CRC32) and readback comparison to ensure the consistency of log data in cross-core transmission.

[0074] In addition, by storing log information (such as data address, timestamp, etc.) in a structure, the system supports anomaly backtracking and auditing.

[0075] (4) Scalability and multi-protocol compatibility: This device can support a variety of communication interfaces (such as GPIB bus, RS485, Ethernet, etc.), making it easy to integrate into complex environments such as the Industrial Internet of Things.

[0076] The advantage of this invention lies in the deep integration of hierarchical logging strategies and heterogeneous core collaboration. This not only solves the real-time bottleneck of traditional log synchronization but also improves system reliability and energy efficiency through dynamic resource allocation and verification mechanisms. It integrates innovations from multiple fields, including heterogeneous computing, timestamp synchronization, and shared memory optimization, and is suitable for embedded systems, industrial control, and other scenarios.

[0077] Optionally, the heterogeneous system of the log hierarchical synchronization system based on the ARM-MCU heterogeneous system consists of: an ARM core (Cortex-A7@1.8GHz) running a Linux system, responsible for log aggregation and network transmission; and an MCU core (Cortex-M7@400MHz) carrying a Real-Time Operating System (RTOS) to handle sensor data acquisition and real-time log generation. Shared resources include 512KB dual-port SRAM (address 0x80000000) and an AXI bus (bandwidth 4GB / s). Security isolation is provided by dividing the MCU log storage area into secure domains (TEEs) via TrustZone, requiring authentication before access by the ARM core.

[0078] Optionally, the log grading criteria are as follows: MCU side: Emergency log (ERROR): Hardware failure, etc. (triggering inter-core interrupt).

[0079] Regular logs (WARNING / INFO): Stored in a circular buffer (capacity 256 entries, with CRC16 checksum).

[0080] ARM side: Application logs (DEBUG / TRACE): written to the local SQLite database via syslog.

[0081] The synchronization mechanism is as follows: In the emergency channel, the MCU directly wakes up the ARM core via IPC interrupt (RPMSG) to transmit the log header and critical data (delay <10μs).

[0082] In the batch channel, the ARM polls the shared memory every 100ms and copies the logs to DDR3 in batches via Direct Memory Access (DMA) (bandwidth utilization ≥85%).

[0083] The log hierarchical synchronization system based on ARM-MCU heterogeneous systems provided by this invention is applicable to various scenarios, especially to distributed log recording of ARM architecture Linux hosts and multiple MCU slaves in industrial control, Internet of Things and other scenarios, as shown below: Scenario 1: Industrial robot joint control. The MCU detects motor overcurrent (ERROR level), immediately interrupts the ARM core, synchronizes the log to the cloud, and triggers an emergency stop.

[0084] Scenario 2: Smart meter data acquisition. The MCU writes a current sampling log (INFO level) every 5 seconds, and the ARM performs batch compression before uploading via LoRaWAN.

[0085] The log hierarchical synchronization system based on ARM-MCU heterogeneous system provided by this invention reduces the real-time log synchronization latency from 50ms in the traditional solution to 15μs, and reduces the MCU-side static random-access memory (SRAM) usage by 40% (only retaining the level 2 log buffer).

[0086] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware (such as a processor, controller, etc.), and the computer program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0087] The log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.< / message> < / type> < / message> < / type>

Claims

1. A log hierarchical synchronization system based on an ARM-MCU heterogeneous system, characterized in that, include: MCU slave, FPGA module and ARM master; The MCU slave is connected to the FPGA module via an LVDS bus, and the FPGA module is connected to the ARM host via an Ethernet connection. The MCU slave is used to send the generated logs to the FPGA module and store the logs containing key events through a circular buffer; The FPGA module is used to encapsulate the logs into UDP packets and send the UDP packets to the ARM host; The ARM host is used to parse the UDP packets to obtain the logs and the system time, write the logs and the system time into a log file, and store the logs hierarchically based on their priority.

2. The log hierarchical synchronization system based on an ARM-MCU heterogeneous system according to claim 1, characterized in that, The ARM host is specifically used for: Logs containing emergency events are stored in a memory queue, while regular logs are stored in eMMC storage.

3. The log hierarchical synchronization system based on an ARM-MCU heterogeneous system according to claim 1, characterized in that, The ARM host is also used for: The log and system time are written to the local disk, and then written to the log server via the syslog protocol.

4. The log hierarchical synchronization system based on an ARM-MCU heterogeneous system according to claim 1, characterized in that, The ARM host is also used for: The system time is converted into a string, and the system time and the log are concatenated and written to the log file.

5. The log hierarchical synchronization system based on an ARM-MCU heterogeneous system according to claim 1, characterized in that, The ARM host communicates with the host computer via the TCP protocol; the host computer sends a log read command to the ARM host to retrieve the log.

6. The log hierarchical synchronization system based on an ARM-MCU heterogeneous system according to claim 5, characterized in that, The ARM host includes: The SCPI parsing module is used to parse the read log command and read the critical error log based on the read log command.

7. The log hierarchical synchronization system based on an ARM-MCU heterogeneous system according to claim 1, characterized in that, The UDP message includes: Synchronization header, type, target identifier, source identifier, current frame length, application layer data, and synchronization tail.

8. The log hierarchical synchronization system based on an ARM-MCU heterogeneous system according to claim 1, characterized in that, The MCU slave device is specifically used for: Collect sensor data and generate logs based on the sensor data; The MCU slave device is also used to send fault and abnormal configuration parameters during MCU slave device operation to the ARM host via log upload.

9. The log hierarchical synchronization system based on an ARM-MCU heterogeneous system according to claim 1, characterized in that, The ARM master unit uses a Cortex-A7 processor; the MCU slave unit uses an STM32F407.

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