Logarithmic pixel signal quantization method and module based on gain dynamic adjustment, image sensor

Abstract

The application discloses a logarithmic pixel signal quantization method and module based on gain dynamic adjustment and an image sensor. The logarithmic pixel signal quantization method comprises the following steps: converting photoelectric current logarithmic amplification into logarithmic voltage by using a logarithmic response unit; comparing the logarithmic voltage with a threshold voltage by using a voltage type comparator, outputting a gain configuration of a programmable gain amplifier and a gain control signal for input reference voltage switching, making the programmable gain amplifier work in different gain modes, and inputting a flag bit to an N-bit analog-to-digital converter; amplifying and shifting the logarithmic voltage to the output within the quantization range of the N-bit analog-to-digital converter by the programmable gain amplifier based on the current gain mode; and sampling the output voltage signal of the programmable gain amplifier by the N-bit analog-to-digital converter, combining the flag bit, and outputting an N+1-bit equivalent digital code value signal. The application simultaneously realizes high-sensitivity quantization of low-light-intensity signals and high-precision conversion of high-light-intensity signals.

Description

Technical Field

[0001] This invention relates to the field of CMOS image sensor technology, and in particular to a logarithmic pixel signal quantization method and module based on dynamic gain adjustment, and an image sensor. Background Technology

[0002] CMOS image sensors have consistently strived for wide dynamic range and high sensitivity under both strong and low light conditions. A steeper slope in the photoelectric conversion characteristic curve of a pixel (i.e., the light intensity-output signal relationship curve) can result in higher sensitivity but a narrower dynamic range. This is because a steeper slope indicates that a unit change in light intensity produces a larger change in signal output, but it also leads to faster saturation. Pixels with wide dynamic range require a gentler response slope, which in turn degrades sensitivity. Due to the linear light response of traditional pixels, there is a trade-off between dynamic range and sensitivity. To achieve wide dynamic range and high sensitivity, CMOS image sensors employ techniques such as multiple sampling and multiple exposures, but these techniques also introduce drawbacks: noise, increased power consumption, and larger sensor size.

[0003] In wide dynamic range (WDL) technology, logarithmic pixels exhibit nonlinear characteristics, resulting in a logarithmic output signal. The photocurrent is fed to transistors with logarithmic current-voltage characteristics, operating in the weak inversion region. Continuously operating transistors directly convert the photocurrent into a corresponding voltage without any integration process. This significantly extends the dynamic range with simple operation and low cost, typically exceeding 120 dB. The logarithmic response maintains near-linear sensitivity in low-light conditions and compresses high-light images, effectively preventing image lag in low-light environments and extending the dynamic range by preserving details in dark and overexposed areas. However, the pixel output swing is typically only a few hundred millivolts, resulting in low sensitivity. The limited voltage swing also reduces the signal-to-noise ratio, severely impacting image quality. Nevertheless, this method remains the most effective in terms of dynamic range.

[0004] For the quantization of pixel light intensity voltage output, single-slope analog-to-digital converters (SS-ADCs) have been widely used in column-parallel architecture CMOS image sensors. An SS-ADC consists of a ramp generator, comparator, and counter, generating a linear ramp signal for quantization using a constant-frequency counter. Therefore, a normal SS-ADC exhibits a linear response. To achieve wide dynamic range imaging, exponential ramp signals or logarithmic counter frequencies have been used, but these methods suffer from steep conversion rates and complex compensation circuits. Furthermore, traditional fixed-gain quantization schemes cannot simultaneously meet the quantization requirements of both the high-slope (easily saturated) and low-slope (insufficient resolution) regions of the logarithmic curve.

[0005] Therefore, how to achieve high linearity and low power consumption quantization of logarithmic voltage with a wide dynamic range and low power consumption while maintaining hardware efficiency with a limited number of ADC bits has become an urgent problem to be solved. Summary of the Invention

[0006] The purpose of this invention is to provide a logarithmic pixel signal quantization method and module, as well as an image sensor, based on dynamic gain adjustment to address the signal quantization problem in wide dynamic range imaging scenarios. Through an adaptive gain switching mechanism, it simultaneously achieves high-sensitivity quantization of low-intensity signals and high-precision conversion of high-intensity signals, effectively expanding the dynamic range of the imaging system.

[0007] In a first aspect, the present invention provides a logarithmic pixel signal quantization method based on dynamic gain adjustment, comprising:

[0008] Using a logarithmic response unit to convert photocurrent I ph Logarithmic amplification to logarithmic voltage V log Post-input voltage comparator and programmable gain amplifier;

[0009] The voltage comparator converts the logarithmic voltage V log With the preset threshold voltage V th A comparison is performed, and based on the comparison result, a gain control signal is output for the gain configuration and input reference voltage switching of the programmable gain amplifier, enabling the programmable gain amplifier to operate in different gain modes, and a flag bit is input to the N-bit analog-to-digital converter; the programmable gain amplifier, based on the current gain mode, adjusts the logarithmic voltage V... log Amplify and shift the output to the quantization range of the N-bit analog-to-digital converter;

[0010] The N-bit analog-to-digital converter samples the output voltage signal of the programmable gain amplifier and combines it with the flag bit to output an N+1-bit equivalent digital code value signal.

[0011] Where, if the logarithmic voltage V log <threshold voltage V th The programmable gain amplifier operates in the first gain mode; if the logarithmic voltage V log Threshold voltage V th The programmable gain amplifier operates in the second gain mode.

[0012] The first gain mode is a low gain mode, and the second gain mode is a high gain mode.

[0013] In the first gain mode, the programmable gain amplifier receives a first input reference voltage; in the second gain mode, the programmable gain amplifier receives a second input reference voltage.

[0014] The voltage comparator is connected to the programmable gain amplifier via a complementary switch controlled by complementary signals amp_low and amp_high, and inputs a gain control signal to the programmable gain amplifier.

[0015] The programmable gain amplifier includes a sampling capacitor C formed by a configurable array of n minimum unit capacitors C0. s The holding capacitance C is formed by a single smallest unit capacitor C0. h Sampling capacitor C s One end of the smallest unit capacitor C0 in the array is connected to the source of the first switch, the drain of switch sw2, and the drain of switch sw3. The other end is connected to one end of the other n-1 smallest unit capacitors C0 connected in parallel, and the holding capacitor C h One end of the capacitor is connected to the source of switch sw1 and the negative input terminal of OPA; the other end of the other n-1 parallel smallest unit capacitors C0 is connected to the drain of the first switch; the holding capacitor C h The other end is connected to the drain of switch sw1, the output of OPA, and the source of switch sw4. The drain of switch sw4 is grounded through a capacitor. The non-inverting input of OPA is connected to the reset voltage V. res The source of switch sw3 is connected to the logarithmic voltage V. log The source of switch sw2 is connected to the drain of the third switch and the second switch, and the sources of the third switch and the second switch are each connected to the first input reference voltage V. in_cm1 The second input reference voltage V in_cm2 The complementary switching signal output by the voltage comparator is connected to the gate of the third switch, and the signal amp_high is connected to the gates of the first and second switches.

[0016] The gain of the programmable gain amplifier is determined by the sampling capacitor C. s With holding capacitor C h The ratio determines G=C s / C h When the voltage comparator outputs 0, the first switch is turned off, causing a portion of the sampling capacitor Cs to be connected to form a low-gain G1 = C. s1 / C h At the same time, the third switch closes, selecting the first input reference voltage V. in_cm1 When the voltage comparator outputs 1, the first and second switches close, causing the sampling capacitor C to... s High gain G2 = C is achieved by connecting all capacitors in the middle. s2 / C h And switch to the second input reference voltage V in_cm2 .

[0017] The programmable gain amplifier operates alternately between reset mode and amplification mode;

[0018] In reset mode, switches sw1 and sw2 are closed, and sw3 is open, determining the gain and input reference voltage of the programmable gain amplifier; when switch sw1 is closed, the reset switch connected across the OPA is turned on, holding capacitor C. h Clear the programmable gain amplifier; the output voltage is equal to the reset voltage V. res When switch sw2 is closed, the first input reference voltage V... in_cm1 / Second input reference voltage V in_cm2 Connection circuit; in reset mode, the output is stable, switch SW4 is closed, and the programmable gain amplifier reset voltage V... res The output is sampled by an N-bit analog-to-digital converter;

[0019] In amplification mode, switch sw3 is closed, and sw1 and sw2 are open. The states of the switches controlled by the complementary signals amp_low and amp_high (low-gain switch and two high-gain switches, or the first, second, and third switches) remain unchanged. The logarithmic voltage is connected to the left plate of the sampling capacitor, keeping the voltage across the capacitor dynamically changing with the input signal. When the output of the amplification mode is stable, switch sw4 remains closed, and the PGA amplification voltage V... sig The output is sampled by the SS-ADC; in reset mode, the output reset voltage V is used. res Amplification mode output amplified voltage V sig ;

[0020] Calculate the output voltage of the programmable gain amplifier in amplification mode using the following formula:

[0021] .

[0022] A second aspect of the present invention provides a logarithmic pixel signal quantization module based on dynamic gain adjustment, comprising:

[0023] Logarithmic response unit, used to convert photocurrent I ph Logarithmic amplification to logarithmic voltage V log ;

[0024] A voltage comparator is used to convert the logarithmic voltage V... log With the preset threshold voltage V th The comparison is performed, and based on the comparison result, a gain control signal is output for the gain configuration and input reference voltage switching of the programmable gain amplifier, so that the programmable gain amplifier operates in different gain modes, and a flag bit is input to the N-bit analog-to-digital converter.

[0025] The programmable gain amplifier is used to adjust the logarithmic voltage V based on the current gain mode.log Amplify and shift the output to the quantization range of the N-bit analog-to-digital converter;

[0026] The N-bit analog-to-digital converter is used to sample the output voltage signal of the programmable gain amplifier in different gain modes, and combine it with the flag bit to output an N+1-bit equivalent digital code value signal.

[0027] In a third aspect, the present invention provides an image sensor including the aforementioned logarithmic pixel signal quantization module based on gain dynamic adjustment.

[0028] This invention divides the logarithmic voltage into intervals using a voltage comparator and dynamically adjusts the gain. It then uses a programmable gain amplifier (PGA) to dynamically amplify the logarithmic voltage, enabling logarithmic pixel signal quantization based on dynamic gain adjustment. Through an adaptive gain switching mechanism, it simultaneously achieves high-sensitivity quantization of low-intensity signals and high-precision conversion of high-intensity signals, effectively expanding the dynamic range of the imaging system. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the circuit module involved in the logarithmic pixel signal quantization method based on dynamic gain adjustment according to an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram illustrating a specific implementation of the voltage comparator preprocessing in an embodiment of the present invention.

[0031] Figure 3 This is a circuit diagram of a programmable gain amplifier according to an embodiment of the present invention.

[0032] Figure 4 This is a timing diagram of the programmable gain amplifier according to an embodiment of the present invention. Detailed Implementation

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0034] In an exemplary embodiment of this application, the proposed logarithmic pixel signal quantization method based on dynamic gain adjustment is based on Figure 1 The circuit module or structure shown is implemented using the following steps:

[0035] First, the photocurrent I is converted by the logarithmic response unit (logI / V). ph Logarithmic amplification to logarithmic voltage V log Then, it enters the interval discrimination stage, using a voltage comparator to determine the logarithmic voltage V. log With the preset threshold voltage V thComparisons are made to determine intervals, such as determining the logarithmic voltage V. log After determining whether it's the first or second interval, and completing the interval discrimination phase, the gain adjustment phase begins, with the input logarithmic voltage V... log Identified within a discrimination interval, the programmable gain amplifier (PGA) operates in either the first or second gain mode, depending on the output control of the voltage comparator. The PGA is set to a fixed gain amplifier, converting the logarithmic voltage V... log The voltage is amplified and shifted to the quantization range of the SS-ADC (N-bit digital-to-analog converter); finally, it enters the analog-to-digital conversion stage, where the SS-ADC samples the voltage output of the PGA, and the output of the voltage comparator is combined with the output of the N-bit ADC as a flag bit to output an N+1-bit digital code value.

[0036] Taking a two-segment gain as an example, if the logarithmic voltage V log <threshold voltage V th The PGA uses the first gain; if V log >V th The PGA uses a second gain; corresponding to different gains, the input reference voltage V of the PGA... in_cm It needs to be changed accordingly to accommodate different input ranges of V log Scaling to the same output range for AD quantization.

[0037] Figure 2 This is a schematic diagram illustrating a specific implementation of the voltage comparator preprocessing in an embodiment of this application. During the interval discrimination stage, the voltage comparator adjusts the PGA circuit structure through a pair of complementary switches controlled by complementary signals amp_low and amp_high. The voltage comparator has two inputs: the logarithmic voltage V0. log and the set threshold voltage V th Comparing the two, when V log <V th When the voltage comparator outputs 0, the PGA operates in the first gain mode, using low gain and the first input reference voltage V. in_cm1 To avoid ADC saturation caused by the high slope of the logarithmic curve in the low light intensity range; when V log >V th When the voltage comparator outputs 1, it switches to the second gain mode, using high gain and the second input reference voltage V. in_cm2 This design addresses the resolution deficiency issue in the high-intensity range caused by the low slope of the logarithmic curve. A dynamic gain-common-mode collaborative adjustment mechanism ensures that the amplified signal in each range accurately matches the ADC range. The first gain is designed to be low, significantly lower than the second gain, preserving the inherent sensitivity in the low-intensity range while improving the quantization accuracy in the high-intensity range.

[0038] Specifically, such as Figure 2 As shown in the figure, its curve is the logarithmic voltage (V) log The diagram illustrates the quantization response under different gain modes, with the horizontal axis representing the input light intensity (corresponding to the logarithmic voltage V). log The vertical axis represents the signal quantity (or final quantization effect) entering the ADC after amplification by the PGA. The gain switching point corresponds to the threshold voltage V. th The location is the boundary between the Low Gain Region and the High Gain Region, i.e., V. log =V th Place.

[0039] In the low-gain region, when V log <V th In low light intensity scenarios, the voltage comparator outputs 0, the switch controlled by the signal amp_low closes, and the PGA operates in low gain mode (first gain). The slope of the line in this region is small, which avoids ADC saturation caused by the high slope of the logarithmic curve under low light intensity and preserves the sensitivity of low light intensity signals.

[0040] In the high-gain region, when V log >V th In high-intensity scenes, the voltage comparator outputs 1, the switch controlled by the signal amp_high closes, and the PGA switches to high-gain mode (second gain). The lines in this region have a larger slope, which is used to improve the resolution problem caused by the low slope of the logarithmic curve under high light intensity.

[0041] Figure 3 A circuit diagram of a programmable gain amplifier according to an embodiment of this application is shown to further illustrate how the voltage comparator adjusts the gain via a switch controlled by complementary signals amp_low and amp_high. In the figure, V log Represents logarithmic voltage, V res Represents the reset voltage, V in_cm1 Indicates the first input reference voltage, V in_cm2 This represents the second input reference voltage. The gain is determined by the sampling capacitor C. s With holding capacitor C h The ratio determines (G=C) s / C h ), where the holding capacitor C h Fixed as the smallest unit C0, sampling capacitor C sDesigned as a configurable array. The complementary switching signals amp_low and amp_high from the voltage-type comparator output synchronously control the PGA gain configuration and input reference voltage switching: when the comparator output is 0 (low light intensity range), the first switch controlled by the signal amp_high is turned off, causing C... s Partial access results in low gain G1=C s1 / C h When the switch controlled by the signal amp_low is closed, the first input reference voltage V is selected. in_cm1 When the comparator outputs 1 (high light intensity range), the switch controlled by the signal amp_high closes, causing C... s Achieving high gain G2=C through full access s2 / C h And switch to the second input reference voltage V in_cm2 .

[0042] During the analog-to-digital conversion stage, the output of the voltage comparator is used as a flag bit to indicate whether the current logarithmic voltage is in the first or second interval. Although the code value range of the ADC output is the same in each interval, due to the combination of the flag bit, the N-bit ADC outputs N+1 bits of digital code value, which is equivalent to twice the quantization code value range.

[0043] Figure 4 A timing diagram of the PGA operation according to an embodiment of this application is shown.

[0044] The voltage comparator operates first, comparing the input logarithmic voltage V. log and threshold voltage V th After the comparison, the result is transmitted to the PGA, and the gain of the PGA and the input reference voltage V are dynamically adjusted by a switch controlled by complementary signals amp_low and amp_high. in_cm The PGA operates alternately between reset mode and amplification mode.

[0045] In reset mode, switches sw1 and sw2 are closed, and sw3 is open. During this period, the switches controlled by complementary signals amp_low and amp_high remain in a stable state, i.e., the PGA gain and the input reference voltage V. in_cm Confirmed; Switch sw1 is closed, the reset switch connected across the operational amplifier (OPA) is turned on, and capacitor C is held in place. h When the charge is cleared, the PGA output voltage equals the reset voltage V. res When switch sw2 is closed, V is determined by the preprocessing of the voltage comparator. in_cm1 or V in_cm2 The circuit is connected with the input reference voltage connected to the left plate of the sampling capacitor; in the reset mode, the output is stable, switch sw4 is closed, and the PGA reset voltage V... resThe output is sampled by the SS-ADC.

[0046] In amplification mode, switch sw3 is closed, and switches sw1 and sw2 are open. The switches controlled by the complementary signals amp_low and amp_high (the low-gain switch and two high-gain switches, or the first, second, and third switches) remain unchanged, i.e., maintaining the state unchanged from the reset mode. Because sw3 is closed and sw2 is open, the logarithmic voltage is connected to the left plate of the sampling capacitor; sw1 is open, keeping the voltage across the capacitor dynamically changing with the input signal. When the output in the amplification mode is stable, switch sw4 remains closed, and the PGA amplification voltage V... sig The output is sampled by the SS-ADC. The reset voltage V is output in reset mode. res Amplification mode output amplified voltage V sig Based on the charge conservation principle of switched capacitor circuits, the transfer function between the PGA output voltage and the logarithmic input voltage can be expressed as:

[0047] .

[0048] In the transfer function, V sig V represents the output voltage in PGA amplification mode. log C represents the logarithmic voltage of the input. s / C h This indicates adjustable gain, achieved in the circuit by changing the size of the sampling capacitor array through the output of a voltage comparator; V in_cm This indicates an adjustable input reference voltage; the circuit provides dual reference voltage sources V. in_cm1 and V in_cm2 , corresponding to the first gain and the second gain respectively. When the PGA selects the first gain, V in_cm1 Connect the circuit via sw2, or conversely, V. in_cm2 Connect to the circuit.

[0049] This application embodiment, through the aforementioned gain dynamic adjustment method, coordinates the expansion of the voltage comparator flag bit, combines the N-bit quantization result of the ADC with the output flag bit of the voltage comparator to generate an N+1-bit equivalent digital code value, thereby expanding the dynamic range of the ADC, breaking through the limitation of physical bit length, saving circuit complexity, effectively solving the problem of the incompatibility between resolution and range in wide dynamic range logarithmic pixel signal quantization, and eliminating the defects of nonlinear distortion and limited dynamic range of traditional ADC quantization logarithmic voltage.

[0050] This application proposes a logarithmic pixel signal quantization method based on dynamic gain adjustment to address the technical requirements of wide dynamic range imaging. The method employs a programmable gain amplifier to dynamically amplify the logarithmic voltage and combines it with comparator flag bit extension technology.

[0051] Compared with traditional logarithmic pixel signal quantization schemes, the embodiments of this application prevent ADC quantization saturation in low-light scenes and improve the resolution of ADC quantization in strong light scenes through dynamic gain adjustment, achieving fine quantization with a wide dynamic range. At the same time, the effective resolution of the N-bit ADC is extended to the equivalent N+1 bits through the flag bit output by the voltage comparator, which significantly improves the dynamic range of the system with almost no increase in hardware cost.

[0052] Furthermore, the different gain ranges in this application embodiment, combined with the corresponding input reference voltage adjustment, ensure that the PGA output always matches the quantization range of the ADC, effectively solving the problem that resolution and range cannot be simultaneously achieved in wide dynamic range logarithmic voltage quantization, while eliminating the nonlinear distortion and limited dynamic range defects of traditional ADC quantization logarithmic voltage.

[0053] This application further provides a logarithmic pixel signal quantization module based on dynamic gain adjustment, see [link to relevant documentation]. Figure 1 As shown, it includes:

[0054] Logarithmic response unit, used to convert photocurrent I ph Logarithmic amplification to logarithmic voltage V log ;

[0055] A voltage comparator is used to convert the logarithmic voltage V... log With the preset threshold voltage V th The comparison is performed, and based on the comparison result, a gain control signal is output for the gain configuration and input reference voltage switching of the programmable gain amplifier, so that the programmable gain amplifier operates in different gain modes, and a flag bit is input to the N-bit analog-to-digital converter.

[0056] The programmable gain amplifier is used to adjust the logarithmic voltage V based on the current gain mode. log Amplify and shift the output to the quantization range of the N-bit analog-to-digital converter;

[0057] The N-bit analog-to-digital converter is used to sample the output voltage signal of the programmable gain amplifier in different gain modes, and combine it with the flag bit to output an N+1-bit equivalent digital code value signal.

[0058] In this embodiment of the application, the photocurrent I is converted into a logarithmic response unit. ph Logarithmic amplification to logarithmic voltage V log Next, the interval discrimination stage begins, where a voltage comparator compares the logarithmic voltage with a preset threshold voltage V. th The input logarithmic voltage is compared and interval discrimination is performed to determine whether it belongs to the first interval or the second interval. After the interval discrimination stage is completed, the gain adjustment stage begins, where the input logarithmic voltage V... logOnce identified within a certain range, the programmable gain amplifier is set to a fixed gain amplifier based on the output control of the voltage comparator, amplifying the logarithmic voltage and shifting it into the quantization range of the SS-ADC. Finally, in the analog-to-digital conversion stage, the ADC samples the voltage output of the PGA, and the output of the voltage comparator is combined with the output of the N-bit ADC as a flag bit to output an N+1-bit digital code value.

[0059] Taking a two-segment gain as an example, if the logarithmic voltage V log <threshold voltage V th The PGA uses the first gain; if V log >V th The PGA uses a second gain, and the input reference voltage V of the PGA is... in_cm This also changes accordingly, to accommodate different input ranges of V. log Scaling to the same output range for AD quantization.

[0060] Figure 2 This is a schematic diagram illustrating a specific implementation of the voltage comparator preprocessing in an embodiment of this application. During the interval discrimination stage, the voltage comparator adjusts the PGA circuit structure using a switch controlled by a pair of complementary signals, amp_low and amp_high. The voltage comparator has two inputs: a logarithmic input voltage V0. log and the set threshold voltage V th Comparing the two, when V log <V th When the voltage comparator outputs 0, the PGA operates in the first gain mode, using low gain and the first input reference voltage V. in_cm1 To avoid ADC saturation caused by the high slope of the logarithmic curve in the low light intensity range; when V log >V th When the voltage comparator outputs 1, it switches to the second gain mode, using high gain and the second input reference voltage V. in_cm2 This addresses the resolution deficiency issue in the high-intensity range caused by the low slope of the logarithmic curve. A dynamic gain-common-mode coordinated adjustment mechanism ensures that the amplified signal in each range accurately matches the ADC range. The design, where the first gain is significantly lower than the second gain, preserves the inherent sensitivity in the low-intensity range while improving the quantization accuracy in the high-intensity range.

[0061] Figure 3 A circuit diagram of a programmable gain amplifier according to an embodiment of this application is shown to further illustrate how the voltage comparator adjusts the gain via a switch controlled by complementary signals amp_low and amp_high. Figure 3 In the middle, V log Represents logarithmic voltage, V res Represents the reset voltage, Vin_cm1 Indicates the first input reference voltage, V in_cm2 This represents the second input reference voltage. The gain is determined by the sampling capacitor C. s With holding capacitor C h The ratio determines (G=C) s / C h ), where the holding capacitor C h Fixed as the smallest unit C0, sampling capacitor C s Designed as a configurable array. The complementary switching signals amp_low and amp_high from the voltage-type comparator output synchronously control the PGA gain configuration and input reference voltage switching: when the comparator output is 0 (low light intensity range), the first switch controlled by the signal amp_high is turned off, causing C... s Partial access results in low gain G1=C s1 / C h The third switch controlled by the signal amp_low closes simultaneously, selecting the first input reference voltage V. in_cm1 When the comparator outputs 1 (high light intensity range), the first and second switches controlled by the signal amp_high close, causing C... s Achieving high gain G2=C through full access s2 / C h And switch to the second input reference voltage V in_cm2 .

[0062] During the analog-to-digital conversion stage, the output of the voltage comparator serves as a flag bit, indicating the current logarithmic voltage V. log Whether it's in the first or second interval, although the final range of the ADC output code value is the same for each interval, combined with the flag bit output by the voltage comparator, the N-bit ADC outputs an N+1-bit digital code value, which is equivalent to twice the range of quantization code value.

[0063] Figure 4 The following is a timing diagram of the PGA operation according to an embodiment of this application. The voltage comparator operates first, comparing the input logarithmic voltage V. log and threshold voltage V th After the comparison is complete, the result is transmitted to the PGA. The gain of the PGA and the input reference voltage V are dynamically adjusted by a switch controlled by complementary signals amp_low and amp_high. in_cm The PGA operates alternately between reset mode and amplification mode.

[0064] In reset mode, switches sw1 and sw2 are closed, and sw3 is open. The switches controlled by complementary signals amp_low and amp_high, which are controlled by the voltage comparator output, stabilize early during this period, i.e., the PGA gain and the input reference voltage V. in_cmConfirmed. Switch sw1 is closed, the reset switch connected across the operational amplifier is turned on, and capacitor C is held in place. h When the charge is cleared, the PGA output voltage equals the reset voltage V. res ;sw2 is closed, and V is determined by the preprocessing of the voltage comparator. in_cm1 or V in_cm2 Connect the circuit, with the input reference voltage connected to the left plate of the sampling capacitor. In reset mode, the output is stable, sw4 is closed, and the PGA reset voltage V... res The output is sampled by the SS-ADC.

[0065] In amplification mode, switch sw3 is closed, and sw1 and sw2 are open. The switches controlled by the complementary signals amp_low and amp_high remain unchanged. Because sw3 is closed and sw2 is open, the logarithmic voltage is connected to the left plate of the sampling capacitor; sw1 is open, maintaining the voltage across the capacitor dynamically changing with the input signal. In amplification mode, when the output is stable, switch sw4 remains closed, and the PGA amplified voltage V... sig The output is sampled by the SS-ADC. The reset voltage V is output in reset mode. res Amplification mode output amplified voltage V sig Based on the charge conservation principle of switched capacitor circuits, the transfer function between the PGA output voltage and the input logarithmic voltage can be expressed as:

[0066] .

[0067] In the transfer function, V sig V represents the output voltage in PGA amplification mode. log C represents the logarithmic voltage of the input. s / C h This indicates adjustable gain, which is achieved in the circuit by changing the size of the sampling capacitor array through the output of a voltage-type comparator; V in_cm This indicates an adjustable input reference voltage; the circuit provides dual reference voltage sources V. in_cm1 and V in_cm2 , corresponding to the first gain and the second gain respectively. When the PGA selects the first gain, V in_cm1 Connect the circuit via sw2, or conversely, V. in_cm2 Connect to the circuit.

[0068] This application embodiment, through the aforementioned gain dynamic adjustment method, coordinates the expansion of the voltage comparator flag bit, combines the N-bit quantization result of the ADC with the output flag bit of the voltage comparator to generate an N+1-bit equivalent digital code value, thereby expanding the dynamic range of the ADC, breaking through the limitation of physical bit length, saving circuit complexity, effectively solving the problem of the incompatibility between resolution and range in wide dynamic range logarithmic pixel signal quantization, and eliminating the defects of nonlinear distortion and limited dynamic range of traditional ADC quantization logarithmic voltage.

[0069] This application addresses the technical requirements of wide dynamic range imaging by proposing a logarithmic pixel signal quantization method based on dynamic gain adjustment. It employs a programmable gain amplifier to dynamically amplify the logarithmic voltage and combines this with a voltage comparator flag bit extension technique. Compared to traditional logarithmic pixel signal quantization schemes, this application's embodiment prevents ADC quantization saturation in low-light scenes and improves ADC quantization resolution in high-light scenes through dynamic gain adjustment, achieving fine quantization over a wide dynamic range. Simultaneously, by extending the effective resolution of the N-bit ADC to an equivalent N+1 bits through the flag bit output by the voltage comparator, it significantly improves the system's dynamic range with almost no increase in hardware cost.

[0070] Furthermore, different gain ranges, combined with corresponding input reference voltage adjustments, ensure that the PGA output always matches the quantization range of the ADC, effectively solving the problem of the incompatibility between resolution and range in wide dynamic range logarithmic voltage quantization, while eliminating the nonlinear distortion and limited dynamic range defects of traditional ADC quantization logarithmic voltage.

[0071] In summary, the embodiments of this application divide the logarithmic voltage into intervals using a voltage comparator, dynamically adjust the gain, and use a programmable gain amplifier (PGA) to dynamically amplify the logarithmic voltage. This enables logarithmic pixel signal quantization processing based on dynamic gain adjustment. Through an adaptive gain switching mechanism, it simultaneously achieves high-sensitivity quantization of low-intensity signals and high-precision conversion of high-intensity signals, effectively expanding the dynamic range of the imaging system.

[0072] This application further provides an image sensor, including the aforementioned logarithmic pixel signal quantization module based on dynamic gain adjustment. This image sensor divides the logarithmic voltage into intervals using a voltage comparator, dynamically adjusts the gain, and employs a programmable gain amplifier (PGA) to dynamically amplify the logarithmic voltage. This enables logarithmic pixel signal quantization processing based on dynamic gain adjustment. Through an adaptive gain switching mechanism, it simultaneously achieves high-sensitivity quantization of low-intensity signals and high-precision conversion of high-intensity signals, effectively expanding the dynamic range of the imaging system.

[0073] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, the embodiments should be regarded as exemplary and non-limiting in all respects. The scope of the present invention is defined by the appended claims rather than the foregoing description, and therefore all changes falling within the meaning and scope of the equivalents of the claims are intended to be included within the present invention.

[0074] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A logarithmic pixel signal quantization method based on dynamic gain adjustment, characterized in that, The process includes the following steps: using a logarithmic response unit to convert the photocurrent I... ph Logarithmic amplification to logarithmic voltage V log The input voltage comparator and programmable gain amplifier are then used; the voltage comparator converts the logarithmic voltage V... log With the preset threshold voltage V th A comparison is performed, and based on the comparison result, a gain control signal is output for the gain configuration and input reference voltage switching of the programmable gain amplifier, enabling the programmable gain amplifier to operate in different gain modes, and a flag bit is input to the N-bit analog-to-digital converter; the programmable gain amplifier, based on the current gain mode, adjusts the logarithmic voltage V... log The signal is amplified and shifted to the quantization range of the SS-ADC for output; the N-bit analog-to-digital converter samples the output voltage signal of the programmable gain amplifier, combines it with the flag bit, and outputs an N+1-bit equivalent digital code value signal. The programmable gain amplifier includes a sampling capacitor C formed by a configurable array of n minimum unit capacitors C0. s The holding capacitance C is formed by a single smallest unit capacitor C0. h Sampling capacitor C s One end of the smallest unit capacitor C0 in the array is connected to the source of the first switch, the drain of switch sw2, and the drain of switch sw3. The other end is connected to one end of the other n-1 smallest unit capacitors C0 connected in parallel, and the holding capacitor C h One end of the capacitor is connected to the source of switch sw1 and the negative input terminal of OPA; the other end of the other n-1 parallel smallest unit capacitors C0 is connected to the drain of the first switch; the holding capacitor C h The other end is connected to the drain of switch sw1, the output of OPA, and the source of switch sw4. The drain of switch sw4 is grounded through a capacitor. The non-inverting input of OPA is connected to the reset voltage V. res The source of switch sw3 is connected to the logarithmic voltage V. log The source of switch sw2 is connected to the drain of the third switch and the second switch, and the sources of the third switch and the second switch are each connected to the first input reference voltage V. in_cm1 Second input reference voltage V in_cm2 The complementary switching signal output by the voltage comparator, amp_low, is connected to the gate of the third switch, and amp_high is connected to the gates of the first and second switches.

2. The logarithmic pixel signal quantization method based on dynamic gain adjustment according to claim 1, characterized in that, If the logarithmic voltage V log <threshold voltage V th The programmable gain amplifier operates in the first gain mode; if the logarithmic voltage V log Threshold voltage V th The programmable gain amplifier operates in the second gain mode.

3. The logarithmic pixel signal quantization method based on dynamic gain adjustment according to claim 2, characterized in that, The first gain mode is a low gain mode, and the second gain mode is a high gain mode.

4. The logarithmic pixel signal quantization method based on dynamic gain adjustment according to claim 3, characterized in that, In the first gain mode, the programmable gain amplifier receives a first input reference voltage; In the second gain mode, the programmable gain amplifier receives a second input reference voltage.

5. The logarithmic pixel signal quantization method based on dynamic gain adjustment according to claim 1, characterized in that, The voltage comparator is connected to the programmable gain amplifier via a complementary switch controlled by complementary signals amp_low and amp_high, and inputs a gain control signal to the programmable gain amplifier.

6. The logarithmic pixel signal quantization method based on dynamic gain adjustment according to claim 5, characterized in that, The gain of the programmable gain amplifier is determined by the sampling capacitor C. s With holding capacitor C h The ratio determines G=C s / C h When the voltage comparator outputs 0, the first switch is turned off, causing the sampling capacitor C to... s Part of the capacitor is connected to form a low-gain G1=C s1 / C h At the same time, the third switch closes to select the first input reference voltage V. in_cm1 When the voltage comparator outputs 1, the first and second switches close, causing the sampling capacitor C to... s High gain G2 = C is achieved by connecting all capacitors in the middle. s2 / C h And switch to the second input reference voltage V in_cm2 .

7. The logarithmic pixel signal quantization method based on dynamic gain adjustment according to claim 6, characterized in that, The programmable gain amplifier operates alternately between reset mode and amplification mode. In reset mode, switches sw1 and sw2 are closed, and sw3 is open, determining the gain and input reference voltage of the programmable gain amplifier. When switch sw1 is closed, the reset switch connected across the OPA is turned on, maintaining capacitor C. h Clear the programmable gain amplifier; the output voltage is equal to the reset voltage V. res Switch sw2 is closed, and the first input reference voltage V in_cm1 / Second input reference voltage V in_cm2 Connection circuit; in reset mode, the output is stable, switch SW4 is closed, and the programmable gain amplifier reset voltage V... res The output is sampled by an N-bit analog-to-digital converter. In amplification mode, switch sw3 is closed, and sw1 and sw2 are open. The states of the switches controlled by the complementary signals amp_low and amp_high remain unchanged. The logarithmic voltage is connected to the left plate of the sampling capacitor, keeping the voltage across the capacitor dynamically changing with the input signal. When the output is stable in amplification mode, switch sw4 remains closed, and the PGA amplification voltage V... sig The output is sampled by the SS-ADC; in reset mode, the output reset voltage V is used. res Amplification mode output amplified voltage V sig Calculate the output voltage of the programmable gain amplifier in amplification mode according to the following formula; 。 8. A logarithmic pixel signal quantization module based on dynamic gain adjustment, characterized in that, include: Logarithmic response unit, used to convert photocurrent I ph Logarithmic amplification to logarithmic voltage V log A voltage comparator is used to convert the logarithmic voltage V... log With the preset threshold voltage V th A comparison is made, and based on the comparison result, a gain control signal is output for the gain configuration and input reference voltage switching of the programmable gain amplifier, enabling the programmable gain amplifier to operate in different gain modes, and a flag bit is input to the N-bit analog-to-digital converter; the programmable gain amplifier is used to adjust the logarithmic voltage V based on the current gain mode. log The signal is amplified and shifted to the SS-ADC quantization range for output; the N-bit analog-to-digital converter is used to sample the output voltage signal of the programmable gain amplifier in different gain modes, and combine it with the flag bit to output an N+1-bit equivalent digital code value signal; the programmable gain amplifier includes a sampling capacitor C formed by a configurable array of n minimum unit capacitors C0. s The holding capacitance C is formed by a single smallest unit capacitor C0. h Sampling capacitor C s One end of the smallest unit capacitor C0 in the array is connected to the source of the first switch, the drain of switch sw2, and the drain of switch sw3. The other end is connected to one end of the other n-1 smallest unit capacitors C0 connected in parallel, and the holding capacitor C h One end of the capacitor is connected to the source of switch sw1 and the negative input terminal of OPA; the other end of the other n-1 parallel smallest unit capacitors C0 is connected to the drain of the first switch; the holding capacitor C h The other end is connected to the drain of switch sw1, the output of OPA, and the source of switch sw4. The drain of switch sw4 is grounded through a capacitor. The non-inverting input of OPA is connected to the reset voltage V. res The source of switch sw3 is connected to the logarithmic voltage V. log The source of switch sw2 is connected to the drain of the third switch and the second switch, and the sources of the third switch and the second switch are each connected to the first input reference voltage V. in_cm1 Second input reference voltage V in_cm2 The complementary switching signal output by the voltage comparator, amp_low, is connected to the gate of the third switch, and amp_high is connected to the gates of the first and second switches.

9. An image sensor, characterized in that, It includes the logarithmic pixel signal quantization module based on dynamic gain adjustment as described in claim 8.

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