Semiconductor device and method of manufacturing semiconductor device

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface arranged oppositely, the semiconductor substrate being provided with a channel region extending into the semiconductor substrate from the first surface, a source region and a drain region, the source region and the drain region being arranged on two sides of the channel region respectively; a source electrode arranged above the source region; a drain electrode arranged above the drain region; and a gate electrode arranged above the channel region, the gate electrode comprising a first part and a second part, the first part being close to the source electrode, the second part being close to the drain electrode, the first part being made of a first material, the second part being made of a second material, the work function of the first material being greater than that of the second material. According to the application, the leakage current can be reduced, and the short channel effect can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] Semiconductor devices employing two materials for their gates exist in the art. Devices using dual-material gates can achieve more precise electric field control in the channel region through two independent or co-operating gates. However, existing dual-material gates cannot effectively address the issues of high leakage current and short-channel effects. Therefore, there is an urgent need in the art for a semiconductor device employing a dual-material gate structure that can improve the transconductance of the device, reduce drain-induced barrier reduction (DIBL), decrease drain conductance, reduce leakage current, and suppress short-channel and hot carrier effects. Summary of the Invention

[0003] Therefore, this application aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can reduce leakage current and reduce short-channel effect.

[0004] In one aspect, this application provides a semiconductor device, comprising: a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, the semiconductor substrate having a channel region, a source region and a drain region extending from the first surface into the semiconductor substrate, the source region and the drain region being disposed on both sides of the channel region; a source electrode disposed above the source region; a drain electrode disposed above the drain region; and a gate electrode disposed above the channel region, the gate electrode including a first portion and a second portion, the first portion being close to the source electrode and the second portion being close to the drain electrode, the first portion being made of a first material and the second portion being made of a second material, the work function of the first material being greater than the work function of the second material.

[0005] In one possible implementation of this application, the first material includes polycrystalline silicon and the second material includes metal.

[0006] In one possible implementation of this application, the first surface is in the form of a stepped structure, and the channel region covers the height variation portion of the first surface.

[0007] In one possible implementation of this application, the first surface includes a first planar portion, a vertical portion, and a second planar portion. The vertical portion connects the first planar portion and the second planar portion at its upper and lower ends, respectively. The drain area is disposed in the first planar portion, the source area is disposed in the second planar portion, and the channel area is configured to cover the vertical portion, the first adjacent portion of the first planar portion adjacent to the vertical portion, and the second adjacent portion of the second planar portion adjacent to the vertical portion.

[0008] In one possible implementation of this application, the first part is configured to cover the vertical part from the side and the second adjacent part from above, and the second part is configured to cover the first adjacent part and the first part from above.

[0009] In one possible implementation of this application, the first surface is in the form of a stepped structure and includes a first planar portion, a vertical portion, and a second planar portion. The vertical portion connects the first planar portion and the second planar portion at its upper and lower ends, respectively. The channel area covers the vertical portion, the first adjacent portion of the first planar portion adjacent to the vertical portion, and the second adjacent portion of the second planar portion adjacent to the vertical portion. The first portion is configured to cover the vertical portion from the side and the second adjacent portion from above. The second portion is configured to cover the first adjacent portion and the first portion from above. The first portion has a first protective layer on the side of the horizontal portion away from the vertical portion, and the second portion has a second protective layer and a third protective layer on both sides of the horizontal portion, respectively.

[0010] In one possible implementation of this application, the first protective layer includes an oxide layer and a silicon nitride layer, the second protective layer includes an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer, and the third protective layer includes an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer.

[0011] In one possible implementation of this application, an isolation layer is provided between the gate and the first surface.

[0012] In one possible implementation of this application, the isolation layer includes a titanium nitride layer, a hafnium dioxide layer, and a silicon oxide layer.

[0013] In one possible implementation of this application, the semiconductor substrate further includes a lightly doped source region and a lightly doped drain region, with the lightly doped source region disposed outside the source region and the lightly doped drain region disposed outside the drain region.

[0014] In one possible implementation of this application, a well layer is disposed below the channel region, the lightly doped source region, and the lightly doped drain region on the semiconductor substrate.

[0015] In one possible implementation of this application, a deep well layer is disposed below the well layer on the semiconductor substrate.

[0016] On the other hand, this application provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other; forming a channel region, a source region and a drain region extending from the first surface into the semiconductor substrate in the semiconductor substrate, the source region and the drain region being disposed on both sides of the channel region; forming a source electrode above the source region; forming a drain electrode above the drain region; forming a gate electrode above the channel region, the gate electrode including a first portion and a second portion, the first portion being close to the source electrode and the second portion being close to the drain electrode, the first portion being made of a first material and the second portion being made of a second material, the work function of the first material being greater than the work function of the second material.

[0017] Compared with existing technologies, the unexpected technical effect of this application is the reduction of leakage current and suppression of short-channel effects. In this application, the gate is composed of a first part and a second part, which are made of different materials, forming a dual-material gate. In this dual-material gate semiconductor device, the work function of the first material near the source is greater than that of the second material near the drain, which creates a steeper potential gradient near the drain. This electric field distribution optimizes the control of channel carriers, especially when the device is turned off, and can more effectively suppress carrier injection near the drain, thereby reducing leakage current. In addition, this dual-material gate enhances the electric field confinement of the drain region through the lower work function on the drain side, effectively suppressing short-channel effects (such as drain-induced barrier reduction (DIBL)), thereby reducing leakage current. Attached Figure Description

[0018] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein: Figure 1 This invention illustrates one of the structural schematic diagrams of a semiconductor device according to an embodiment of the present application; Figure 2 A second schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown; Figure 3 A third schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown; Figure 4 Fourth schematic diagram of the structure of a semiconductor device according to an embodiment of this application; Figure 5 Fifth schematic diagram of the structure of a semiconductor device according to an embodiment of this application; Figure 6 Sixth schematic diagram of the structure of a semiconductor device according to an embodiment of this application; Figure 7A schematic flowchart of a semiconductor device manufacturing method according to an embodiment of this application is shown; Figure 8 This diagram illustrates the steps of a semiconductor device manufacturing method according to an embodiment of the present application. Figure 9 Showing according to Figure 8 One of the schematic diagrams illustrating the steps of the semiconductor device manufacturing method in the embodiment; Figure 10 Showing according to Figure 8 A second schematic diagram illustrating the steps of the semiconductor device manufacturing method in the embodiment; Figure 11 Showing according to Figure 8 The third schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment; Figure 12 Showing according to Figure 8 Fourth schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment; Figure 13 Showing according to Figure 8 Fifth schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment; Figure 14 Showing according to Figure 8 Sixth schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment; Figure 15 Showing according to Figure 8 Seventh schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment; Figure 16 Showing according to Figure 8 Eighth schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment; Figure 17 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (nine); Figure 18 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment; Figure 19 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (illustration eleven); Figure 20 Showing according to Figure 8 12. Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment; Figure 21 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (13th example); Figure 22 Showing according to Figure 8 Fourteenth schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment; Figure 23 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (15th example); Figure 24 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (Sixteenth example); Figure 25 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (Seventeenth example); Figure 26 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (18th example); Figure 27 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (19th example); Figure 28 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (20th example); Figure 29 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (21); Figure 30 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (22nd example); Figure 31 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (23rd in the series); Figure 32 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (24th example); Figure 33 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (25th example); Figure 34 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment (26th example); Figure 35 Showing according to Figure 8 Schematic diagram of the steps of the semiconductor device manufacturing method in the embodiment, number twenty-seven. Detailed Implementation

[0019] To enable those skilled in the art to more clearly understand the concepts and ideas of this application, the application is described in detail below with reference to specific embodiments. It should be understood that the embodiments given herein are only a part of all possible embodiments of this application. After reading the specification of this application, those skilled in the art are capable of making improvements, modifications, or substitutions to parts or the entirety of the following embodiments, and such improvements, modifications, or substitutions are also included within the scope of protection claimed in this application.

[0020] In this document, the terms "one," "an," and other similar words are not intended to indicate that only one of the described things exists, but rather that the description refers only to one of the described things, which may have one or more. In this document, the terms "comprising," "including," and other similar words are intended to indicate a logical relationship, not a spatial relationship. For example, "A includes B" means that logically B belongs to A, not that spatially B is located inside A. Furthermore, the meanings of the terms "comprising," "including," and other similar words should be considered open-ended, not closed-ended. For example, "A includes B" means that B belongs to A, but B does not necessarily constitute all of A; A may also include other elements such as C, D, and E.

[0021] In this document, the terms "first," "second," and other similar terms are not intended to imply any order, quantity, or importance, but are merely used to distinguish different elements. In this document, the terms "embodiment," "this embodiment," "an embodiment," or "an example" do not indicate that the description applies only to one specific embodiment, but rather that such description may also be applicable to one or more other embodiments. Those skilled in the art will understand that any description made herein with respect to one embodiment can be substituted, combined, or otherwise combined with the descriptions in one or more other embodiments, and the new embodiments resulting from such substitutions, combinations, or other combinations are readily conceived by those skilled in the art and fall within the scope of protection of this application.

[0022] In the embodiments of this application, semiconductor devices can refer to electronic devices made based on semiconductor materials (such as silicon, germanium, gallium arsenide, etc.). Their core function is to precisely control the current by controlling the conductivity of the material, thereby completing tasks such as signal processing, energy conversion, and data storage. These devices are typically composed of basic structures such as PN junctions, transistors, diodes, and field-effect transistors, and are constructed on semiconductor substrates through processes such as photolithography, doping, and thin film deposition. Their unique electrical characteristics stem from the fact that the conductivity of semiconductor materials is between that of conductors and insulators. The concentration and movement of charge carriers (electrons and holes) can be changed by applying voltage, illumination, or doping to achieve functions such as switching, amplification, and rectification of circuits.

[0023] Since the advent of Moore's Law, the number of transistors has doubled every year. As time has progressed, process nodes have reached 2nm or even 0.3nm, all with the aim of increasing the number of transistors and improving chip operating speed. When the number of transistors reaches a certain level, it is impossible to increase the number of transistors without structural changes. However, structural changes make the process very complex, such as FinFET (Fin Field-Effect Transistor) and GAA (Gate-All-Around).

[0024] In some embodiments of this application, a novel MOS (Metal Oxide Semiconductor) structure and a novel process method are proposed, which can improve short-channel effects, increase silicon wafer utilization, improve device performance, reduce DIBL (Drain Induced Barrier Lowering), reduce parasitic capacitance and leakage current, improve current distribution, prevent edge effects, and promote miniaturization.

[0025] In some embodiments of this application, the novel device structure can improve carrier transport efficiency and transconductance, reduce drain-induced barrier reduction and drain conductance, and also suppress short-channel effect and hot carrier effect.

[0026] In some embodiments of this application, the new device structure can realize a three-terminal separation structure of source, drain, and gate, which can improve the utilization of silicon wafers, reduce lateral parasitic capacitance, improve current distribution, prevent edge effects, and promote miniaturization.

[0027] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown.

[0028] According to this embodiment, the semiconductor device 100 includes: a semiconductor substrate 110, which includes a first surface 111 and a second surface 112 disposed opposite to each other. The semiconductor substrate 110 is provided with a channel region 113, a source region 114, and a drain region 115 extending from the first surface 111 into the semiconductor substrate 110. The source region 114 and the drain region 115 are respectively disposed on both sides of the channel region 113; a source electrode 120, which is disposed above the source region 114; a drain electrode 130, which is disposed above the drain region 115; and a gate electrode 140, which is disposed above the channel region 113. The gate electrode 140 includes a first portion 141 and a second portion 142. The first portion 141 is close to the source electrode 120, and the second portion 142 is close to the drain electrode 130. The first portion 141 is made of a first material, and the second portion 142 is made of a second material. The work function of the first material is greater than that of the second material.

[0029] In this embodiment, the gate is composed of a first part and a second part, which are made of different materials, forming a dual-material gate. In this dual-material gate semiconductor device, the work function of the first material near the source is greater than that of the second material near the drain, resulting in a steeper potential gradient near the drain. This electric field distribution optimizes the control of channel carriers, especially during device turn-off, and can more effectively suppress carrier injection near the drain, thereby reducing leakage current. In addition, this dual-material gate enhances the electric field confinement of the drain region through the lower work function on the drain side, effectively suppressing short-channel effects (such as drain-induced barrier reduction (DIBL)) and further reducing leakage current.

[0030] In this embodiment, the work function refers to the minimum energy required for an electron to escape from the surface of a material into a vacuum, typically measured in electron volts (eV). It reflects the ease with which an electron can escape the atomic nucleus from within the material; a smaller work function means an easier escape. In semiconductor technology, the work function is a key parameter for designing devices such as transistors. For example, the work function of the gate material directly affects the threshold voltage of a field-effect transistor, determining the device's on / off state. By selecting materials with different work functions (such as metals or semiconductors), the electrical performance of the device can be tuned. High work function materials are often used in enhancement-mode devices to increase the threshold voltage, while low work function materials are used in depletion-mode devices or to optimize current conduction. Furthermore, differences in work function can precisely adjust the interface potential in heterojunction or dual-material gate structures, improving electrostatic control, suppressing leakage current, and thus enhancing the device's energy efficiency and reliability.

[0031] As an example, the first material includes polycrystalline silicon, and the second material includes metal.

[0032] In this example, the inventors of this application discovered through extensive research and practice that using polycrystalline silicon as the first material and a metal as the second material effectively satisfies the requirement that the work function of the first material is greater than that of the second material, thereby better achieving the technical effects of reducing leakage current and suppressing short-channel effects. By employing these two materials, the function of the dual-material gate can be better realized.

[0033] Figure 2 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown.

[0034] According to this embodiment, the semiconductor device 200 includes: a semiconductor substrate 210, which includes a first surface 211 and a second surface 212 disposed opposite to each other. The semiconductor substrate 210 is provided with a channel region 213, a source region 214, and a drain region 215 extending from the first surface 211 into the semiconductor substrate 210, with the source region 214 and the drain region 215 respectively disposed on both sides of the channel region 213; a source electrode 220 disposed above the source region 214; a drain electrode 230 disposed above the drain region 215; and a gate electrode 240 disposed above the channel region 213, which includes a first portion 241 and a second portion 242, with the first portion 241 close to the source electrode 220 and the second portion 242 close to the drain electrode 230. According to this embodiment, the first surface 211 is in the shape of a stepped ladder, and the channel region 213 covers the height variation portion of the first surface 211.

[0035] In this embodiment, by setting the first surface in a stepped shape, the shape of the channel region can be changed, so that the channel region extends not only in the horizontal direction but also in the vertical direction. This shape of the channel region lengthens the channel region in the same horizontal area, thereby suppressing the short channel effect and improving the utilization rate of the silicon wafer.

[0036] According to this embodiment, the first surface 211 includes a first planar portion 216, a vertical portion 217, and a second planar portion 218. The vertical portion 217 is connected to the first planar portion 216 and the second planar portion 218 at its upper and lower ends, respectively. The drain area 215 is disposed in the first planar portion 216, the source area 214 is disposed in the second planar portion 218, and the channel area 213 is configured to cover the vertical portion 217, the first adjacent portion of the first planar portion 216 adjacent to the vertical portion 217, and the second adjacent portion of the second planar portion 218 adjacent to the vertical portion 217.

[0037] In this embodiment, by covering two planar portions and one vertical portion, the channel region forms a Z-shaped structure. This allows for a longer channel length within the same horizontal area, thus suppressing the short-channel effect. Furthermore, since a longer channel region can be generated within the same area, the silicon wafer area occupied by semiconductor devices with the same channel length can be reduced, thereby improving silicon wafer utilization.

[0038] Figure 3 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown.

[0039] According to this embodiment, the semiconductor device 300 includes: a semiconductor substrate 310, which includes a first surface 311 and a second surface 312 disposed opposite to each other. The semiconductor substrate 310 is provided with a channel region 313, a source region 314 and a drain region 315 extending from the first surface 311 into the semiconductor substrate 310. The source region 314 and the drain region 315 are respectively disposed on both sides of the channel region 313; a source electrode 320, which is disposed above the source region 314; a drain electrode 330, which is disposed above the drain region 315; and a gate electrode 340, which is disposed above the channel region 313. The gate electrode 340 includes a first portion 341 and a second portion 342, where the first portion 341 is close to the source electrode 320 and the second portion 342 is close to the drain electrode 330. The first surface 311 includes a first planar portion 316, a vertical portion 317, and a second planar portion 318. The vertical portion 317 connects to the first planar portion 316 and the second planar portion 318 at its upper and lower ends, respectively. A drain area 315 is disposed in the first planar portion 316, and a source area 314 is disposed in the second planar portion 318. A channel area 313 is configured to cover the vertical portion 317, the first adjacent portion of the first planar portion 316 adjacent to the vertical portion 317, and the second adjacent portion of the second planar portion 318 adjacent to the vertical portion 317. According to this embodiment, the first portion 341 is configured to cover the vertical portion 317 from the side and the second adjacent portion from above, and the second portion 342 is configured to cover the first adjacent portion and the first portion 341 from above.

[0040] In this embodiment, the first part of the dual-material gate covers the second adjacent part in the lower layer, and the second part covers the entire channel region in the upper layer. The second part in the upper layer and the first part in the lower layer can optimize the potential distribution at different positions in the channel, thereby controlling the movement of charge carriers more precisely. This design significantly enhances the electrostatic confinement of the channel and improves the switching efficiency and stability of the device.

[0041] Figure 4 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown.

[0042] According to this embodiment, the semiconductor device 400 includes: a semiconductor substrate 410, which includes a first surface 411 and a second surface 412 disposed opposite to each other. The semiconductor substrate 410 is provided with a channel region 413, a source region 414 and a drain region 415 extending from the first surface 411 into the semiconductor substrate 410. The source region 414 and the drain region 415 are respectively disposed on both sides of the channel region 413; a source electrode 420, which is disposed above the source region 414; a drain electrode 430, which is disposed above the drain region 415; and a gate electrode 440, which is disposed above the channel region 413. The gate electrode 440 includes a first portion 441 and a second portion 442, where the first portion 441 is close to the source electrode 420 and the second portion 442 is close to the drain electrode 430. According to this embodiment, the first surface 411 is in the shape of a stepped first plane and includes a first planar portion 416, a vertical portion 417, and a second planar portion 418. The vertical portion 417 is connected to the first planar portion 416 and the second planar portion 418 at its upper and lower ends, respectively. The channel area 413 is configured to cover the vertical portion 417, the first adjacent portion of the first planar portion 416 adjacent to the vertical portion 417, and the second adjacent portion of the second planar portion 418 adjacent to the vertical portion 417. The first portion 441 is configured to cover the vertical portion 417 from the side and the second adjacent portion from above. The second portion 442 is configured to cover the first adjacent portion and the first portion 441 from above. The first portion 441 has a first protective layer 443 on the side away from the vertical portion 417 in the horizontal direction. The second portion 442 has a second protective layer 444 and a third protective layer 445 on both sides in the horizontal direction, respectively.

[0043] In this embodiment, by setting the first, second, and third protective layers, the electric field concentration at the slot corner can be effectively mitigated. High electric fields can easily lead to gate breakdown, while the protective layers reduce the damage to the gate by adjusting the electric field distribution, thereby improving the device's withstand voltage and long-term reliability. The protective layers can also serve as a physical support structure, maintaining the geometry of the gate and its surrounding structure in complex processes and preventing structural deformation or collapse.

[0044] As an example, the first protective layer includes an oxide layer and a silicon nitride layer, the second protective layer includes an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer, and the third protective layer includes an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer.

[0045] In this example, the inventors of this application discovered through extensive research and practice that a protective layer made of the aforementioned material can effectively protect the gate, improve the device's withstand voltage characteristics, and protect the gate's physical structure. The protective layer made of the aforementioned material has proven to particularly effectively utilize its technical functions, allowing it to maximize its application value.

[0046] Figure 5A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown.

[0047] According to this embodiment, the semiconductor device 500 includes: a semiconductor substrate 510, which includes a first surface 511 and a second surface 512 disposed opposite to each other. The semiconductor substrate 510 is provided with a channel region 513, a source region 514, and a drain region 515 extending from the first surface 511 into the semiconductor substrate 510, with the source region 514 and the drain region 515 respectively disposed on both sides of the channel region 513; a source electrode 520 disposed above the source region 514; a drain electrode 530 disposed above the drain region 515; and a gate electrode 540 disposed above the channel region 513, which includes a first portion 541 and a second portion 542, with the first portion 541 close to the source electrode 520 and the second portion 542 close to the drain electrode 530. According to this embodiment, an isolation layer 550 is disposed between the gate electrode 540 and the first surface 511.

[0048] In this embodiment, the function of the isolation layer is to isolate the gate and the channel region, preventing direct contact between them and thus avoiding a short circuit. As the medium for the gate electric field, the dielectric constant and thickness of the isolation layer directly affect the strength and distribution of the electric field. By applying a gate voltage, the isolation layer transfers the electric field to the channel region, inducing or depleting the charge carriers in the channel, thereby controlling the device's conduction or cutoff. The isolation layer can also prevent impurities (such as metal ions) in the gate material from diffusing into the channel region, avoiding disruption of the channel doping concentration, thereby ensuring the stability of the device's threshold voltage and conductivity.

[0049] As an example, the isolation layer 550 includes a titanium nitride layer, a hafnium dioxide layer, and a silicon oxide layer.

[0050] In this example, the inventors of this application discovered through extensive research and experimentation that the isolation layer, which includes a titanium nitride layer, a hafnium dioxide layer, and a silicon oxide layer, is particularly suitable for playing the role of an isolation layer, and can effectively isolate the gate and channel regions, so that the technical advantages of the isolation layer can be ideally brought into play.

[0051] Figure 6 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown.

[0052] According to this embodiment, the semiconductor device 600 includes: a semiconductor substrate 610, which includes a first surface 611 and a second surface 612 disposed opposite to each other. The semiconductor substrate 610 is provided with a channel region 613, a source region 614 and a drain region 615 extending from the first surface 611 into the semiconductor substrate 610. The source region 614 and the drain region 615 are respectively disposed on both sides of the channel region 613; a source electrode 620, which is disposed above the source region 614; a drain electrode 630, which is disposed above the drain region 615; and a gate electrode 640, which is disposed above the channel region 613. The gate electrode 640 includes a first portion 641 and a second portion 642, where the first portion 641 is close to the source electrode 620 and the second portion 642 is close to the drain electrode 630. According to this embodiment, the semiconductor substrate 610 further includes a lightly doped source region 680 and a lightly doped drain region 650. The lightly doped source region 680 is disposed outside the source region 614, and the lightly doped drain region 650 is disposed outside the drain region 615.

[0053] In this embodiment, by inserting a lightly doped region between the source and drain and the channel, the electric field can be dispersed, reducing the peak electric field near the source and drain. This reduces carrier acceleration, thereby suppressing the generation of hot carriers and significantly improving device reliability and lifetime. The lightly doped region can adjust the electric field distribution between the source and drain and the channel, making the electric field smoother, thereby mitigating short-channel effects. For example, by reducing the influence of the source and drain on the channel barrier, it helps maintain a stable threshold voltage and improves the performance consistency of the device in small sizes.

[0054] According to this embodiment, a well layer 660 is disposed below the channel region 613, the source lightly doped region 680, and the drain lightly doped region 650 in the semiconductor substrate 610.

[0055] In this embodiment, the well layer is a heavily doped region formed on the substrate through doping. Its core function is to provide an independent capacitor for the MOS transistor, enabling electrical isolation between the PMOS and NMOS transistors. This structure allows NMOS and PMOS transistors to coexist on the same chip, avoiding mutual interference and thus enabling the integration of complementary logic circuits. Furthermore, by adjusting the bias voltage of the well layer, the threshold voltage of the MOS transistor can be adjusted, thereby optimizing the power consumption and speed of the circuit.

[0056] According to this embodiment, a deep well layer 670 is disposed below the well layer 660 in the semiconductor substrate 610.

[0057] In this embodiment, the deep well layer is a doped region further deepened below the well layer, and its main function is to provide a higher degree of isolation for noise-sensitive devices. The deep well layer can accommodate devices at different potentials, supporting the multi-voltage domain design of complex circuits. In high-density integration or scenarios with high noise requirements, the deep well layer reduces the impact of substrate noise on critical circuits through physical and electrical isolation, ensuring circuit stability and reliability.

[0058] Figure 7 A schematic flowchart of a semiconductor device manufacturing method according to an embodiment of this application is shown.

[0059] According to this embodiment, the method for manufacturing a semiconductor device includes: S710, A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other; S720: A channel region, a source region, and a drain region are formed in a semiconductor substrate, extending from a first surface into the semiconductor substrate, with the source region and drain region respectively disposed on both sides of the channel region; S730, a source electrode is formed above the source region; S740, A drain electrode is formed above the drain region; S750. A gate is formed above the channel region. The gate includes a first part and a second part. The first part is close to the source and the second part is close to the drain. The first part is made of a first material and the second part is made of a second material. The work function of the first material is greater than the work function of the second material.

[0060] In this embodiment, the semiconductor device manufactured according to the above steps has a gate composed of a first part and a second part, which are made of different materials, forming a dual-material gate. In this dual-material gate semiconductor device, the work function of the first material near the source is greater than that of the second material near the drain, resulting in a steeper potential gradient near the drain. This electric field distribution optimizes the control of channel carriers, especially during device turn-off, and can more effectively suppress carrier injection near the drain, thereby reducing leakage current. In addition, this dual-material gate enhances the electric field confinement of the drain region through the lower work function on the drain side, effectively suppressing short-channel effects (such as drain-induced barrier reduction (DIBL)) and further reducing leakage current.

[0061] Figures 8 to 35 A schematic diagram illustrating a semiconductor device manufacturing method according to an embodiment of this application is shown. Figure 8 A schematic diagram illustrating the steps of a semiconductor device manufacturing method according to this embodiment is shown.

[0062] like Figure 8As shown, in this step, a pad oxide layer of a certain thickness is first grown using a furnace tube. Its main purpose is to prevent damage to the silicon surface by the subsequent ion implantation process, and then a deep N-well (DNW) is formed.

[0063] Figure 9 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0064] like Figure 9 As shown, a certain thickness of silicon nitride (SiN) is first deposited to act as a hard mask, then photoresist (PR) is coated and developed. This mainly forms the isolation region STI (Shallow Trench Isolation) between NMOS (N-type MOS transistor) and PMOS (P-type MOS transistor).

[0065] Figure 10 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0066] like Figure 10 As shown, this step involves etching with STI.

[0067] Figure 11 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0068] like Figure 11 As shown, a thin layer of liner oxide (Liner OX) is grown in STI using a furnace tube, which is mainly used to repair damage to the surface of the active area (AA) caused by etch plasma.

[0069] Figure 12 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0070] like Figure 12As shown, TEOS (Tetraethyl Orthosilicate) was deposited in STI using a high aspect ratio process deposition (HARP depo) as the isolation portion of the device. Following the HARP depo, annealing was performed at a specific temperature to make the deposited TEOS more dense. Then, the TEOS was smoothed using CMP (Chemical Mechanical Polishing) and stopped on the silicon nitride (SiN) using EPD (Endpoint Detection).

[0071] Figure 13 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0072] like Figure 13 As shown, silicon nitride (SiN) and oxide (OX) were removed using phosphoric acid and DHF (Dilute Hydrofluoric Acid) to obtain the structure shown in the figure.

[0073] Figure 14 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0074] like Figure 14 As shown, PW (P-well) and NW (N-well) ion implantations were then performed on the left and right sides of the STI, respectively. Figure 14 In this process, ion implantation of the NW region is performed first. First, a photoresist (PR) coating is applied, followed by exposure and development of the NW region, and then ion implantation is carried out. Phosphorus ions (P) and arsenic ions (As) are typically used. Ion implantation is performed in three steps, implanting to different depths each time.

[0075] Figure 15 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0076] First, the photoresist (PR) left over from the previous process is removed. Then, PR is applied, followed by exposure and development of the PW area, and finally ion implantation. Boron (B) ions and boron difluoride (BF2) ions are typically used. Because B ions are lighter, they need to be implanted in four steps, each to a different depth.

[0077] Figure 16 Showing according to Figure 8A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0078] like Figure 16 As shown, the PR (removable photomask) residue from the previous process is first removed, and then a certain thickness of silicon nitride (SiN) is deposited to act as a hard mask. Next, PR is coated, exposed, and then developed. This process mainly forms the drain and gate regions of NMOS and PMOS transistors.

[0079] Figure 17 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0080] like Figure 17 As shown, the hard mask and active region are then etched to obtain the structure shown in the figure.

[0081] Figure 18 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0082] like Figure 18 As shown, the residual PR is then removed using an asher process, and the residual polymer and particles are etched in the wet-clean area to obtain the structure shown in the figure.

[0083] Figure 19 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0084] like Figure 19 As shown, SiN and OX are removed using phosphoric acid and DHF to obtain the structure shown in the figure.

[0085] Figure 20 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0086] like Figure 20As shown, taking a low-voltage device (LV device) as an example, the ISSG (In Situ Steam Generation) process within the RTP (Rapid Thermal Processing) technology is used to generate an input / output oxide (IO OX) layer of a certain thickness in the AA (active region), approximately 23 Å thick. Then, high-K hafnium dioxide (HfO2) and titanium nitride (TiN) of a certain thickness are sequentially deposited using atomic layer deposition, with the high-K hafnium dioxide deposition thickness at 16 Å and the titanium nitride deposition thickness at 20 Å. This is to protect the HK (high-K material) and prevent subsequent metal diffusion. Then, annealing is performed at 680°C for 30 seconds, followed by a three-second heating to 910°C and then cooling. This is to make the HK more dense. This results in the structure shown in the figure.

[0087] Figure 21 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0088] like Figure 21 As shown, a certain thickness of polysilicon (ploy) is deposited in the trench using a furnace tube, then CMP (chemical mechanical polishing) is applied to smooth it and stop it on TiN. The signal of TiN in EPD (endpoint detection) is then captured to stop the process, resulting in the structure shown in the figure.

[0089] Figure 22 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0090] like Figure 22As shown, a layer of aluminum of a certain thickness, up to 800 Å (equivalent to the thickness of polysilicon), is then formed on the wafer surface using CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition) processes. Next, a layer of Ti or TiN of a certain thickness is formed on top of the Al. Then, layers of silicon nitride (SiN), oxide (OX), anti-reflection coating (ARC), and bottom anti-reflective coating (BARC) of a certain thickness are deposited sequentially. The ARC layer comprises SiON (silicon oxynitride) and OX (oxide). Finally, a photopolymer coating (PR) is applied, followed by exposure and development of the gate mask. This results in the structure shown in the diagram.

[0091] Before Al deposition, the polycrystalline silicon surface needs to be thoroughly cleaned to remove oxides, contaminants, and other impurities. Surface treatment processes such as ion bombardment, plasma treatment, or wet chemical treatment can also be introduced to change the surface roughness and hydrophilicity, thus facilitating the adhesion of metallic aluminum. After depositing a certain thickness of Al using PVD or CVD, alloying is performed. This requires thermal annealing in an inert gas atmosphere to promote the reaction between metallic aluminum and polycrystalline silicon, forming an alloyed interface. This alloyed layer can reduce contact resistance and improve interface stability.

[0092] Figure 23 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0093] like Figure 23 As shown, a multi-step etching process is then used to obtain the structure shown in the figure.

[0094] Figure 24 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0095] like Figure 24 As shown, the ROX (recessed oxide) process and the R-alumina (recessed alumina) process are then performed to generate oxide (OX) and alumina of a certain thickness on the sidewalls of the polysilicon.

[0096] Figure 25 Showing according to Figure 8A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0097] like Figure 25 As shown, phosphoric acid is then used to remove SiN to obtain the structure shown in the figure.

[0098] This process results in a 7-shaped gate structure, composed of two different rectangles. The lower half uses a polysilicon layer with a work function of approximately 4.0 to 5.1 eV. High N-type doping achieves 4.0 eV, while high P-type doping achieves 5.1 eV. The upper half uses Al metal with a work function of approximately 4.28 eV. Therefore, depending on the device design, we can fabricate polysilicon with different work functions for NMOS and PMOS devices. Alternatively, the lower half can be made of Al, and the upper half of polysilicon. Various metals can be chosen, such as W / TiN, Mo, Ta, TAN, TiN, gold, silver, and chromium. These metals can have their work functions altered by doping with N or other atoms. It is important to note that the work function of the gate material near the drain should be set lower than that near the source.

[0099] Figure 26 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0100] like Figure 26 As shown, the process then proceeds to the spacer one process, where a certain thickness of oxide (OX) and silicon nitride (SiN) is deposited. Then, a self-aligned etching process is used to remove the horizontal OX and SiN. A certain thickness of OX remains on the AA (active region), resulting in the structure shown in the diagram.

[0101] Figure 27 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0102] like Figure 27 As shown, the process then proceeds to LDD (Lightly Doped Drain) technology. First, photoresist is coated onto NLDD (N-type LDD). After exposure and development, ion implantation is performed. The ion implantation is done at a certain angle, and generally, Ge, C, B (pocket implantation), N, P, and As are implanted sequentially to a certain depth to form the NLDD region.

[0103] Figure 28 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0104] like Figure 28 As shown, the photoresist left from the previous process is removed first, then PLDD (P-type LDD) photoresist is coated, and after exposure and development, ion implantation is performed. Ion implantation is performed at a certain implantation angle. Generally, Ge, C, As (pocket implantation), and BF2 (boron difluoride) are implanted to a certain depth in sequence to form the PLDD region.

[0105] Figure 29 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0106] like Figure 29 As shown, the PR residue left from the previous process is removed first, and then N+ (N ions) and P+ (P ions) are formed in the source and drain regions of the NMOS and PMOS, respectively. This requires two photolithography processes. Figure 29 In the process, the N+ region is first injected with P, Ge, P, As, and F at a certain depth in sequence.

[0107] Figure 30 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0108] like Figure 30 As shown, the PR layer left in the previous layer is removed first, and then P+ ions are implanted. Ge, B and BF2 are implanted into the P+ region in sequence to a certain depth. Then, annealing is performed at a certain temperature using a spike annealing process, for example, 1050℃, mainly to fix the implanted ions to move within a certain region.

[0109] Figure 31 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0110] like Figure 31As shown, the PR layer left from the previous layer is removed first, followed by the SAB (Self-Aligned Barrier) process and the NiSi (nickel silicide) formation process. NiSi is formed in the areas where contact holes (CTs) need to be connected to reduce resistance. First, oxide (OX) and silicon nitride (SiN) are deposited to cover areas where metal silicide formation is not required. Then, metal silicide formation begins. A SiCoNi pre-clean, approximately 60 Å thick, is performed to remove native impurities. Then, a NiPt alloy, approximately 120 Å thick, is deposited. Finally, a TiN capping layer, 50 Å thick, is deposited. Then, after the first RTP1 (rapid thermal treatment 1), the process conditions are 290 degrees Celsius and 30 seconds, forming a high-resistivity metal silicide Ni2PtSi (nickel-platinum-silicon alloy). Then, after the second RTP2 (rapid thermal treatment 2), a low-resistivity NiPtSi2 (nickel-platinum-silicon alloy) is formed. After completion, the Ni in the areas where NiPtSi2 was not formed is removed, thus forming the structure shown in the figure.

[0111] Figure 32 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0112] Next, the contact loop (CT loop) process begins. First, a 300 Å SiN CESL (Contact Etch Stop Layer) is deposited. Then, a TEOS (Tetraethyl Orthosilicate) layer of a certain thickness, 1100 Å, is deposited using a high aspect ratio harp deposition process. Following this, a PE-TEOS (Plasma Enhanced Chemical Vapor Deposition TEOS) layer of a certain thickness, 3600 Å, is deposited using Critical Dimension (CD) CVD. Finally, the ILD (Interlayer Dielectric) is planarized using CMP, and then TEOS is recapped to a thickness of 600 Å. This results in the structure shown in the figure.

[0113] Figure 33 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0114] like Figure 33As shown, a layer of amorphous carbon (aC) with a thickness of 1900 Å is deposited sequentially, followed by a layer of ARC (composed of SiON with a thickness of 320 Å and OX with a thickness of 50 Å), and then a layer of BARC with a thickness of 200 Å. Then, a layer of PR with a thickness of 1000 Å is coated. Finally, the contact holes are exposed and developed.

[0115] Figure 34 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0116] like Figure 34 As shown, the structure shown will be formed by a multi-step dry etching process.

[0117] Figure 35 Showing according to Figure 8 A schematic diagram of the steps in the semiconductor device manufacturing method of the embodiment.

[0118] Next, the WET (wet process) is used to clean up any remaining material from the CT etching process. Then, a 100 Å thick Ti layer and a 50 Å thick TiN layer are deposited sequentially, followed by the deposition of W (tungsten). Finally, the W layer is smoothed by CMP before proceeding to the subsequent metal processing.

[0119] The reasons for needing to deposit both Ti and TiN materials are as follows. If only Ti is used, W deposition would require WF6 (tungsten hexafluoride), which has strong oxidizing properties and will react with Ti, forming defects and causing the entire contact hole to peel off from the substrate. Therefore, a TiN layer is needed to prevent the diffusion and contact between WF6 and Ti. If only TiN is used, its stress is very high, making it easy to peel off from the substrate. Ti is needed as a mitigating layer to improve adhesion.

[0120] The concepts, principles, and ideas of this application have been described in detail above with reference to specific embodiments (including examples and instances). Those skilled in the art should understand that the embodiments of this application are not limited to those given above. After reading this application, those skilled in the art can make any possible improvements, substitutions, and equivalents to the steps, methods, apparatus, and components in the above embodiments, and such improvements, substitutions, and equivalents should be considered to fall within the scope of this application. The scope of protection of this application is limited to the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device is a metal-oxide-semiconductor semiconductor, comprising: A semiconductor substrate (110) includes a first surface (111) and a second surface (112) disposed opposite to each other. The semiconductor substrate (110) is provided with a channel region (113), a source region (114) and a drain region (115) extending from the first surface (111) into the semiconductor substrate (110). The source region (114) and the drain region (115) are respectively disposed on both sides of the channel region (113). Source electrode (120), the source electrode (120) is disposed above the source region (114); Drain (130), the drain (130) is disposed above the drain region (115); A gate (140) is disposed above the channel region (113). The gate (140) includes a first portion (141) and a second portion (142). The first portion (141) is close to the source (120), and the second portion (142) is close to the drain (130). The first portion (141) is made of a first material, and the second portion (142) is made of a second material. The work function of the first material is greater than that of the second material. The first part (141) is formed by depositing polycrystalline silicon and CMP polishing. The first surface (111) is in the shape of a stepped platform, and the channel area (113) covers the height variation portion of the first surface (111). The first surface (111) includes a first planar portion (216), a vertical portion (217), and a second planar portion (218). The first planar portion (216) is higher than the second planar portion (218). The vertical portion (217) connects the first planar portion (216) and the second planar portion (218) at its upper and lower ends, respectively. The drain area (115) is disposed in the first planar portion (216), and the source area (114) is disposed in the second planar portion (218). The channel area (113) is configured to cover the vertical portion (217), the first adjacent portion of the first planar portion (216) adjacent to the vertical portion (217), and the second adjacent portion of the second planar portion (218) adjacent to the vertical portion (217). The first portion (141) is configured to cover the vertical portion (217) from the side and the second adjacent portion from above. The second portion (142) is configured to cover the first adjacent portion and the first portion (141) from above.

2. The semiconductor device according to claim 1, characterized in that, The first material comprises polycrystalline silicon, and the second material comprises metal.

3. The semiconductor device according to claim 1, characterized in that, in, The first part (141) has a first protective layer (443) on the side away from the vertical part (217) in the horizontal direction, and the second part (142) has a second protective layer (444) and a third protective layer (445) on both sides in the horizontal direction.

4. The semiconductor device according to claim 3, characterized in that, The first protective layer (443) includes an oxide layer and a silicon nitride layer, the second protective layer (444) includes an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer, and the third protective layer (445) includes an aluminum oxide layer, a silicon oxide layer and a silicon nitride layer.

5. The semiconductor device according to claim 1, characterized in that, An isolation layer (550) is provided between the gate (140) and the first surface (111).

6. The semiconductor device according to claim 5, characterized in that, The isolation layer (550) includes a titanium nitride layer, a hafnium dioxide layer, and a silicon oxide layer.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate (110) further includes a lightly doped source region (680) and a lightly doped drain region (650), wherein the lightly doped source region (680) is disposed outside the source region (114) and the lightly doped drain region (650) is disposed outside the drain region (115).

8. The semiconductor device according to claim 7, characterized in that, The semiconductor substrate (110) has a well layer (660) below the channel region (113), the source lightly doped region (680), and the drain lightly doped region (650).

9. The semiconductor device according to claim 8, characterized in that, The semiconductor substrate (110) has a deep well layer (670) disposed below the well layer (660).

10. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device is a metal-oxide-semiconductor semiconductor, comprising: A semiconductor substrate (110) is provided, the semiconductor substrate (110) including a first surface (111) and a second surface (112) disposed opposite to each other. A channel region (113), a source region (114), and a drain region (115) extending from the first surface (111) into the semiconductor substrate (110) are formed therein, wherein the source region (114) and the drain region (115) are respectively disposed on both sides of the channel region (113); A source electrode (120) is formed above the source region (114); A drain electrode (130) is formed above the drain region (115); A gate (140) is formed above the channel region (113). The gate (140) includes a first portion (141) and a second portion (142). The first portion (141) is close to the source (120), and the second portion (142) is close to the drain (130). The first portion (141) is made of a first material, and the second portion (142) is made of a second material. The work function of the first material is greater than that of the second material. The first part (141) is formed by depositing polycrystalline silicon and CMP polishing. The first surface (111) is in the shape of a stepped platform, and the channel area (113) covers the height variation portion of the first surface (111). The first surface (111) includes a first planar portion (216), a vertical portion (217), and a second planar portion (218). The first planar portion (216) is higher than the second planar portion (218). The vertical portion (217) connects the first planar portion (216) and the second planar portion (218) at its upper and lower ends, respectively. The drain area (115) is disposed in the first planar portion (216), and the source area (114) is disposed in the second planar portion (218). The channel area (113) is configured to cover the vertical portion (217), the first adjacent portion of the first planar portion (216) adjacent to the vertical portion (217), and the second adjacent portion of the second planar portion (218) adjacent to the vertical portion (217). The first portion (141) is configured to cover the vertical portion (217) from the side and the second adjacent portion from above. The second portion (142) is configured to cover the first adjacent portion and the first portion (141) from above.

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