A method for transferring low-dimensional semiconductor materials and its array structure

Abstract

This invention provides a method for transferring low-dimensional semiconductor materials and its array structure, relating to the field of semiconductor material and device manufacturing technology. It achieves wafer-level non-destructive transfer of low-dimensional semiconductor material arrays by repeatedly transferring small areas of low-dimensional semiconductor materials to form an array, which can be used to realize high-yield wafer-level low-dimensional semiconductor material transfer and chip manufacturing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials and device manufacturing technology, specifically to a method for transferring low-dimensional semiconductor materials and an array structure of low-dimensional semiconductor materials. Background Technology

[0002] Low-dimensional semiconductor materials, especially those with atomic-level thickness, high carrier mobility, flexibility, and transparency, are considered core candidate materials for continuing Moore's Law and realizing flexible electronics. Industrial applications require the complete, wrinkle-free, and undamaged transfer of large-size low-dimensional semiconductor material films from growth substrates (such as sapphire) to target device substrates (such as SiO2 / Si wafers).

[0003] Existing wafer-level transfer technologies for low-dimensional semiconductor materials (PMMA wet process, roll-to-roll dry process, PDMS stamping, etc.) face the following common challenges at the ≥100 mm wafer scale: 1. The internal stress and surface tension of the thin film increase linearly with area, making it easy to generate cracks and voids; 2. The damage location is randomly distributed, and falling into the device channel area will cause chip failure, resulting in low wafer-level device yield; 3. The electrical properties of the grown wafer have spatial inhomogeneity, and the whole-wafer transfer cannot make optimal use of high-quality areas; 4. The edge defects of the transfer area cannot be matched with the photolithography size, resulting in poor performance consistency of the core circuit area.

[0004] Therefore, the industry urgently needs a transfer solution that can achieve "non-destructive, high-yield, and precise positioning" at the wafer scale and is compatible with existing production lines. Summary of the Invention

[0005] Based on this, the purpose of this invention is to provide a method for transferring low-dimensional semiconductor materials and a low-dimensional semiconductor material array structure to achieve single, damage-free transfer, and then splice them into a complete array on the target substrate, thereby simultaneously solving the four major problems of damage, yield, positioning and uniformity.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A method for transferring low-dimensional semiconductor materials includes the following steps:

[0008] S100 cuts low-dimensional semiconductor materials grown on a source substrate into multiple small pieces;

[0009] S200 utilizes a transfer platform to position and transfer individual low-dimensional semiconductor material wafers.

[0010] S300, repeat step S200 to form a low-dimensional semiconductor material array on the target substrate, realizing the non-destructive transfer of wafer-level low-dimensional semiconductor materials.

[0011] Optionally, S200 also includes the following steps:

[0012] S210, removes the source substrate, making the low-dimensional semiconductor material wafers independent;

[0013] S220, using a transfer platform, the low-dimensional semiconductor material wafer is transferred and bonded to a designated area of ​​the target substrate by optical microscopic alignment.

[0014] Optionally, the following steps may be included between step S100 and step S200:

[0015] S110, a transfer medium is applied to the surface of the small piece to form a transfer medium / low-dimensional semiconductor material / source substrate composite structure.

[0016] Optionally, the following steps may be included between step S110 and step S200:

[0017] S120 removes the source substrate, making the transfer dielectric / low-dimensional semiconductor material composite structure independent.

[0018] Optionally, the transfer medium is a flexible transfer medium or a rigid transfer medium.

[0019] Optionally, the following steps are also included:

[0020] S400, Remove transfer medium;

[0021] Step S400 is positioned between steps S200 and S300 to remove the transfer medium after each of the low-dimensional semiconductor material wafers has been transferred; or

[0022] Step S400 is set after step S300 to remove the transfer medium after forming a low-dimensional semiconductor material array on the target substrate.

[0023] Optionally, the size of each of the low-dimensional semiconductor material wafers is greater than or equal to the size of the target chip die.

[0024] Optionally, the size of each of the low-dimensional semiconductor material wafers is matched with the size of the target chip die, and the gap between adjacent low-dimensional semiconductor material wafers after transfer is located in the non-channel region of the target chip die.

[0025] Optionally, when cutting the low-dimensional semiconductor material wafers, the source substrate is also cut simultaneously to form a low-dimensional semiconductor material / source substrate wafer structure.

[0026] Optionally, the growth size of the low-dimensional semiconductor material is at the wafer level, and the low-dimensional semiconductor material includes at least one or more combinations of graphene, molybdenum disulfide, tungsten diselenide, boron nitride, molybdenum diselenide, carbon nanotubes, and IGZO and SiC.

[0027] Optionally, the source substrate and target substrate include one or a combination of SiO2 / Si, quartz, flexible PI, PET, ITO glass, silicon nitride, silicon carbon nitride, graphite, gallium arsenide, indium phosphide, lithium niobate, SiGe, AlN / GaN, SrTiO3, polycarbonate, MgO, copper foil, gold, nickel, titanium, sapphire, hafnium oxide, aluminum oxide, mica, SiC, TiC, WC, GaN, and AlN.

[0028] Optionally, the cutting method is any one or a combination of laser cutting, stealth cutting, deep ultraviolet lithography followed by etching, plasma etching, and mechanical cutting.

[0029] Optionally, the step of removing the source substrate may employ wet chemical etching, mechanical stripping, or water-assisted stripping.

[0030] Optionally, the transfer platform has sub-millimeter alignment accuracy.

[0031] Optionally, the transfer platform is equipped with a heating module for releasing the heat-release tape.

[0032] Optionally, the side length of the low-dimensional semiconductor material wafer is 5 mm to 100 mm.

[0033] The present invention also provides a low-dimensional semiconductor material array structure, which is prepared by the aforementioned method, and the array structure is composed of multiple small-sized low-dimensional semiconductor material chips.

[0034] Optionally, the edge of the low-dimensional semiconductor material wafer is located in the dicing groove between the bare dies, so that the device channel region avoids edge defects.

[0035] Optionally, the low-dimensional semiconductor material array structure can be used in integrated circuits, solar cells, or optoelectronic devices.

[0036] This invention provides a method for transferring low-dimensional semiconductor materials. Taking advantage of the low breakage rate of small-piece transfer, the method involves cutting the low-dimensional semiconductor material into small pieces and sequentially positioning and transferring them in an array. This method can achieve complete and high-yield transfer of low-dimensional semiconductor materials at the die location. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0038] Figure 1 This is a flowchart illustrating a method for transferring low-dimensional semiconductor materials according to the present invention.

[0039] Figure 2 This is a schematic diagram of a method for transferring low-dimensional semiconductor materials according to the present invention;

[0040] Figure 3 This is a schematic diagram of a transfer scheme combining a method for transferring low-dimensional semiconductor materials with PMMA-assisted wet transfer according to the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and beneficial effects of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] This invention proposes a technical approach of "cutting first, then arraying, and multiple precise positioning and transfers," which disperses the risk of wafer-level breakage to small wafer-sized pieces. It achieves single, breakage-free transfer with the assistance of flexible media and splices them into a complete array on the target substrate, thereby simultaneously solving the four major problems of breakage, yield, positioning, and uniformity.

[0043] like Figure 1 and Figure 2 As shown, the present invention provides a method for transferring low-dimensional semiconductor materials, comprising the following steps:

[0044] S100 cuts low-dimensional semiconductor materials grown on a source substrate into multiple small pieces;

[0045] S200 utilizes a transfer platform to position and transfer individual low-dimensional semiconductor material wafers.

[0046] S300, repeat step S200 to form a low-dimensional semiconductor material array on the target substrate, realizing the non-destructive transfer of wafer-level low-dimensional semiconductor materials.

[0047] like Figure 2As shown, the present invention provides an example of a method for transferring low-dimensional semiconductor materials, which is based on flexible dielectric-assisted transfer of low-dimensional semiconductor materials. First, the low-dimensional semiconductor material to be transferred is precisely cut into individual die sizes (e.g., 8*8mm). 2 Then, precise positioning and transfer are performed to ensure that the position and size of the low-dimensional semiconductor material transferred to the target substrate meet the requirements of subsequent chip fabrication. Since the probability of breakage during small-piece transfer is much lower than that during wafer transfer, the device yield of the low-dimensional semiconductor material array obtained by this method is greatly improved.

[0048] Specifically, in step S100, the side length of the small pieces cut from the low-dimensional semiconductor material is 5 mm to 100 mm. The low-dimensional semiconductor material includes at least one or more combinations of graphene, molybdenum disulfide, tungsten diselenide, boron nitride, molybdenum diselenide, carbon nanotubes, and IGZO and SiC. Specifically, taking a two-dimensional material as an example, it can be a single crystal, polycrystalline, or stacked heterostructure, specifically selected from graphene (including single-layer, double-layer, and few-layer structures, e.g., 1–10 layers), semiconducting transition metal chalcogenides (such as molybdenum disulfide MoS2, molybdenum diselenide MoSe2, tungsten disulfide WS2, tungsten diselenide WSe2, and any alloy of Mo), etc. 1-x W x S2, MoS 2(1-x) Se 2x The materials include, etc.), insulator hexagonal boron nitride (h-BN, number of layers 1–50), and other low-dimensional semiconductor materials, as well as one or more van der Waals heterojunctions (e.g. Gr / h-BN, MoS2 / h-BN, MoS2 / WS2, etc.) formed by vertically stacking the above materials.

[0049] The source substrate can include one or a combination of SiO2 / Si, quartz, flexible PI, PET, ITO glass, silicon nitride, silicon carbon nitride, graphite, silicon, gallium arsenide (GaAs), indium phosphide (InP), lithium niobate (LiNbO3), SiGe, AlN / GaN, SrTiO3, polycarbonate, MgO, copper foil, gold, nickel, titanium, sapphire, hafnium oxide, alumina, quartz, mica, SiC, TiC, WC, GaN, and AlN. Specifically, taking two-dimensional materials as an example, the source substrate can be selected from c-plane or r-plane sapphire (Al2O3), 4H- or 6H-silicon carbide (SiC), fused silica, or synthetic quartz glass.

[0050] In step S300, the target substrate is the carrier of the final device or functional thin film. Specifically, it can be selected from silicon oxide / heavily doped silicon wafers and silicon oxide / heavily doped silicon wafers with pre-prepared bottom gate / dielectric layer structures (for back gate field effect devices), high-purity quartz (UV transmittance >85%, suitable for photoelectric detection windows), flexible polyimide (PI, thickness 25–125 μm, glass transition temperature Tg >350 °C, suitable for high-temperature flexible electronics), flexible polyethylene terephthalate (PET, thickness 50–200 μm, transmittance >90%, suitable for wearable displays), soda-lime or borosilicate glass (thickness 100–700 μm, suitable for transparent electrodes or optoelectronic integration), and the above-mentioned substrates that have undergone pre-surface treatment (such as spin-coating adhesive layers APTES, PMMA or SOG, plasma activation, evaporation of organic macromolecules, etc., to increase the mechanical strength of the transfer interface).

[0051] Optionally, S200 also includes the following steps:

[0052] S210, removes the source substrate, making the low-dimensional semiconductor material wafers independent;

[0053] S220, using a transfer platform, the low-dimensional semiconductor material wafer is transferred and bonded to a designated area of ​​the target substrate by optical microscopic alignment.

[0054] Specifically, the size of each low-dimensional semiconductor material wafer is greater than or equal to the size of the target chip die. In one specific implementation, the size of each low-dimensional semiconductor material wafer matches the size of the target chip die, and the gap between adjacent low-dimensional semiconductor material wafers after transfer is located in the non-channel region of the target chip die. This ensures that the breakage points caused by cutting and transfer during the transfer of low-dimensional semiconductor material wafers are all located in the non-channel region of the target chip die, thereby guaranteeing that the areas of the target chip die to be processed in subsequent processes are undamaged, thus improving yield.

[0055] In one specific implementation, when cutting low-dimensional semiconductor material wafers, the source substrate can be cut simultaneously to form a low-dimensional semiconductor material / source substrate wafer structure for easy transfer.

[0056] Optionally, the following steps may be included between step S100 and step S200:

[0057] S110, a transfer medium is applied to the surface of the small piece to form a transfer medium / low-dimensional semiconductor material / source substrate composite structure.

[0058] The following steps may also be included between step S110 and step S200:

[0059] S120 removes the source substrate, making the transfer dielectric / low-dimensional semiconductor material composite structure independent.

[0060] It should be noted that when transferring low-dimensional semiconductor materials, the transfer medium can be a flexible medium or a rigid medium. In some other embodiments, the transfer can also be performed without a transfer medium.

[0061] In step S110, the flexible transfer medium is a temporary carrier that can be spin-coated, vapor-deposited, and peeled off, and can form a weak van der Waals interface or controllable chemical bond with low-dimensional semiconductor materials. Specifically, it can be selected from: polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinylpyrrolidone (PVP), polydimethylsiloxane (PDMS), polystyrene (PS), metal auxiliary layer (Cu, Ni or Au), etc. The above media can be used alone, or can be multilayered with various tapes such as heat-release tape, water-soluble tape, blue film (such as PMMA / Cu / tape, PVA / PDMS stack) to take into account the characteristics of mechanical support, thermal stability and easy removal.

[0062] In some embodiments, the following steps may also be included:

[0063] S400, Remove transfer medium;

[0064] Step S400 is positioned between steps S200 and S300 to remove the transfer medium after each low-dimensional semiconductor material wafer is transferred; or

[0065] Step S400 is set after step S300 to remove the transfer medium after forming a low-dimensional semiconductor material array on the target substrate.

[0066] Specifically, if a transfer medium is used to assist in the transfer process, the transfer medium needs to be removed after the transfer. The transfer medium can be removed after each low-dimensional semiconductor material chip is transferred, or it can be removed all at once after all low-dimensional semiconductor material chips have been transferred and formed into a low-dimensional semiconductor material array.

[0067] In step S100, various cutting methods can be used to achieve the required cutting precision and damage. For example, laser cutting, stealth cutting, deep ultraviolet lithography followed by etching, plasma etching, and mechanical cutting can be used. These methods can be used individually or in cascade: for example, stealth cutting can be used to pre-fabricate cleavage surfaces inside the substrate, and then DUV lithography can be used to define the device area to achieve "macro-micro" dual-scale patterning.

[0068] Let's take laser cutting as an example. Laser cutting can use a focused Gaussian beam or a picosecond / femtosecond ultrafast laser, scanned in air, nitrogen, or medium atmosphere, with a heat-affected zone <2 µm and a kerf width as narrow as 5 µm; for monolayer sulfides such as MoS2 and WS2, the laser power density is 0.5-1.5 J cm⁻¹. -2 This allows for cold ablation without molten edges.

[0069] In step S210, the process of removing the source substrate needs to consider the material system, thickness, and subsequent integrity. Specific strategies include:

[0070] Wet chemical etching is used for sapphire at 85-95 ℃ with 3-7 M KOH solution, and for SiO2 / Si substrates, room temperature HF (1-5%) or buffered oxide etching solution (BOE 7:1) is used.

[0071] Mechanical peeling utilizes the difference in bonding forces between low-dimensional semiconductor materials and transfer media, and between low-dimensional semiconductor materials and growth substrates, to generate shear stress at the interface through rolling or three-point bending, achieving "dry" separation.

[0072] Water-assisted stripping utilizes the difference in hydrophilicity and hydrophobicity at different interfaces to separate low-dimensional semiconductor materials from the source substrate.

[0073] In step S220, the transfer platform is an integrated micro-nano manipulation system of "optics-piezoelectricity-heating" with micron to sub-millimeter level alignment accuracy, so as to accurately transfer and bond low-dimensional semiconductor material chips to a designated area of ​​the target substrate through optical micro-alignment.

[0074] In some embodiments, the transfer platform may also integrate a heating module for heating and releasing the heat release tape.

[0075] This invention provides a method for transferring low-dimensional semiconductor materials. Leveraging the low breakage rate of small-wafer transfers, the method involves cutting the low-dimensional semiconductor material into small wafers and sequentially positioning and transferring them in an array. This achieves complete and high-yield transfer of the low-dimensional semiconductor material at the die location. Direct wafer transfer of low-dimensional semiconductor materials results in uncontrollable void and crack locations, leading to low overall wafer device yield. In contrast, single-wafer transfers achieve high yields. By cutting the low-dimensional semiconductor material wafer into small wafers and performing multiple breakage-free small-wafer transfers, high-yield wafer-level transfer of low-dimensional semiconductor materials can ultimately be achieved.

[0076] The present invention provides a method for transferring low-dimensional semiconductor materials. For cases where the properties of low-dimensional semiconductor materials are not uniform within the wafer, additional detection steps can be added, such as characterization methods like optical microscopy, atomic force microscopy, Raman scanning imaging, and second harmonic imaging, to obtain information such as coverage, grain size, crystal orientation, and surface roughness. This information can then be used to select the optimal region in the grown wafer for transfer, thereby improving the performance of the target wafer.

[0077] This invention also provides a low-dimensional semiconductor material array structure, prepared by the aforementioned method. The low-dimensional semiconductor material array structure is composed of multiple die-sized low-dimensional semiconductor material wafers spliced ​​together, with continuous and undamaged low-dimensional semiconductor material within each wafer. The edges of the low-dimensional semiconductor material wafers are located within the chip dicing groove or test area, allowing the device channel region to avoid edge defects. This facilitates matching the low-dimensional semiconductor material transfer area with the specific photomask unit area (shot size) in the device process. This allows all edge defects in the transfer area to be located in the test area (i.e., non-channel area) surrounding each die, maximizing the circuit performance of the core area within the die.

[0078] This invention provides a method for transferring low-dimensional semiconductor materials. By transferring small areas of low-dimensional semiconductor materials into an array multiple times without damage, a wafer-level low-dimensional semiconductor material array can be transferred without damage. This method can be used to achieve high-yield wafer-level low-dimensional semiconductor material transfer and chip manufacturing.

[0079] The following is a description using specific embodiments.

[0080] Example 1:

[0081] like Figure 3 As shown, Example 1 uses heat-release tape / PMMA-assisted wet transfer of molybdenum disulfide as an example to illustrate the detailed steps for achieving high-yield transfer:

[0082] 1. The molybdenum disulfide / sapphire wafer to be transferred is laser-cut into multiple small pieces, the size of which conforms to the size of a single die (the die size is related to the chip design, for example, 8*8 mm). 2 Or 10*10mm 2 (a square);

[0083] 2. Spin-coat the surface of the cut pieces with PMMA adhesive and bake (e.g., 950, A2, 2000 rpm for 1 minute, then bake at 180℃ for 1 minute).

[0084] 3. Immerse the PMMA / molybdenum disulfide / sapphire wafers after homogenization in a heated (temperature example: 90℃) potassium hydroxide (KOH) solution to etch the substrate (potassium hydroxide solution concentration example: 5g KOH, 50 ml ultrapure water) for a certain period of time (e.g., 1 hour).

[0085] 4. After soaking, the PMMA / molybdenum disulfide is separated from the sapphire substrate. First, it is rinsed with ultrapure water, then the structure is lifted out of the water with a clean substrate and dried. Then, heat release tape is applied to the PMMA / molybdenum disulfide and peeled off.

[0086] 5. On a high-precision transfer stage, use an optical microscope to align and bond the heat-release tape / PMMA / molybdenum disulfide and the target substrate to be transferred.

[0087] 6. Heat the bonded structure (the heating temperature depends on the type of heat release tape, usually 90-150℃) to release the heat release tape;

[0088] 7. Immerse PMMA / molybdenum disulfide / target substrate in acetone to dissolve and remove PMMA, ultimately achieving complete and undamaged transfer of molybdenum disulfide from a single die area;

[0089] 8. Repeat the above process to achieve the transfer of multiple bare wafer-level molybdenum disulfide arrays.

[0090] Example 2:

[0091] This second embodiment uses PVA-assisted wet transfer of molybdenum disulfide as an example to illustrate the detailed steps for achieving high-yield transfer:

[0092] 1. The molybdenum disulfide / sapphire wafer to be transferred is laser-cut into multiple small pieces, the size of which conforms to the size of a single die (the die size is related to the chip design, for example, 8*8 mm). 2 Or 10*10 mm 2 (a square);

[0093] 2. Spin-coat the surface of the cut pieces with PVA / PVP and bake (PVP such as 58000, 2500 rpm for 1 minute, then bake at 70℃ for 1 minute; PVA such as 9% by mass, degree of hydrolysis 98%~99%).

[0094] 3. Peel off the PVA / PVP / molybdenum disulfide flakes from the sapphire after homogenization;

[0095] 4. On a high-precision transfer stage, use an optical microscope to align and bond the areas to be transferred of PVA / PVP / molybdenum disulfide and the target substrate.

[0096] 5. Immerse PVA / PVP / molybdenum disulfide / target substrate in deionized water (70-80℃) to remove PVA / PVP, ultimately achieving complete and undamaged transfer of molybdenum disulfide from a single die area;

[0097] 6. Repeat the above process to achieve the transfer of multiple bare wafer-level molybdenum disulfide arrays.

[0098] Example 3:

[0099] Taking PDMS-assisted wet transfer of molybdenum disulfide as an example, the detailed steps to achieve high-yield transfer are as follows:

[0100] 1. The molybdenum disulfide / sapphire wafer to be transferred is laser-cut into multiple small pieces, the size of which matches the size of a single bare wafer;

[0101] 2. Adhere the transfer medium PDMS to the cut pieces;

[0102] 3. Place the bonded PDMS / molybdenum disulfide / sapphire into deionized water for peeling;

[0103] 4. On a high-precision transfer stage, use an optical microscope to align and bond the PDMS / molybdenum disulfide and the target substrate to be transferred.

[0104] 5. Heat the PDMS / molybdenum disulfide / target substrate (e.g., 70°C) and slowly peel it off to achieve complete and undamaged transfer of molybdenum disulfide from a single bare wafer area;

[0105] 6. Repeat the above process to achieve the transfer of multiple bare wafer-level molybdenum disulfide arrays.

[0106] Example 4:

[0107] Taking PS-assisted wet transfer of molybdenum disulfide as an example, the detailed steps for achieving high-yield transfer using this method are as follows:

[0108] 1. The molybdenum disulfide / sapphire wafer to be transferred is laser-cut into multiple small pieces, the size of which matches the size of a single bare wafer;

[0109] 2. Spin-coat the surface of the cut pieces with PS and bake (parameter example: 3500 rpm for 1 minute, 80-90℃ for 15 minutes).

[0110] 3. Apply heat-release tape to the PS / molybdenum disulfide / sapphire surface after spin coating and immerse it in deionized water for peeling.

[0111] 4. On a high-precision transfer stage, use an optical microscope to align and bond the heat-release tape / PS / molybdenum disulfide and the target substrate to be transferred.

[0112] 5. Heat the heat release tape / PS / molybdenum disulfide / target substrate (e.g., 120°C) to remove the heat release tape;

[0113] 6. Rinse the PS / molybdenum disulfide / target substrate surface with toluene to remove PS, ultimately achieving complete and undamaged transfer of molybdenum disulfide from a single die area;

[0114] 7. Repeat the above process to achieve the transfer of multiple bare wafer-level molybdenum disulfide arrays.

[0115] Example 5:

[0116] Taking copper-assisted wet transfer of molybdenum disulfide as an example, the detailed steps for achieving high-yield transfer using this method are as follows:

[0117] 1. The molybdenum disulfide / sapphire wafer to be transferred is laser-cut into multiple small pieces, the size of which matches the size of a single bare wafer;

[0118] 2. A copper (Cu) thin film of approximately 60 nanometers thick is vapor-deposited onto the surface of the cut pieces;

[0119] 3. Apply the heat release tape to the copper / molybdenum disulfide / sapphire, and then peel off the heat release tape from the copper / molybdenum disulfide.

[0120] 4. On a high-precision transfer stage, use an optical microscope to align and bond the heat-release tape / copper / molybdenum disulfide and the target substrate to be transferred.

[0121] 5. Heat the heat release tape / copper / molybdenum disulfide / target substrate (e.g., 120°C) to remove the heat release tape;

[0122] 6. Etching the Cu film: The copper film is etched using a mixed solution of 15% ammonium persulfate and deionized water; ultimately achieving complete and undamaged transfer of molybdenum disulfide across a single die area;

[0123] 7. Repeat the above process to achieve the transfer of multiple bare wafer-level molybdenum disulfide arrays.

[0124] This invention provides a method for transferring low-dimensional semiconductor materials and a corresponding array structure of low-dimensional semiconductor materials, offering a feasible, economical, and scalable technical path for low-dimensional semiconductor materials to enter mainstream semiconductor production lines. It has the following advantages:

[0125] Breakage rate <0.1%, component yield ≥99%;

[0126] The low-dimensional semiconductor material within the array is continuous and crack-free, with a thickness non-uniformity of <3%;

[0127] Edge defects can be precisely arranged into the dicing slots, and the non-uniformity of the conduction current of the core components is <5%;

[0128] High-mobility regions can be selectively transferred, resulting in an overall performance improvement of 10%–30% for the target wafer.

[0129] It is compatible with mainstream flexible media such as PMMA, PVA, PDMS, PS, and metal-assisted materials, requiring no additional equipment.

[0130] The embodiments described above are merely illustrative of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the present invention.

Claims

1. A method for transferring low-dimensional semiconductor materials, characterized in that, Includes the following steps: S100 cuts low-dimensional semiconductor materials grown on a source substrate into multiple low-dimensional semiconductor material chips; S200 utilizes a transfer platform to position and transfer individual low-dimensional semiconductor material wafers. S300, repeating step S200, forms a low-dimensional semiconductor material array on the target substrate, achieving wafer-level, damage-free transfer of low-dimensional semiconductor materials. The low-dimensional semiconductor material array is composed of multiple low-dimensional semiconductor material chips spliced ​​together. The size of each low-dimensional semiconductor material wafer is greater than or equal to the size of the target chip die, and after transfer, the gap between adjacent low-dimensional semiconductor material wafers is located in the non-channel region of the target chip die. When cutting the plurality of low-dimensional semiconductor material wafers, the source substrate is also cut simultaneously to form a low-dimensional semiconductor material / source substrate wafer structure.

2. The method according to claim 1, characterized in that, S200 also includes the following steps: S210, removes the source substrate, making the low-dimensional semiconductor material wafers independent; S220, using a transfer platform, the low-dimensional semiconductor material wafer is transferred and bonded to a designated area of ​​the target substrate by optical microscopic alignment.

3. The method according to claim 2, characterized in that, The following steps are also included between step S100 and step S200: S110, a transfer medium is applied to the surface of the small piece to form a transfer medium / low-dimensional semiconductor material / source substrate composite structure.

4. The method according to claim 3, characterized in that, The following steps are also included between step S110 and step S200: S120 removes the source substrate, making the transfer dielectric / low-dimensional semiconductor material composite structure independent.

5. The method according to claim 3 or 4, characterized in that, The transfer medium is either a flexible transfer medium or a rigid transfer medium.

6. The method according to claim 3 or 4, characterized in that, It also includes the following steps: S400, Remove transfer medium; Step S400 is set between steps S200 and S300 to remove the transfer medium after each of the low-dimensional semiconductor material wafers is transferred; or Step S400 is set after step S300 to remove the transfer medium after forming a low-dimensional semiconductor material array on the target substrate.

7. The method according to any one of claims 1-4, characterized in that, The low-dimensional semiconductor material includes at least one or more combinations of graphene, molybdenum disulfide, tungsten diselenide, boron nitride, molybdenum diselenide, carbon nanotubes, and IGZO and SiC.

8. The method according to any one of claims 1-4, characterized in that, The source and target substrates include one or a combination of SiO2 / Si, quartz, flexible PI, PET, ITO glass, silicon nitride, silicon carbon nitride, graphite, gallium arsenide, indium phosphide, lithium niobate, SiGe, AlN / GaN, SrTiO3, polycarbonate, MgO, copper foil, gold, nickel, titanium, sapphire, hafnium oxide, aluminum oxide, mica, SiC, TiC, WC, GaN, and AlN.

9. The method according to any one of claims 2-4, characterized in that, The cutting method is any one or a combination of laser cutting, stealth cutting, deep ultraviolet lithography followed by etching, plasma etching, and mechanical cutting; the step of removing the source substrate is performed by wet chemical etching, mechanical stripping, or liquid-assisted stripping.

10. The method according to any one of claims 1-4, characterized in that, The transfer platform has an alignment accuracy of sub-millimeter level or higher.

11. The method according to any one of claims 1-4, characterized in that, The transfer platform is equipped with a heating module for releasing the heat-release tape.

12. The method according to any one of claims 1-4, characterized in that, The side length of the low-dimensional semiconductor material chip is 5 mm to 100 mm.

13. A low-dimensional semiconductor material array structure, characterized in that, The array structure is prepared by any one of claims 1 to 12 and is composed of multiple small-sized low-dimensional semiconductor material chips.

14. The low-dimensional semiconductor material array structure according to claim 13, characterized in that, The edge of the low-dimensional semiconductor material wafer is located in the dicing groove between the bare dies, so that the device channel region avoids edge defects.

15. An integrated circuit, characterized in that, Including the low-dimensional semiconductor material array structure according to claim 13 or 14.

16. An optoelectronic device, characterized in that, Including the low-dimensional semiconductor material array structure according to claim 13 or 14.

17. The optoelectronic device according to claim 16, characterized in that, The optoelectronic device includes a solar cell.

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