A compact half-bridge package structure with low parasitic inductance

Abstract

This invention provides a compact, low-parasitic-inductance half-bridge package structure. A main substrate has positive and AC connection terminals at both ends. A first chip and a second chip are positioned between the two terminals. The positive power electrode of the first chip is electrically connected to the positive connection terminal, the positive power electrode of the second chip is electrically connected to the AC connection terminal, and the negative power electrode of the second chip is electrically connected to the negative terminal. A control substrate is positioned directly above the two chips. One surface of the control substrate has a first bridging connector, through which the negative power electrode of the first chip is electrically connected to the AC connection terminal. The other surface of the control substrate has multiple gate connectors capable of energizing the gates of the two chips. This invention, by placing the control substrate above the main substrate, positions the device gates above the surface, reducing the planar space occupied by the gates and shortening the distance between the gate connectors and the chip gates, thus reducing the overall size of the package structure.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging, and in particular relates to a compact half-bridge packaging structure with low parasitic inductance. Background Technology

[0002] Silicon carbide devices are among the most widely used wide-bandgap semiconductor electronic devices, demonstrating great potential in high-power, high-temperature, and high-frequency applications due to their excellent physical properties. They are now widely used in fields such as new energy vehicles, flexible power grids, aerospace, and smart manufacturing.

[0003] In some chip applications, external signals control the power terminals connected to the main circuit to open / close via the chip's signal terminals, thereby controlling the circuit's on / off state. Currently, most power module packaging structures adopt the traditional packaging layout of silicon-based chips, which cannot fully utilize the performance of silicon carbide devices. Moreover, the packaged size is relatively large, which is not conducive to the miniaturization design of electrical appliances.

[0004] Currently, most traditional packages arrange power and signal terminals in a flat layout, which often requires a large planar space and results in large spacing between some connected devices and pins, excessively long wiring, and a tendency to generate large parasitic inductance during operation, increasing module losses. In some packages, in order to enable devices to respond faster during use or to collect environmental data during operation, gate drivers, temperature and current sensing components are also added to the package, further occupying internal space and making the overall package size larger. Some fields where such packages are used (such as electric vehicles, aerospace, and compact frequency inverters) are space-sensitive fields, which need to minimize the space occupied by electronic components in order to reduce the application cost of the product.

[0005] Furthermore, as the switching frequency of devices increases, traditional packaging structures are more prone to generating larger parasitic inductances, increasing module losses, causing voltage overshoot, and affecting the stability of power module operation. Summary of the Invention

[0006] In view of this, the present invention aims to propose a compact half-bridge package structure with low parasitic inductance, so as to reduce the package size and reduce the parasitic inductance generated by the device in the package during operation.

[0007] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0008] A compact half-bridge package structure with low parasitic inductance, including

[0009] The main substrate has a positive connection terminal at one end and an AC connection terminal at the other end. A first chip and a second chip are fixed between the positive connection terminal and the AC connection terminal. The positive power electrode of the first chip is electrically connected to the positive connection terminal, the positive power electrode of the second chip is electrically connected to the AC connection terminal, and the negative power electrode of the second chip is electrically connected to the negative terminal.

[0010] A control substrate is positioned directly above two chips. A first bridge connector is provided on one side of the control substrate. The negative power electrode of the first chip is electrically connected to the AC connection terminal through the first bridge connector. Multiple gate connectors are provided on the other side of the control substrate. The gates of the first chip and the second chip are electrically connected to the gate connectors respectively.

[0011] Furthermore, the negative terminal is fixed on the side of the control substrate away from the second chip.

[0012] Furthermore, a second bridge connection piece is fixed on the control substrate, the negative power electrode of the second chip is connected to one side of the second bridge connection piece, and the negative terminal is connected to the other side of the second bridge connection piece.

[0013] Furthermore, at least a portion of the gates of the first chip and the second chip are located outside the projection area covered by the control substrate.

[0014] Furthermore, the packaging structure also includes an AC terminal connector fixed on the main substrate. The positive power electrode of the second chip is electrically connected to the AC connection terminal through the AC terminal connector. The two ends of the first bridge connector are respectively fixed to one end of two connection pads. The other end of one connection pad is connected to the negative power terminal of the first chip, and the other end of the other connection pad is connected to the AC terminal connector.

[0015] Furthermore, a third connection pad is provided between the negative power electrode of the second chip and the control substrate, and the negative power electrode of the second chip is electrically connected to the negative terminal through the third connection pad.

[0016] Furthermore, a plurality of drive circuit connection pieces are provided on one side surface of the control substrate, and the solder windows of the drive circuits of the first chip and / or the second chip are electrically connected to the drive circuit connection pieces respectively.

[0017] Furthermore, the thermistor connection piece is also provided on the main substrate and / or the control substrate.

[0018] Furthermore, the negative terminal includes a fixing part and a connector, and the fixing part is connected to the negative power electrode of the second chip, while a safety space is left between the connector and the positive connection terminal.

[0019] Furthermore, the fixing part extends outward at an angle to form a connecting part, which is connected to the connector as a whole.

[0020] Compared to existing technologies, the compact, low-parasitic-inductance half-bridge package structure described in this invention has the following advantages:

[0021] The present invention adopts a control substrate above the main substrate and a gate connection piece on the control substrate, which reduces the amount of planar space occupied by the gate and shortens the distance between the gate connection piece and the chip gate, thereby shortening the connection distance at the corresponding position and reducing the space occupied by the gate connection position of the package structure.

[0022] By placing the negative terminal on the side of the control substrate away from the second chip, the current passing through the second chip can flow towards the first chip, thus making the current passing through the first chip and the current passing through the second chip in opposite directions. This results in the inductance generated by the two currents being in opposite directions, allowing the two inductors to inhibit each other, thereby reducing the overall parasitic inductance of the package structure.

[0023] AC terminal connecting pieces and two connecting pads are used to electrically connect the negative terminal, the positive power electrode of the second chip, and the negative power electrode of the first chip. At the same time, the control substrate is supported and fixed to avoid changes in the gap between the control substrate and the main substrate during the packaging process, which could lead to incorrect connections at various connection points or between chips.

[0024] By placing the drive circuit connecting piece on the control substrate, compared with the existing method of laying each pin flat, the drive circuit connecting piece avoids occupying more space, and at the same time shortens the gap between the drive circuit connecting piece and the chip solder window to be connected. This facilitates connection, reduces the footprint of the package, and reduces the inductance that is prone to occur in long electrical circuits.

[0025] An inclined connection part is provided on the negative terminal to ensure sufficient safety space between the connector and the positive terminal, thus preventing short circuits caused by electrical connection between the positive and negative terminals during use. Attached Figure Description

[0026] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0027] Figure 1 This is a schematic diagram of the overall packaging structure;

[0028] Figure 2 A schematic diagram showing the connection between the lower surface of the control substrate and the two chips;

[0029] Figure 3 A schematic diagram showing the wire bonding between the control substrate and the two chips;

[0030] Figure 4 This is a schematic diagram of the current flow in the package structure after the first chip is turned on.

[0031] Figure 5 This is a schematic diagram of the current flow in the package structure after the second chip is turned on.

[0032] Figure 6 This is a schematic diagram of the negative extremum structure.

[0033] Explanation of reference numerals in the attached figures:

[0034] 1-Main substrate; 11-Positive terminal connector; 12-AC terminal connector; 13-First chip; 14-Second chip; 15-Thermistor connector; 2-Control substrate; 21-First bridge connector; 22-Second bridge connector; 23-Gate connector; 24-Drive circuit connector; 24a-Kelvin source connector; 24b-Kelvin drain connector; 3-Positive terminal; 4-AC terminal; 5-Negative terminal; 51-Fixing part; 52-Connecting part; 53-Connector; 6-First connecting pad; 7-Second connecting pad; 8-Third connecting pad. Detailed Implementation

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0036] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] like Figures 1-5 As shown, a compact, low parasitic inductance half-bridge package structure includes a main substrate 1 and a control substrate 2. The control substrate 2 is positioned directly above the main substrate 1. Optionally, in this embodiment, the main substrate 1 and the control substrate 2 are both insulating ceramics. In other embodiments, the main substrate 1 and the control substrate 2 can also be made of other insulating materials. A positive terminal connecting piece 11 and an AC terminal connecting piece 12 are respectively fixed at both ends of the main substrate 1. The positive terminal connecting piece 11 is connected to a positive terminal 3, and the AC terminal connecting piece 12 is connected to an AC terminal 4, such that the positive terminal 3 and the AC terminal 4 are respectively positioned at both ends of the main substrate 1. Optionally, the connection between the terminal and the connecting piece can be achieved by embedding, bonding, or other connection methods. The connecting piece can be fixed to the main substrate 1 by electroplating or other methods. More specifically, in this embodiment, the surface of the main substrate 1 is provided with a copper layer, and each connecting piece is formed by etching from the copper layer.

[0040] A first chip 13 and a second chip 14 are fixed on the main substrate 1. The first chip 13 and the second chip 14 are arranged along the direction from the positive terminal 3 to the AC terminal 4. The positive power terminal of the first chip 13 is electrically connected to the positive terminal 3, and the positive power electrode of the second chip 14 is electrically connected to the AC terminal 4. In this embodiment, the first chip 13 is fixed on the positive terminal connecting piece 11, and its positive power electrode is electrically connected to the positive terminal 3 through the positive terminal connecting piece 11; the second chip 14 is fixed on the AC terminal connecting piece, and its positive power electrode is electrically connected to the AC terminal 4 through the AC terminal connecting piece.

[0041] The control substrate 2 is positioned directly above the two chips. A first bridging connector 21 and a second bridging connector 22 are provided on one side surface of the control substrate 2. One end of the first bridging connector 21 is positioned directly above the negative power electrode of the first chip 13, and the other end is positioned directly above the AC terminal connector 12. The negative power electrode of the first chip 13 and the AC terminal connector 12 are electrically connected to the first bridging connector 21 via a first connecting pad 6 and a second connecting pad 7, respectively. This allows the negative power electrode of the first chip 13 to be electrically connected to the AC terminal 4. Simultaneously, the first connecting pad 6 and the second connecting pad 7 support and fix the control substrate 2, preventing misalignment of the control substrate 2 during the packaging process, which could lead to open circuits or accidental contact at other connection nodes connected via wire bonding, causing open circuits or short circuits. One side of the second bridge connecting piece 22 is positioned directly above the negative power electrode of the second chip 14. The negative power electrode of the second chip 14 is electrically connected to the second bridge connecting piece 22 via the third connecting pad 8. The other side of the second bridge connecting piece 22 is connected to a negative terminal 5, and the negative terminal 5 is positioned on the side of the control substrate 2 away from the second chip 14. More specifically, the negative terminal 5 is positioned above the positive connecting terminal 3.

[0042] During operation, when the first chip 13 is turned on, the current flows sequentially through the positive terminal 3, the positive terminal connecting piece 11, the first chip 13, the first connecting pad 6, the first bridge connecting piece 21, the second connecting pad 7, the AC terminal connecting piece 12, and the AC terminal 4. When the second chip 14 is turned on, the current flows sequentially through the AC terminal 4, the AC terminal connecting piece 12, the second chip 14, the third connecting pad 8, the second bridge connecting piece 22, and the negative terminal 5. This causes the two currents within the packaged device to flow in opposite directions, thereby forming two opposite inductors. This mutual suppression of inductors within the packaged device reduces the parasitic inductance generated within the packaged device, making the chip and circuit within the package work more stably.

[0043] In this embodiment, the second bridge connecting piece 22 is U-shaped, the first bridge connecting piece 21 is placed inside the opening of the second bridge connecting piece 22, the third connecting pad 8 is connected to the closed side of the U-shape, and the open side of the U-shape is connected to the negative pressure terminal, thereby making the current spacing inside the package smaller, making the suppression effect of the inductance generated by the two currents stronger, and further reducing the overall inductance of the device.

[0044] The negative power electrode of the second chip 14 is electrically connected to the AC connection terminal 4 through the second bridge connecting piece 22. Multiple gate connecting pieces 23 are provided on the other side surface of the control substrate 2. The gates of the first chip 13 and the second chip 14 are electrically connected to the gate connecting pieces 23 respectively.

[0045] On the other side surface of the control substrate 2, a plurality of gate connection pieces 23 and a plurality of drive circuit connection pieces 24 are fixedly provided. The gate bonding windows of the first chip 13 and the second chip 14 can be electrically connected to the gate connection pieces 23 of the control substrate 2 by wire bonding. In this embodiment, the first bridge connection piece 21 and the second bridge connection piece 22 are respectively placed on the lower surface of the substrate, corresponding to the main substrate 1; the gate connection pieces 23 and the drive circuit connection pieces 24 are respectively placed on the upper surface of the substrate, so that the connection pieces can be partially or completely exposed outside the package, which facilitates the connection of external circuits. At least part of the gates of the first chip 13 and the second chip 14 are placed outside the projection area covered by the control substrate 2, so that during the wire bonding process, the gate bonding windows of the chips exposed outside the projection area of ​​the control substrate 2 can be directly wire bonded to the gate connection pieces 23 of the control substrate 2. Similarly, the corresponding bonding windows of the drive circuits of the chips are also partially exposed outside the projection range of the control substrate 2.

[0046] In this embodiment, at least one edge of the drive circuit connecting piece 24 and the gate connecting piece 23 is close to the edge of the control substrate 2, so as to reduce the curvature of the wire during the wire bonding process, and at the same time avoid the wire from accidentally touching other connecting pieces after crossing part of the connecting piece during the encapsulation process.

[0047] In this embodiment, the drive circuit connection pieces 24 are Kelvin source connection piece 24a and Kelvin drain connection piece 24b, respectively. The Kelvin source solder window and Kelvin drain solder window of the chip can be electrically connected to their respective connection pieces by wire bonding. In other embodiments, the drive circuit can also be a gate driver connection piece, etc.

[0048] In this embodiment, the main substrate 1 and / or the control substrate 2 are also provided with a thermistor connecting piece 15. In use, the thermistor can be fixed on the thermistor connecting piece 15 to detect the temperature inside the packaged device.

[0049] Combination Figure 6 As shown, the negative terminal 5 includes a fixing part 51 and a connector 53. The fixing part 51 is connected to the negative power electrode of the second chip 14. A safety space is left between the connector 53 and the positive terminal 3. Optionally, the fixing part 51 extends outward at an angle to form a connecting part 52. The connecting part 52 and the connector 53 are connected as a whole, so that the connector 53 can maintain sufficient safety space with the positive terminal 3, avoiding short circuit caused by electrical connection between the positive terminal 3 and the negative terminal 5 during use.

[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A compact half-bridge package structure with low parasitic inductance, characterized in that: include The main substrate has a positive connection terminal at one end and an AC connection terminal at the other end. A first chip and a second chip are fixed between the positive connection terminal and the AC connection terminal. The positive power electrode of the first chip is electrically connected to the positive connection terminal, the positive power electrode of the second chip is electrically connected to the AC connection terminal, and the negative power electrode of the second chip is electrically connected to the negative terminal. A control substrate is positioned directly above two chips. A first bridge connecting piece is provided on one side surface of the control substrate. The negative power electrode of the first chip is electrically connected to the AC connection terminal through the first bridge connecting piece. Multiple gate connecting pieces are provided on the other side surface of the control substrate. The gates of the first chip and the second chip are electrically connected to the gate connecting pieces respectively. The negative terminal is fixed on the side of the control substrate away from the second chip; At least a portion of the gates of the first chip and the second chip are located outside the projection of the area covered by the control substrate.

2. The compact, low parasitic inductance half-bridge package structure according to claim 1, characterized in that: A second bridge connector is fixed on the control substrate. The negative power electrode of the second chip is connected to one side of the second bridge connector, and the negative terminal is connected to the other side of the second bridge connector.

3. The compact, low parasitic inductance half-bridge package structure according to claim 1, characterized in that: It also includes a negative terminal connector fixed on the main substrate, the positive power electrode of the second chip is electrically connected to the negative terminal through the negative terminal connector; the two ends of the first bridge connector are respectively fixed to one end of two connecting pads, the other end of one connecting pad is connected to the negative power terminal of the first chip, and the other end of the other connecting pad is connected to the negative terminal connector.

4. A compact, low-parasitic-inductance half-bridge package structure according to claim 1 or 3, characterized in that: A third connection pad is provided between the negative power electrode of the second chip and the control substrate, and the negative power electrode of the second chip is electrically connected to the negative terminal through the third connection pad.

5. The compact, low parasitic inductance half-bridge package structure according to claim 1, characterized in that: The control substrate has multiple drive circuit connection pieces on one side surface, and the solder windows of the drive circuits of the first chip and / or the second chip are electrically connected to the drive circuit connection pieces respectively.

6. The compact, low parasitic inductance half-bridge package structure according to claim 1, characterized in that: The thermistor connection piece is also provided on the main substrate and / or the control substrate.

7. A compact, low-parasitic-inductance half-bridge package structure according to claim 1 or 2, characterized in that: The negative terminal includes a fixing part and a connector, and the fixing part is connected to the negative power electrode of the second chip, while a safety space is left between the connector and the positive terminal.

8. A compact, low-parasitic-inductance half-bridge package structure according to claim 7, characterized in that: The fixing part extends outward at an angle to form a connecting part, which is connected to the connector as a whole.

Images