Parallel output synchronization control method and system for FPGA

Abstract

The application relates to a parallel output synchronization control method and system for an FPGA, which is composed of the FPGA and a cascaded shift register, and the FPGA is internally integrated with a TVG code value generation module and a shift control state machine. The method comprises the following steps: calculating gain code values according to an action distance and a signal type by using corresponding TVG formulas; serially shifting the code values into the shift register through the state machine; and finally realizing strict synchronization of multi-channel parallel output through a unified STCP latching signal. The application realizes significant saving of pin resources by only occupying three general I / O pins of the FPGA, meanwhile, microsecond-level high-speed updating and accurate multi-channel synchronization control are achieved, and the technical difficulties of high cost, large delay and mismatch among channels of the traditional scheme are effectively solved.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and in particular to a parallel output synchronization control method and system for FPGA. Background Technology

[0002] Field-programmable gate arrays (FPGAs) are widely used in real-time signal processing systems, such as ultrasonic imaging, underwater acoustic detection, and phased array radar, due to their high flexibility and powerful parallel processing capabilities. In these systems, since the signal attenuates with propagation distance, time-varying gain (TVG) technology is typically used to dynamically amplify the echo signal in a depth-dependent manner to ensure the consistency of signal amplitude.

[0003] As system functions become increasingly complex, higher demands are placed on the number of I / O pins on FPGAs. Taking a 32-channel underwater acoustic side-scan sonar system as an example, it needs to connect multiple ADC chips, storage devices, and communication interfaces (such as JTAG, USB, and Ethernet), already consuming a significant amount of I / O resources. If a parallel interface is also needed for multi-channel TVG code value output, the required number of I / O pins (N bits × M channels) will far exceed the resource limits of low-to-mid-range FPGAs, forming a significant "pin bottleneck."

[0004] Currently, traditional solutions to the problem of insufficient pin resources have the following limitations:

[0005] Using FPGA chips with high pin counts: This approach directly leads to a sharp increase in hardware costs, which is unacceptable in mass-produced products where cost-effectiveness is a key factor.

[0006] Using I 2 Multi-channel digital-to-analog converters (DACs) with C or SPI interfaces: These serial communication protocols inherently have high communication overhead and low speed, and their update delay is usually on the order of tens of microseconds, making it difficult to meet the stringent real-time requirements of TVG control.

[0007] I / O expansion using general-purpose shift registers: Existing applications are mostly concentrated in scenarios such as LED display drivers where synchronization and timing accuracy requirements are not high. Their control logic is simple, lacking timing optimization for the critical requirements of high synchronization, low latency, and glitch-free output necessary for TVG code values. Specifically, when driving multiple cascaded shift registers, improper latch signal control can easily lead to asynchronous output updates across channels due to slight differences in latch timing, introducing gain mismatch between channels and ultimately producing artifacts in the imaging results or causing a decrease in ranging accuracy.

[0008] Therefore, there is an urgent need in this field for a low-cost solution that can significantly save FPGA pin resources while achieving high-speed, high-synchronization TVG code value output. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention provides a parallel output synchronization control method for FPGAs, comprising:

[0010] Step S1: TVG code value generation; The TVG digital code value is calculated based on the time-varying gain formula according to the system operating distance and signal type.

[0011] Step S2: Timing control signal generation; The serial data signal (DS), shift clock signal (SHCP), and storage register clock signal (STCP) are generated by the shift control state machine in the FPGA;

[0012] Step S3: Data shifting; Under the control of the shift clock signal (SHCP), the TVG digital code value is shifted serially into the cascaded shift registers.

[0013] Step S4: Synchronous latching; After all data bits have been shifted in, the shift control state machine generates a rising edge of the storage register clock signal (STCP) to simultaneously latch the data in all cascaded shift registers to their parallel output terminals, thereby achieving strict synchronization of multi-channel output.

[0014] In one embodiment of the present invention, the TVG code value generation in step S1, for a linear frequency modulated pulse signal, is based on the time-varying gain formula as follows:

[0015] TVG=20log(r)+2αr+MGC+Bias

[0016] Where r is the operating distance, α is the attenuation coefficient, MGC is the variable gain, and Bias is the bias gain.

[0017] In one embodiment of the present invention, the TVG code value generation in step S1, for a continuous wave signal, is based on the time-varying gain formula as follows:

[0018] TVG=20log(r)+2αr

[0019] Where r is the effective distance and α is the attenuation coefficient.

[0020] In one embodiment of the present invention, before the data shifting in step S3, the method further includes:

[0021] Data preparation and judgment steps: Read the current TVG code value from the block memory and compare it with the value of the previous cycle. Start the shift process only when the value changes.

[0022] This invention also provides an FPGA parallel output synchronization control system, specifically used to implement the parallel output synchronization control method as described above, including:

[0023] The field-programmable gate array integrates: a TVG code value generation module, which calculates the TVG digital code value based on the time-varying gain formula according to the system operating distance and signal type; and a shift control state machine, which generates the timing control of serial data signals, shift clock signals, and storage register clock signals.

[0024] At least one shift register chip, whose serial data input, shift register clock, and storage register clock are respectively connected to the corresponding general-purpose I / O pins of the FPGA.

[0025] In one embodiment of the present invention, the TVG code value generation module is configured to perform one of the following calculations:

[0026] For a linear frequency modulated pulse signal, the code value is generated according to the formula TVG=20log(r)+2αr+MGC+Bias;

[0027] For continuous wave signals, the code value is generated according to the formula TVG=20log(r)+2αr.

[0028] In one embodiment of the present invention, two or more cascaded shift register chips are included, and all cascaded chips share the same set of shift clock signals and storage register clock signals.

[0029] In one embodiment of the present invention, a decoupling capacitor is connected in parallel between the power supply pin of the shift register chip and ground, and the output enable pin is configured to a constant low level.

[0030] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The parallel output synchronization control scheme of the present invention reduces the original "N-bit × M-channel" parallel I / O pins to a fixed few control pins (DS, SHCP, STCP), thereby enabling multi-channel control using low-cost mid-to-low-end FPGAs, significantly reducing system hardware costs and PCB routing complexity. Simultaneously, by utilizing high-speed CMOS shift register chips such as the 74HC595DMT and applying a high-frequency clock drive (e.g., 25MHz) at the FPGA end, 8-bit data shifting can be completed within 0.32 microseconds, fully meeting the stringent requirements of TVG and other applications for microsecond-level real-time updates, overcoming the bottleneck of high latency in traditional serial DAC schemes. Furthermore, through the core design of generating a single STCP latch signal uniformly by the FPGA, the problem of asynchronous updates between channels caused by timing deviations of multiple latch signals is fundamentally eliminated. This mechanism can effectively suppress image artifacts or ranging errors caused by gain mismatch, significantly improving the overall accuracy and reliability of the imaging or detection system. Attached Figure Description

[0031] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0032] Figure 1 This is an overall structural block diagram of the FPGA parallel output synchronization control system of the present invention;

[0033] Figure 2 This is a schematic diagram of the hardware circuit of the parallel output synchronization control system in this invention;

[0034] Figure 3 This is a schematic diagram of the internal structure of the 74HC595DMT chip described in this invention;

[0035] Figure 4 This is a flowchart of the TVG code value generation module described in this invention;

[0036] Figure 5 This is a flowchart of the shift control state machine described in this invention.

[0037] Figure 6 This is the simulation timing diagram in this invention. Detailed Implementation

[0038] Example 1

[0039] like Figure 1 As shown, this embodiment provides an FPGA parallel output synchronous control system. The system mainly consists of two parts: an FPGA core processing unit and a peripheral 74HC595DMT shift register expansion circuit.

[0040] The FPGA integrates two core functional modules: a TVG code value generation module and a shift control state machine. The TVG code value generation module is responsible for calculating the time-varying gain value in real time based on the current operating distance; the shift control state machine is responsible for implementing precise timing control, converting parallel TVG code values ​​into a serial data stream, and generating the corresponding control timing.

[0041] In the peripheral circuitry, two 74HC595DMT shift register chips were cascaded for expansion. The FPGA connects to the shift register chips via a limited number of general-purpose I / O pins, mainly including:

[0042] Serial data output (DS); shift register clock (SHCP); storage register clock (STCP).

[0043] The core of the solution in this embodiment is to synchronously control all cascaded shift register chips through a unified STCP latch signal, ensuring that the TVG code values ​​of multiple channels are updated on the same clock edge, thus fundamentally eliminating the channel gain mismatch problem caused by latch timing differences in traditional solutions.

[0044] Specifically, see Figure 2 The hardware schematic shown in this embodiment uses two cascaded 74HC595DMT chips to achieve 16-bit TVG code value output. The specific pin connections are as follows:

[0045] The serial data input (DS, pin 14) of the first 74HC595DMT chip (U10) receives the PGA_L100K_DS signal from the FPGA; the serial data input (DS, pin 14) of the second chip (U8) receives the PGA_R100K_DS signal. The shift register clock input (SHCP, pin 11) of both chips is connected to the PGA_100K_SHCP signal of the FPGA, and the storage register clock input (STCP, pin 12) is connected to the PGA_100K_STCP signal.

[0046] Furthermore, to enable cascaded data transmission, the serial output (Q7', pin 9) of the first chip is directly connected to the serial data input (DS, pin 14) of the second chip. This cascading method allows the FPGA to achieve 16-bit parallel output expansion with only 3 general-purpose I / O pins.

[0047] In addition, to ensure the stability of the system under high-speed operation, this embodiment adopts several reliability design measures:

[0048] In terms of power supply design, the VCC pin (pin 16) of all 74HC595DMT chips is connected to a 3.3V power supply (VDD_3V3_BANK). A 100nF ceramic decoupling capacitor (C30, C46) is connected in parallel between the VCC and GND pins of each chip. These capacitors are placed close to the chip's power supply pins to effectively suppress power supply noise generated during high-speed switching.

[0049] In terms of pin configuration, the output enable pin (OE, pin 13) is pulled up to a low level through 10kΩ resistors (R61, R85) to ensure that the output is always enabled; the main reset pin (MR, pin 10) is pulled down to ground through a 10kΩ resistor to prevent accidental reset due to the pin being floating.

[0050] Furthermore, such as Figure 3 The main internal structure of the 74HC595DMT chip is shown. The chip contains three main parts: an 8-bit serial input shift register, an 8-bit parallel output memory register, and a tri-state output buffer.

[0051] During operation, serial data is shifted bit by bit into the internal shift register via the DS pin on the rising edge of the SHCP clock signal. Once all 8 bits of data have been shifted in, the data in the shift register is latched into the output storage register in parallel on the rising edge of the STCP signal. Because the output enable OE remains active low, the data in the storage register is immediately output in parallel via pins Q0-Q7.

[0052] Example 2

[0053] like Figure 4 , Figure 5 As shown, this embodiment provides a parallel output synchronization control method for FPGA; and the specific TVG code value generation module adopts different time-varying gain calculation formulas according to the sonar system's working mode and signal characteristics.

[0054] For continuous wave (CW) signals, the formula is: TVG=20log(r)+2αr.

[0055] For a linear frequency modulated pulse (LFM) signal, the formula is: TVG=20log(r)+2αr+MGC+Bias.

[0056] Where r represents the effective distance in meters; α is the attenuation coefficient in dB / m; MGC is the variable gain, configured by the host computer, with an adjustment range of -50 to 50; and Bias is the bias gain, used for system calibration.

[0057] In actual implementation, the PS terminal first pre-calculates the TVG code value table for the entire operating range based on system parameters, and then stores these code values ​​in the block memory (BRAM) of the PL terminal. The PL terminal reads the TVG code value corresponding to the current distance from the BRAM at 1ms intervals for subsequent shift output.

[0058] Specifically, such as Figure 5 The detailed workflow of the shift control state machine is shown; this state machine is responsible for converting parallel TVG code values ​​into a serial data stream and generating precise timing control signals.

[0059] The state machine's workflow begins in the IDLE state. Every 1ms cycle, the state machine reads a 16-bit TVG code value from the BRAM and compares it with the value stored in the previous cycle. If a change in value is detected, the new TVG code value is latched when the load_trig signal is high, and the shift process begins.

[0060] During the shift process, the state machine generates eight complete SHCP clock signals, each clock cycle consisting of a 40ns high level and a 40ns low level. At the rising edge of each SHCP, one bit of data is shifted into the shift register via the DS pin. After the 8-bit data shift is complete, the state machine generates a 40ns wide STCP high-level pulse. The rising edge of this pulse simultaneously applies to all cascaded 74HC595DMT chips, synchronously updating the data in the shift registers to the parallel output.

[0061] Furthermore, to verify the correctness of the design, a functional simulation of the shift control state machine was performed on the parallel output synchronization control method described in this embodiment. During the simulation, the test input value was set to 0xA5 (binary 10100101), and the system clock frequency was 100MHz. The timing diagram obtained from the simulation is shown below. Figure 6 As shown.

[0062] The simulation waveform clearly shows that at each rising edge of the SHCP clock, the data bits on the DS pin are correctly sampled and shifted into the shift register; after all 8 bits of data have been shifted in, the STCP signal generates a positive pulse to latch the data to the output; the entire 16-bit data shifting process takes 1.28μs, which fully meets the TVG system's requirement for microsecond-level update speed.

[0063] On a real hardware circuit board, the generated SHCP and STCP signals were measured using an oscilloscope. The test results showed that the actual generated signal waveforms were completely consistent with the design expectations: the SHCP clock frequency was stable at 12.5MHz, the STCP signal was accurately generated after the SHCP clock sequence ended, the pulse width strictly met the design requirement of 40ns, the signal edges were clear, and there were no obvious ringing or overshoot phenomena, indicating good signal integrity.

[0064] Through comparative testing with traditional solutions, the technical advantages of this invention have been fully verified: compared with traditional solutions... 2 The update latency of the C DAC solution is 20-50μs. This invention reduces the update latency to 1.28μs, an improvement of 15-39 times; the synchronization error is reduced from 100-500ns in the traditional solution to less than 1ns, an improvement of 100-500 times; at the same time, it significantly reduces the number of FPGA pins occupied and reduces system cost.

[0065] Furthermore, based on the core idea of ​​this invention, various alternative implementation schemes can be derived. For example, in applications requiring larger-scale I / O expansion, modular expansion can be achieved by adding chip select signals, allowing multiple cascaded groups to be independently addressed and controlled. Additionally, adaptive clock frequency control can be implemented, dynamically adjusting the SHCP clock frequency according to the real-time needs of the system, increasing the frequency when high-speed updates are required, and decreasing the frequency in low-power mode, achieving the optimal balance between performance and power consumption.

[0066] Through the above implementation methods, this invention successfully achieves efficient expansion of FPGA pins and meets the stringent requirements of TVG systems for high-speed, synchronous, and glitch-free output. Those skilled in the art can make appropriate adjustments to the specific parameters and configurations based on the above description, and all such adjustments should be included within the scope of protection of this invention.

[0067] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A parallel output synchronization control method for FPGA, characterized in that, The steps include the following: Step S1: TVG code value generation; Based on the system operating distance and signal type, the TVG digital code value is calculated using the time-varying gain formula; specifically, the TVG code value generation involves performing one of the following calculations: For a linear frequency modulated pulse signal, the time-varying gain formula used is: TVG = 20log(r) + 2αr + MGC + Bias Where r is the effective distance, α is the attenuation coefficient, MGC is the variable gain, and Bias is the bias gain; For continuous wave signals, the applicable time-varying gain formula is: TVG = 20log(r) + 2αr Where r is the effective distance and α is the attenuation coefficient; Step S2: Timing control signal generation; the serial data signal, shift clock signal, and storage register clock signal are generated by the shift control state machine in the FPGA; Step S3: Data shifting; Under the control of the shift clock signal, the TVG digital code value is shifted serially into the cascaded shift registers. Step S4: Synchronous latching; After all data bits have been shifted in, the shift control state machine generates a rising edge of the clock signal of the storage register, and latches the data in all cascaded shift registers to their parallel output terminals simultaneously, so as to achieve strict synchronization of multi-channel output.

2. The parallel output synchronization control method according to claim 1, characterized in that: Before the data shifting in step S3, the following is also included: Data preparation and judgment steps: Read the current TVG code value from the block memory and compare it with the value of the previous cycle. Start the shift process only when the value changes.

3. An FPGA parallel output synchronization control system, specifically used to implement the parallel output synchronization control method as described in any one of claims 1 to 2, characterized in that, include: The field-programmable gate array integrates a TVG code value generation module, which is used to calculate the TVG digital code value based on the time-varying gain formula according to the system operating distance and signal type. A shift control state machine is used for timing control of the generation of serial data signals, shift clock signals, and storage register clock signals; the TVG code value generation module is configured to perform one of the following calculations: For a linear frequency modulated pulse signal, the code value is generated according to the formula TVG=20log(r)+2αr+MGC+Bias; For continuous wave signals, code values ​​are generated according to the formula TVG=20log(r)+2αr; At least one shift register chip, whose serial data input, shift register clock, and storage register clock are respectively connected to the corresponding general-purpose I / O pins of the FPGA.

4. The parallel output synchronization control system according to claim 3, characterized in that: It includes two or more cascaded shift register chips, with all cascaded chips sharing the same set of shift clock signals and storage register clock signals.

5. The parallel output synchronization control system according to claim 3, characterized in that: Furthermore, a decoupling capacitor is connected in parallel between the power supply pin and ground of the shift register chip, and the output enable pin is configured to a constant low level.

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