Solid state disk energy consumption optimization method and device, electronic equipment and storage medium

Abstract

The application provides a solid state disk energy consumption optimization method and device, electronic equipment and storage medium, the method comprises the following steps: if the first data transmission rate of the PCIe link does not meet the transmission rate requirement, the transmission bandwidth of the PCIe link is throttled; based on the link transmission state of the throttled PCIe link, the cache space of the solid state disk is layered to obtain the layered cache structure; based on the data storage situation of each cache layer in the layered cache structure and the task execution situation of the solid state disk, the migratable tasks in each cache layer are determined, the migratable tasks in each cache layer are migrated to the target cache area to obtain the cache layout after task migration; if the second data transmission rate of the throttled PCIe link meets the transmission rate requirement, the working mode of each component in the solid state disk is adjusted based on the second data transmission rate and the cache layout. The application optimizes the energy consumption of the solid state disk and improves the read-write performance and service life.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) technology, and in particular to a method, apparatus, electronic device, and storage medium for optimizing SSD power consumption. Background Technology

[0002] With the rapid development of information technology, solid-state drives (SSDs) have been widely used in data storage due to their high-speed read / write and low-latency characteristics. However, as the capacity and performance of SSDs continue to improve, their energy consumption has become increasingly prominent. Excessive energy consumption not only increases the operating costs of data centers but also brings a series of problems such as heat dissipation, limiting the application of SSDs in more scenarios.

[0003] Currently, the most common method for optimizing solid-state drive (SSD) power consumption is to dynamically adjust the SSD's operating frequency and voltage to reduce power consumption. While this can reduce SSD power consumption to some extent, the frequency and voltage adjustment method is too coarse and cannot accurately adapt to the SSD's power consumption requirements under different workloads. As a result, the power consumption optimization effect is not good in some complex working scenarios, and frequent frequency and voltage adjustments may even affect the SSD's read and write performance and lifespan. Summary of the Invention

[0004] This invention provides a method, apparatus, electronic device, and storage medium for optimizing solid-state drive (SSD) power consumption, thereby achieving efficient optimization of SSD power consumption in complex working scenarios and improving read / write performance and lifespan.

[0005] In a first aspect, the present invention provides a method for optimizing the power consumption of solid-state drives, comprising:

[0006] If the first data transfer rate of the PCIe link between the solid-state drive and the host is found to be insufficient to meet the transfer rate requirements, the transfer bandwidth of the PCIe link is throttled to obtain the throttled PCIe link.

[0007] Based on the link transmission status of the PCIe link after throttling, the cache space of the solid-state drive is layered to obtain a layered cache structure.

[0008] Based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, the transferable tasks in each cache layer are determined, and the transferable tasks of each cache layer are migrated to the target cache area to obtain the cache layout after task migration.

[0009] If the second data transfer rate of the PCIe link after the throttling is detected to meet the transfer rate requirement, the working mode of each component in the solid-state drive is adjusted based on the second data transfer rate and the cache layout to reduce the power consumption of the solid-state drive.

[0010] In a second aspect, the present invention also provides a solid-state drive (SSD) power consumption optimization device, applied to the SSD power consumption optimization method as described in the first aspect; the SSD power consumption optimization device includes:

[0011] The link throttling module is used to throttle the transmission bandwidth of the PCIe link if the first data transfer rate of the PCIe link between the solid-state drive and the host is found to be insufficient to meet the transmission rate requirements, so as to obtain the throttled PCIe link.

[0012] The cache space tiering module is used to perform tiering operations on the cache space of the solid-state drive based on the link transmission status of the PCIe link after throttling, so as to obtain a tiered cache structure.

[0013] The task migration module is used to determine the migrateable tasks in each cache layer based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, and migrate the migrateable tasks of each cache layer to the target cache area to obtain the cache layout after task migration.

[0014] The working mode adjustment module is used to adjust the working mode of each component in the solid-state drive based on the second data transmission rate and the cache layout if the second data transmission rate of the PCIe link after the throttling is detected to meet the transmission rate requirement, so as to reduce the power consumption of the solid-state drive.

[0015] Thirdly, the present invention also provides an electronic device, comprising: a memory for storing computer software programs; and a processor for reading and executing the computer software programs, thereby realizing the solid-state drive energy consumption optimization method described above.

[0016] Fourthly, the present invention also provides a non-transitory computer-readable storage medium storing a computer software program, which, when executed by a processor, implements the solid-state drive power consumption optimization method described above.

[0017] Fifthly, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the solid-state drive power consumption optimization method described above.

[0018] The solid-state drive (SSD) energy consumption optimization method provided in this invention monitors the real-time data transmission volume of the PCIe link and performs throttling operations to obtain the transmission status of the PCIe link after throttling, reducing energy consumption during data transmission. Based on this result, the cache space is intelligently layered to store data rationally, improving cache utilization efficiency and reducing unnecessary cache access energy consumption. Based on the layered cache structure, the method monitors and obtains information on migrateable idle tasks, and migrates the idle tasks to obtain a new storage layout, further optimizing the data storage and task execution methods within the SSD and reducing energy consumption in the storage area. Based on the storage layout after task migration, the PCIe link transmission status is optimized again to continuously reduce data transmission energy consumption. Finally, based on the optimized PCIe link transmission status and the storage layout after task migration, the working mode of each component of the SSD is dynamically adjusted, reducing the overall energy consumption of the SSD. This achieves efficient optimization of SSD energy consumption in complex working scenarios and improves read / write performance and lifespan. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the solid-state drive power consumption optimization method provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the solid-state drive power consumption optimization device provided in an embodiment of the present invention;

[0021] Figure 3 An embodiment diagram of the electronic device provided in this invention;

[0022] Figure 4 An embodiment diagram of a computer-readable storage medium provided in accordance with the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0025] In the description of this invention, the term "for example" is used to mean "used as an example, illustration, or description." Any embodiment described as "for example" in this invention is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0026] Optional, see below Figure 1 , Figure 1 This is a flowchart illustrating the solid-state drive (SSD) power consumption optimization method provided by the present invention. In this embodiment, the executing entity of the SSD power consumption optimization method is an power consumption optimization device. Therefore, the SSD power consumption optimization method includes:

[0027] Step 10: If the first data transfer rate of the PCIe link between the solid-state drive and the host is found to be insufficient, the transmission bandwidth of the PCIe link is throttled to obtain the throttled PCIe link.

[0028] Optionally, the power optimization device continuously monitors the first data transfer rate of the PCIe link (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) between the solid-state drive and the host. The first data transfer rate refers to the actual data transmission speed of the PCIe link under the current operating conditions, typically measured in bytes per second (B / s) or megabytes per second (MB / s). The power optimization device pre-sets the transfer rate requirements, determined based on factors such as system performance needs and power consumption limitations. When the first data transfer rate is found to be insufficient, the power optimization device throttles the PCIe link's bandwidth. This throttling essentially balances performance and power consumption by reducing the PCIe link's data transfer capacity. This can be achieved by adjusting the PCIe link's operating mode, such as switching from a high-bandwidth mode to a low-bandwidth mode, or by setting flow control parameters to limit the amount of data passing through the PCIe link per unit time. The throttled PCIe link, with its reduced data transfer capacity, results in a corresponding reduction in power consumption.

[0029] In one embodiment, the solid-state drive (SSD) is connected to the host via a PCIe 3.0 x4 link. The preset transfer rate requirement is 1000 MB / s. At a certain moment, the first data transfer rate is detected to be only 800 MB / s, which is lower than the required transfer rate. At this time, the PCIe link is switched from the high-speed operating mode of PCIe 3.0 x4 to PCIe 2.0 x4 mode. In this mode, the theoretical maximum transfer rate is reduced, and power saving is achieved by reducing the data transfer capacity of the link. After the power saving operation, the PCIe link is obtained. Although its transfer rate is reduced, its power consumption is also reduced, and the transfer rate can still meet the needs of some application scenarios with low performance requirements.

[0030] Step 20: Based on the link transmission status of the PCIe link after throttling, the cache space of the solid-state drive is layered to obtain the layered cache structure.

[0031] Furthermore, based on the link transmission status of the PCIe link after throttling, the energy optimization device performs a layered operation on the cache space of the solid-state drive (SSD) to obtain a layered cache structure, as described in steps 201 to 204. The link transmission status includes information such as the current transmission rate and transmission stability of the link. Cache space layering divides the SSD's cache area into different layers according to certain rules. Each layer has different characteristics and uses. This embodiment of the invention enables the SSD to manage cached data more efficiently through layering, improving data access efficiency and thus reducing energy consumption.

[0032] Step 30: Based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, determine the transferable tasks in each cache layer, and migrate the transferable tasks of each cache layer to the target cache area to obtain the cache layout after task migration.

[0033] Furthermore, the energy optimization device determines the migrateable tasks in each cache layer based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive. The data storage status includes information such as the amount of data already stored in each cache layer and its data type. The task execution status includes the priority of the currently executing task and its requirements for cache resources. Migrantable tasks are those that can be migrated from the current cache layer to other cache layers without affecting system performance or task execution results. Therefore, after determining the migrateable tasks, the energy optimization device migrates the migrateable tasks of each cache layer to the target cache area. The target cache area can be a pre-defined cache region based on system resource conditions and task characteristics, or it can be a cache area determined after calculation to be the most suitable for storing these migrateable tasks. Through task migration, a new cache layout is obtained, allowing for a more rational allocation of cache resources and further improving the performance and energy efficiency of the solid-state drive.

[0034] Continuing with the above embodiments, after obtaining the layered cache structure, the energy optimization device analyzes the situation of each cache layer and finds that there is a data backup task in the bottom cache layer with low priority and minimal impact on system performance, while this task consumes a large amount of cache resources; while the higher cache layers have some free space. After evaluation, the data backup task is determined to be a migrated task. The energy optimization device migrates the data backup task to the free area of ​​the higher cache layer, i.e., the target cache area. After the task migration operation, the cache layout after task migration is obtained. At this time, the resources of the bottom cache layer are released, the free space of the higher cache layer is utilized, and the cache resource allocation is more reasonable.

[0035] Step 40: If the second data transfer rate of the PCIe link after throttling is found to meet the transfer rate requirements, then the working mode of each component in the solid-state drive is adjusted based on the second data transfer rate and cache layout to reduce the power consumption of the solid-state drive.

[0036] Furthermore, the energy optimization device continuously monitors the second data transfer rate of the PCIe link after throttling. The second data transfer rate refers to the actual data transfer speed of the PCIe link after the throttling operation in step 10 and the cache space-related operations in steps 20 and 30. When the second data transfer rate is found to meet the transfer rate requirements, the energy optimization device adjusts the operating modes of each component in the solid-state drive (including flash memory chips, controller chips, and cache chips) based on the second data transfer rate and the cache layout (i.e., the cache layout after task migration obtained in step 30). Specifically, this is done as described in steps 401 to 404. The purpose of adjusting the operating modes is to reduce the energy consumption of the solid-state drive while meeting the data transfer requirements.

[0037] This invention monitors the real-time data transmission volume of the PCIe link and performs throttling operations to obtain the transmission status of the PCIe link after throttling, reducing energy consumption during data transmission. Based on this result, the cache space is intelligently layered to store data rationally, improving cache utilization efficiency and reducing unnecessary cache access energy consumption. Based on the layered cache structure, the invention monitors and obtains information on migrateable idle tasks, and migrates these idle tasks to obtain a new storage layout, further optimizing the data storage and task execution methods within the solid-state drive (SSD) and reducing energy consumption in the storage area. Based on the storage layout after task migration, the PCIe link transmission status is further optimized to continuously reduce data transmission energy consumption. Finally, based on the optimized PCIe link transmission status and the storage layout after task migration, the operating modes of each component of the SSD are dynamically adjusted, reducing the overall energy consumption of the SSD. This achieves efficient optimization of SSD energy consumption in complex working scenarios, as well as improving read / write performance and lifespan.

[0038] In one embodiment, steps 201 to 204 include:

[0039] Step 201: Based on the length of the data transmission continuity parameter in the link transmission state, the cache space of the solid-state drive is divided into a continuous transmission cache area and a non-continuous transmission cache area.

[0040] Optionally, the energy optimization device extracts data transmission continuity parameters from the link transmission status of the PCIe link after throttling. These parameters measure whether data transmission is continuous over a period of time, and their value is determined by calculating the time difference between adjacent data transmission intervals; shorter intervals indicate stronger continuity. A continuity threshold is set; when the data transmission continuity parameter is less than the threshold, data transmission is considered continuous; otherwise, it is considered discontinuous. Based on this, the energy optimization device divides the solid-state drive's cache space into a continuous transmission cache area and a discontinuous transmission cache area. The continuous transmission cache area stores frequently used data in continuous data transmission scenarios, while the discontinuous transmission cache area stores data involved in discontinuous data transmission.

[0041] Continuing with the above embodiment, in the throttled PCIe link, the power optimization device detected that the data transmission interval was mostly within 1 millisecond in the past 100 milliseconds, and calculated the data transmission continuity parameter to be 0.8 milliseconds. The continuity threshold is 1 millisecond. Since 0.8 milliseconds is less than 1 millisecond, the power optimization device divides the first 60% of the solid-state drive cache space into a continuous transmission buffer and the last 40% into a non-continuous transmission buffer. The continuous transmission buffer will subsequently be used to store continuously transmitted data such as video stream data, while the non-continuous transmission buffer will be used to store non-continuous data such as data generated by random file read / write operations.

[0042] Step 202: Based on the magnitude of the transmission jitter parameter in the link transmission state, the continuous transmission buffer is divided into a low jitter sub-buffer and a high jitter sub-buffer.

[0043] Furthermore, the energy optimization device continues to extract transmission jitter parameters from the link transmission status of the PCIe link after throttling. These jitter parameters reflect the fluctuation of the data transmission rate over a certain period and can be quantified by calculating the standard deviation of the data transmission rate. A jitter threshold is set; when the transmission jitter parameter is less than this threshold, the data transmission rate fluctuation is small, indicating low jitter; conversely, it is high jitter. Based on this, the energy optimization device further divides the continuous transmission buffer into a low-jitter sub-buffer and a high-jitter sub-buffer. The low-jitter sub-buffer is used to store data with high requirements for transmission stability, while the high-jitter sub-buffer stores data that can adapt to certain transmission rate fluctuations.

[0044] Continuing with the above embodiments, the transmission rate within the corresponding data transmission period is statistically analyzed. For example, if the transmission rates within a certain period are 98MB / s, 102MB / s, 100MB / s, 99MB / s, and 101MB / s, the calculated transmission jitter parameter (standard deviation) is 1.41MB / s. The jitter threshold is 2MB / s. Since 1.41MB / s is less than 2MB / s, the energy optimization device divides the first 70% of the continuous transmission buffer into a low-jitter sub-buffer and the last 30% into a high-jitter sub-buffer. The low-jitter sub-buffer can be used to store real-time audio and video call data, while the high-jitter sub-buffer is used to store video download data with slightly lower stability requirements.

[0045] Step 203: Based on the regularity of the transmission period parameters in the link transmission state, the discontinuous transmission buffer is divided into a regular periodic sub-buffer and an irregular periodic sub-buffer.

[0046] Furthermore, the energy optimization device extracts the transmission cycle parameter from the link transmission status of the PCIe link after throttling. This transmission cycle parameter describes whether data transmission exhibits a periodic pattern. It can be determined by performing a Fourier transform on the data transmission time series and analyzing its spectral characteristics to identify any significant periodic components. If significant periodic components are present, the transmission is regular; otherwise, it is irregular. Based on this, the energy optimization device divides the discontinuous transmission buffer into a regular periodic sub-buffer and an irregular periodic sub-buffer. The regular periodic sub-buffer stores data transmitted at a fixed period, while the irregular periodic sub-buffer stores data with irregular transmission cycles.

[0047] Continuing with the above embodiment, Fourier transform analysis of the transmission time series revealed that a portion of the data was transmitted every 500 milliseconds, exhibiting a clear periodic component, while the transmission time of another portion showed no obvious pattern. Therefore, the first 60% of the non-continuous transmission buffer was designated as a regular periodic sub-buffer, and the remaining 40% as an irregular periodic sub-buffer. The regular periodic sub-buffer can be used to store system periodic backup data, while the irregular periodic sub-buffer can be used to store file read / write data generated by random user operations.

[0048] Step 204: Construct a hierarchical cache structure based on low-jitter sub-cache, high-jitter sub-cache, regular-cycle sub-cache, and irregular-cycle sub-cache.

[0049] Furthermore, the energy consumption optimization device constructs a hierarchical cache structure based on low jitter sub-cache area, high jitter sub-cache area, regular periodic sub-cache area and irregular periodic sub-cache area, as described in steps 2041 to 2044.

[0050] Based on the continuity, jitter, and periodicity characteristics of data transmission, this invention divides the cache space into sub-cache areas with different characteristics, enabling data to be stored in the most suitable area. This allows the solid-state drive (SSD) to quickly locate the corresponding sub-cache area to retrieve data during data reading, reducing data search time and improving data access efficiency. During data writing, the cache space can also be rationally allocated according to data characteristics, avoiding waste of cache resources. At the same time, due to the improved efficiency of data storage and access, unnecessary working time of various components in the SSD is reduced, thereby reducing the overall power consumption of the SSD.

[0051] In one embodiment, steps 2041 to 2044 include:

[0052] Step 2041: Analyze the data interaction threshold between the two buffers based on the difference in transmission characteristics between the low-jitter sub-buffer and the high-jitter sub-buffer to obtain the cross-buffer transmission triggering condition, and configure independent transmission channels for the two buffers based on the cross-buffer transmission triggering condition to obtain the buffer isolation mechanism.

[0053] Optionally, the energy optimization device extracts transmission characteristic parameters from the low-jitter sub-buffer and the high-jitter sub-buffer. These parameters include data transmission rate fluctuation range, transmission delay stability, and data block size distribution. Further, the energy optimization device analyzes the data interaction requirements of the two buffers based on these transmission characteristic parameters and determines data interaction thresholds. These thresholds are used to determine when data migration between the two buffers is necessary. Specifically, the data interaction thresholds include a rate fluctuation threshold (triggered when the data transmission rate fluctuation of one buffer exceeds this value) and a delay deviation threshold (triggered when the difference in transmission delay between the two buffers exceeds this value).

[0054] Furthermore, based on the cross-zone transmission triggering condition, the energy consumption optimization device configures independent transmission channels for the two buffer zones. The independent transmission channels adopt a physical-level signal isolation design to avoid interference between the data transmission of the two buffer zones within the channel. At the same time, a dedicated transmission control module is set for each channel to ensure that the channel only responds to the transmission requests of the corresponding buffer zone, thus forming a buffer zone isolation mechanism to achieve independent and stable data transmission between the two buffer zones.

[0055] Continuing with the above embodiment, based on the low jitter sub-buffer (transmission rate fluctuation range 1MB / s-2MB / s, transmission delay deviation ≤0.5ms) and high jitter sub-buffer (transmission rate fluctuation range 3MB / s-5MB / s, transmission delay deviation ≤1.2ms) divided in step 202, the analysis shows that: when the transmission rate fluctuation of the low jitter sub-buffer exceeds 2.5MB / s, the transmission rate fluctuation of the high jitter sub-buffer is less than 2MB / s, or the difference in transmission delay between the two buffers exceeds 0.8ms, data interaction is required. That is, the critical value for rate fluctuation is determined to be 2.5MB / s for the low jitter area and 2MB / s for the high jitter area, and the critical value for delay deviation is 0.8ms.

[0056] Furthermore, the energy consumption optimization device configures channel A (with a fixed transmission bandwidth of 500MB / s, and the transmission control module only responds to data requests from the low jitter sub-buffer) and channel B (with a dynamically adjustable transmission bandwidth of 300MB / s-600MB / s, and the transmission control module only responds to data requests from the high jitter sub-buffer) for the low jitter sub-buffer. Channel A and channel B use independent PCIe signal lines to form a buffer isolation mechanism, avoiding mutual interference between stable data transmission in the low jitter zone and fluctuating data transmission in the high jitter zone.

[0057] Step 2042: Analyze the resource contention risk of the two cache areas based on the differences in task characteristics between the regular periodic sub-cache area and the irregular periodic sub-cache area, obtain the resource conflict assessment results, and divide the priorities of the two cache areas based on the resource conflict assessment results to obtain the cache area priorities.

[0058] Furthermore, the energy consumption optimization device collects task characteristic parameters from regular periodic sub-buffer areas and irregular periodic sub-buffer areas. These task characteristic parameters include the fixedness of the task execution cycle, the size of the task data, the task's response time requirements, and the task execution frequency.

[0059] Furthermore, the energy consumption optimization device analyzes the resource contention risk of two caches sharing solid-state drive cache resources (such as cache read / write bandwidth and cache storage capacity) based on task characteristic parameters. When two caches initiate resource requests simultaneously, insufficient resource allocation may lead to task delays. By comparing task characteristic parameters, the resource contention risk is quantified, and the resource conflict assessment result is obtained (for example, regular periodic tasks have a fixed cycle, and missing the resource allocation window will lead to task failure, resulting in a higher risk of resource contention; irregular periodic tasks can flexibly adjust their execution time, resulting in a lower risk of resource contention).

[0060] Furthermore, based on the resource conflict assessment results, the energy consumption optimization device uses a two-dimensional assessment model of "task criticality-resource dependency" to prioritize the two cache areas: the higher the task criticality (e.g., if a periodic task is delayed, it will affect the system's scheduled backup function) and the higher the resource dependency (e.g., periodic tasks must rely on fixed cache bandwidth to complete), the higher the priority; conversely, the lower the priority. The priority ranking of the two cache areas is then determined, resulting in the cache area priority.

[0061] Continuing with the above embodiments, regarding the regular periodic sub-cached area (the task is a file backup task executed by the system every 5 minutes, the task data volume is fixed at 2GB, the response time requirement is ≤10s, and the execution frequency is stable) and the irregular periodic sub-cached area (the task is a user-initiated image browsing task, the task data volume is 0.5MB-5MB, the response time requirement is ≤500ms, and the execution frequency is irregular) divided in step 203, the energy consumption optimization device analyzes: If the task in the regular periodic sub-cached area misses the 5-minute periodic window, it will lead to the loss of backup data. The task is highly critical and must rely on a fixed cache capacity of 2GB and a read / write bandwidth of 100MB / s to complete, resulting in high resource dependence. The task in the irregular periodic sub-cached area can be delayed when the user does not operate. The task is less critical, the requirements for cache capacity and bandwidth are flexible, and the resource dependence is low. Therefore, the resource conflict assessment result is that the resource contention risk of the regular periodic sub-cached area is higher than that of the irregular periodic sub-cached area.

[0062] Furthermore, based on the evaluation results, the energy consumption optimization device determines that the priority of the regular periodic sub-cache area is "high" and the priority of the irregular periodic sub-cache area is "low": when the two cache areas request cache resources at the same time, the regular periodic sub-cache area is given priority to allocate 2GB cache capacity and 100MB / s read / write bandwidth, and the remaining resources are then allocated to the irregular periodic sub-cache area.

[0063] Step 2043: Based on the buffer isolation mechanism and buffer priority analysis, analyze the collaborative response strategy of the low-jitter sub-buffer and the regular periodic sub-buffer to obtain the synchronization processing rules. Based on the synchronization processing rules, determine the advance time for the low-jitter sub-buffer to prepare associated data when the regular periodic sub-buffer triggers a periodic task, and obtain the linkage scheduling result.

[0064] Furthermore, the energy consumption optimization device combines a buffer isolation mechanism (independent transmission channels and interactive triggering conditions between low-jitter sub-buffers and high-jitter sub-buffers) and buffer priorities (high priority for regular-cycle sub-buffers and low priority for irregular-cycle sub-buffers) to analyze the collaborative response requirements of low-jitter sub-buffers and regular-cycle sub-buffers. When the regular-cycle sub-buffer performs periodic tasks, it may need the low-jitter sub-buffer to provide related data (such as backup tasks needing to read system configuration data stored in the low-jitter area). If the data in the low-jitter area is not prepared in advance, it will cause delays in regular-cycle tasks.

[0065] Based on this, the energy consumption optimization device formulates synchronization processing rules: before the periodic task is triggered in the periodic sub-buffer, a data preparation request is sent to the low-jitter sub-buffer; after receiving the request, the low-jitter sub-buffer prioritizes loading the associated data into the cache ready area through an independent transmission channel; if cross-area transmission conditions are triggered, data interaction must be completed before the execution of the periodic task. Simultaneously, by calculating the execution preparation time of the periodic task (the time required from request initiation to formal execution) and the loading time of the associated data in the low-jitter sub-buffer (the data transmission time from storage location to the cache ready area), the advance time for the low-jitter sub-buffer to prepare associated data when the periodic task is triggered is determined. That is, advance time = execution preparation time of the periodic task + loading time of the associated data in the low-jitter sub-buffer + reserved buffer time, ultimately obtaining the coordinated scheduling result.

[0066] Continuing with the above embodiment, combining the buffer isolation mechanism (low-jitter sub-buffer channel A, high-jitter sub-buffer channel B, with the interaction trigger condition being rate fluctuation or latency deviation exceeding the standard) and buffer priority (high priority for the periodic sub-buffer), analysis shows that when the periodic sub-buffer performs a backup task every 5 minutes, it needs to read the system configuration data (100MB in size) stored in the low-jitter sub-buffer. Calculations show that the preparation time for the periodic task execution is 2 seconds (from initiating the request to confirming resource readiness), the loading time of the associated data from the low-jitter sub-buffer through channel A is 0.2 seconds (100MB ÷ 500MB / s), and the reserved buffer time is 0.3 seconds (to cope with sudden transmission delays). Therefore, the advance time = 2s + 0.2s + 0.3s = 2.5s. Therefore, the following synchronization processing rules are established: 2.5 seconds before the regular periodic sub-buffer triggers the backup task, it sends a data preparation request to the low jitter sub-buffer; after receiving the request, the low jitter sub-buffer loads 100MB of system configuration data into the cache ready area through channel A; if the transmission rate of the low jitter area fluctuates or the delay deviation between the two areas exceeds the standard at this time, the data interaction must be completed within 2.5 seconds, and the linkage scheduling result is "2.5 seconds before the regular periodic sub-buffer triggers the periodic task, the low jitter sub-buffer starts the associated data preparation process".

[0067] Step 2044: Optimize the emergency handling mechanism of the high jitter sub-buffer and the irregular periodic sub-buffer based on the linkage scheduling results to obtain the burst response scheme. Based on the burst response scheme, reserve a preset proportion of cache space in the two buffers respectively to construct the hierarchical cache structure.

[0068] Furthermore, based on the coordinated scheduling results (coordination time and data interaction rules between low-jitter sub-buffer and regular-cycle sub-buffer), the emergency handling requirements of high-jitter sub-buffer and irregular-cycle sub-buffer are analyzed. The data transmission rate of the high-jitter sub-buffer fluctuates greatly, and the task execution of the irregular-cycle sub-buffer is random, which may lead to sudden data requests (such as a sudden large amount of data transmission in the high-jitter area or a sudden large file read / write in the irregular-cycle area). An emergency handling mechanism needs to be developed to deal with such situations.

[0069] Furthermore, the energy consumption optimization device optimizes the emergency response mechanism: when a sudden data transmission occurs in the high-jitter sub-buffer, its independent transmission channel bandwidth is temporarily increased; when a sudden large file read / write occurs in the irregular periodic sub-buffer, low-priority resources (such as the cache capacity when the regular periodic sub-buffer is idle) are prioritized to form a sudden response plan.

[0070] Furthermore, based on the burst response scheme, the energy consumption optimization device retains a preset proportion of cache space in the high jitter sub-cache area and the irregular periodic sub-cache area respectively (the preset proportion is determined according to the statistics of historical burst data volume, such as 20% cache space in the high jitter sub-cache area to cope with the temporary data storage needs caused by rate fluctuations, and 15% cache space in the irregular periodic sub-cache area to cope with burst large file read and write).

[0071] Furthermore, the energy consumption optimization device integrates a low jitter sub-buffer area (including independent channel A and data interaction threshold), a high jitter sub-buffer area (including independent channel B and 20% reserved space), a regular periodic sub-buffer area (high priority and linkage scheduling rules), and an irregular periodic sub-buffer area (low priority and 15% reserved space) to construct a layered cache structure.

[0072] Continuing with the above embodiments, based on the linkage scheduling results (prepared data for the low jitter zone 2.5s before the regular cycle task), the energy consumption optimization device analyzes: the high jitter sub-buffer may experience a sudden increase in transmission rate from 300MB / s to 600MB / s, and the irregular cycle sub-buffer may experience a sudden task where a user suddenly uploads a 100MB image. Therefore, the optimized emergency handling mechanism is as follows: when the high jitter sub-buffer experiences a sudden increase, the bandwidth of channel B is temporarily adjusted from 300MB / s-600MB / s to 400MB / s-700MB / s; when the irregular cycle sub-buffer experiences a sudden increase, if there are no tasks executing in the regular cycle sub-buffer, its idle cache capacity can be utilized.

[0073] Furthermore, statistical analysis of historical data by the energy optimization device revealed that the maximum burst data volume in the high-jitter sub-buffer accounts for 18% of its total capacity. Therefore, 20% of the cache space (total capacity 10GB, 2GB reserved) is reserved in the high-jitter sub-buffer. The maximum burst data volume in the irregular-period sub-buffer accounts for 12% of its total capacity, so 15% of the cache space (total capacity 8GB, 1.2GB reserved) is reserved. Finally, the characteristics of each sub-buffer are integrated: low-jitter sub-buffer (capacity 12GB, channel A bandwidth 500MB / s, interaction threshold of rate fluctuation 2.5MB / s, latency deviation 0.8ms), high-jitter sub-buffer (capacity 10GB, channel B bandwidth 400MB / s-700MB / s, 2GB reserved), regular-period sub-buffer (capacity 15GB, high priority, triggers the low-jitter zone 2.5s before the task), and irregular-period sub-buffer (capacity 8GB, low priority, 1.2GB reserved), to construct a layered cache structure.

[0074] This invention, through the construction of a refined hierarchical caching architecture, achieves efficient allocation and scheduling of cache resources, reducing the ineffective energy consumption of solid-state drives (SSDs) caused by unstable data transmission, resource contention conflicts, and improper handling of sudden data. Under the premise of ensuring the basic needs of data transmission and task execution, it reduces the overall energy consumption of SSDs.

[0075] In one embodiment, steps 401 to 404 include:

[0076] Step 401: Based on the stability and fluctuation range of the second data transmission rate, determine the theoretical optimal operating frequency range of each component under the second data transmission rate.

[0077] Optionally, the energy consumption optimization device analyzes the stability and fluctuation range of the second data transmission rate, wherein the stability is measured by the coefficient of variation of the transmission rate per unit time (the smaller the coefficient of variation, the higher the stability), and the fluctuation range is determined by the difference between the maximum and minimum values ​​of the transmission rate.

[0078] Furthermore, based on stability and fluctuation range, and combined with the hardware characteristics of each component (flash memory chip, main control chip, cache chip) (such as rated frequency range, frequency-power consumption curve), the energy consumption optimization device calculates the theoretically optimal operating frequency range that can meet the data transmission requirements and minimize energy consumption at the current second data transmission rate. The lower limit of the theoretically optimal operating frequency range must ensure that the component processing capacity is not lower than the load requirement corresponding to the second data transmission rate, while the upper limit must avoid ineffective energy consumption caused by excessive frequency.

[0079] Continuing with the above embodiment, the second data transmission rate is 1200MB / s. The power consumption optimization device analysis shows its stability parameter (coefficient of variation) is 5% (high stability), with a fluctuation range of 1100-1300MB / s. Considering the component hardware characteristics: the flash memory chip's rated frequency range is 200-800MHz, and the theoretical optimal operating frequency range is calculated to be 300-400MHz (meeting the 1200MB / s transmission requirement while remaining in the low-power range). The main control chip's rated frequency range is 500-2000MHz, and the theoretical optimal operating frequency range is 800-1000MHz. The cache chip's rated frequency range is 400-1600MHz, and the theoretical optimal operating frequency range is 600-800MHz.

[0080] Step 402: Based on the data read / write frequency and data access pattern of each cache layer in the cache layout, analyze the actual workload distribution of each component when processing cached data.

[0081] Furthermore, the energy optimization device extracts the data read / write frequency (number of read / write operations per unit time) and data access patterns (such as continuous access, random access, burst access, etc.) of each cache layer (low-jitter sub-cache area, high-jitter sub-cache area, regular-period sub-cache area, and irregular-period sub-cache area) in the cache layout (cache layout after task migration). Based on the characteristics of different cache layers, the actual workload distribution of each component when processing this cached data is analyzed: the load of the flash memory chip is related to the data persistent write frequency, the load of the main control chip is related to the data scheduling and protocol processing complexity, and the load of the cache chip is related to the data temporary storage and fast exchange frequency. The load distribution is quantified and described by the load intensity (such as operations per second) in different time periods.

[0082] Continuing with the above embodiments, based on cache layout analysis: the low-jitter sub-cache has a data read / write frequency of 500 times / second, primarily consisting of continuous access. The high-jitter sub-cache has a data read / write frequency of 300 times / second, primarily consisting of burst access. The regular-period sub-cache has a data read / write frequency of 200 times / second, primarily consisting of periodic continuous access. The irregular-period sub-cache has a data read / write frequency of 100 times / second, primarily consisting of random access.

[0083] Analysis of the energy consumption optimization device shows that:

[0084] The actual workload distribution of flash memory chips is as follows: 80% of the time is under low to medium load (200-300 write operations per second), and 20% of the time is under medium to high load (300-400 write operations per second).

[0085] The actual workload distribution of the main control chip is as follows: it is under medium load for 60% of the time (400-600 scheduling operations per second) and under medium-high load for 40% of the time (600-800 scheduling operations per second).

[0086] The actual workload distribution of the cache chip is as follows: it is under low load (300-500 swap operations per second) for 90% of the time and under high load (500-700 swap operations per second) for 10% of the time.

[0087] Step 403: Based on the theoretical optimal operating frequency range and actual workload distribution of each component, determine the degree of deviation between the current operating mode and the optimal state of each component.

[0088] Furthermore, the energy consumption optimization device compares and analyzes the theoretical optimal operating frequency range of each component with the actual workload distribution. Specifically, for each component, the energy consumption optimization device calculates the matching degree between its current operating frequency's load processing capacity and the actual workload, as well as the deviation value between the current frequency and the theoretical optimal frequency range. The degree of state deviation is represented by a composite index of "frequency deviation coefficient" and "load matching coefficient". The larger the frequency deviation coefficient (the more the current frequency exceeds the theoretical optimal range), the higher the degree of state deviation; the smaller the load matching coefficient (the greater the gap between the processing capacity and the actual load), the higher the degree of state deviation. This yields a quantitative value of the degree of state deviation for each component (range 0-1, with larger values ​​indicating more severe deviation).

[0089] Continuing with the above embodiments, the current operating frequencies of each component are: flash memory chip 450MHz, main control chip 1200MHz, and cache chip 900MHz.

[0090] Flash memory chip: The current frequency of 450MHz exceeds the theoretical optimal range (300-400MHz) upper limit, with a frequency deviation coefficient of 0.2; the actual load and processing capacity match 80%, with a load matching coefficient of 0.8. Therefore, the overall state deviation is 0.3 (the deviation is relatively obvious).

[0091] Main control chip: The current frequency of 1200MHz exceeds the theoretical optimal range (800-1000MHz) upper limit, with a frequency deviation coefficient of 0.3; the actual load and processing capacity match 70%, with a load matching coefficient of 0.7. Therefore, the overall state deviation is 0.4 (significant deviation).

[0092] Cache chip: The current frequency of 900MHz exceeds the upper limit of the theoretical optimal range (600-800MHz), with a frequency deviation coefficient of 0.1; the actual load and processing capacity match 90%, with a load matching coefficient of 0.9. Therefore, the overall state deviation is 0.2 (small deviation).

[0093] Step 404: Adjust the current working mode of each component based on the degree of state deviation of each component to obtain the adjusted working mode of each component.

[0094] Furthermore, the energy consumption optimization device adjusts the current working mode of each component according to the degree of state deviation of each component, and obtains the adjusted working mode of each component, as detailed in steps 4041 to 40412.

[0095] This invention, based on the theoretically optimal operating frequency range determined by the second data transmission rate, ensures a fundamental match between component performance and transmission requirements. Combined with actual workload distribution analysis of cache layout, adjustments are made to better fit actual operating scenarios. The degree of state deviation is used to quantify and guide the adjustment range, achieving "on-demand adjustment." This ensures a high degree of matching between the operating frequency of each component and actual load requirements, avoiding energy waste caused by high-frequency, inefficient operation. Enhanced synergy between component operating modes reduces ineffective power consumption caused by performance mismatch. While meeting the second data transmission rate requirements, the overall energy consumption of the solid-state drive is reduced, while maintaining stable performance output, achieving an optimal balance between energy consumption and performance.

[0096] In one embodiment, steps 4041 to 4044 include:

[0097] Step 4041: Based on the degree of state deviation of the flash memory chip, identify the degree of matching between the number of active read and write units of the flash memory chip in the current working mode and the actual needs, obtain the read and write unit configuration deviation result, and merge continuously idle read and write units into a sleep group based on the read and write unit configuration deviation result, to obtain the dynamic grouping result of read and write units.

[0098] Optionally, the energy optimization device analyzes the degree of mismatch between the number of activated read / write units and actual demand in the current operating mode of the flash memory chip based on the state deviation of the flash memory chip. The number of activated read / write units refers to the number of basic units currently in operation that can be used for data read / write operations, while the actual demand is determined based on the current data transmission volume and cached data processing requirements. By comparing the number of activated units with the actual demand, the read / write unit configuration deviation result is obtained (e.g., the proportion by which the number of activated units exceeds the actual demand). Based on this deviation result, the energy optimization device merges continuously idle read / write units into dormant groups. Each dormant group contains a certain number of continuously idle read / write units, forming a dynamic grouping result of read / write units.

[0099] Continuing with the above embodiment, the state deviation of the flash memory chip is 0.3, and the number of currently active read / write units is 200. However, according to the actual data processing requirements, only 150 read / write units are needed to meet the operational requirements. The read / write unit configuration deviation result is that the number of active units exceeds the actual requirement by 33% (50 read / write units are in an idle state). The energy consumption optimization device identifies 40 consecutively idle read / write units and merges them into 4 sleep groups (each group has 10 consecutively idle read / write units), obtaining the dynamic grouping result of read / write units. The remaining 10 scattered idle read / write units are not merged temporarily because they are not continuous.

[0100] Step 4042: Analyze the hibernation trigger conditions of the read / write units in the hibernation group based on the dynamic grouping results of the read / write units, obtain hibernation control parameters, and adjust the power supply voltage of the read / write units in the hibernation group to the preset standby level based on the hibernation control parameters, thereby obtaining the voltage regulation result.

[0101] Furthermore, the energy consumption optimization device analyzes the hibernation triggering conditions of the read and write units in each hibernation group based on the dynamic grouping results of the read and write units. The hibernation triggering conditions include parameters such as idle duration and next expected usage time. When the preset idle duration is met and there is no usage plan in the short term, the hibernation mechanism is triggered.

[0102] Furthermore, the energy consumption optimization device determines the sleep control parameters (such as sleep voltage value, voltage regulation rate, etc.) based on the sleep triggering conditions, and adjusts the power supply voltage of the read and write unit in the sleep group from the normal operating voltage to the preset standby level (this level is lower than the normal operating voltage and only maintains the basic circuit wake-up capability) based on the sleep control parameters, thus obtaining the voltage regulation result.

[0103] Continuing with the above embodiment, based on the four hibernation groups obtained in step 4041, the energy consumption optimization device analyzes and concludes that: the read / write unit of each hibernation group has been idle for 5 minutes continuously, and according to the task scheduling plan, there is no usage requirement in the next 30 minutes, thus meeting the hibernation trigger condition. The hibernation control parameters are determined as follows: standby voltage 0.8V (normal operating voltage is 1.2V), and voltage regulation rate 0.1V / second. The energy consumption optimization device gradually reduces the power supply voltage of the read / write units in the four hibernation groups from 1.2V to 0.8V according to these parameters, obtaining the voltage regulation result. At this time, the energy consumption of these hibernation groups is reduced by approximately 40% compared to the normal operating state.

[0104] Step 4043: Based on the voltage regulation results, analyze the differences in erase and write frequencies of the flash memory chip in different memory blocks to obtain the memory block usage intensity distribution. Based on the memory block usage intensity distribution, transfer the tasks of memory blocks with usage intensity greater than a preset intensity threshold to memory blocks with usage intensity less than or equal to the preset intensity threshold to obtain the memory block rotation scheduling result.

[0105] Furthermore, the energy optimization device analyzes the differences in erase and write frequencies of different memory blocks based on the voltage regulation results. The erase and write frequency refers to the number of erase and write operations performed on a memory block per unit time, reflecting the usage intensity of the memory block. By statistically analyzing the erase and write frequencies of each memory block, the usage intensity distribution of the memory blocks is obtained. A preset intensity threshold is set, and memory blocks with usage intensity greater than the preset threshold are identified as high-load memory blocks, while those with usage intensity less than or equal to the preset threshold are identified as low-load memory blocks. Therefore, based on the memory block usage intensity distribution, the energy optimization device transfers tasks from high-load memory blocks to low-load memory blocks, obtaining the memory block rotation scheduling result.

[0106] Continuing with the above embodiments, based on the voltage regulation results, the energy consumption optimization device statistically analyzes the erase / write frequencies of 20 memory blocks in the flash memory chip to obtain the memory block usage intensity distribution: 5 memory blocks have an erase / write frequency of 80 times / hour, 8 memory blocks have an erase / write frequency of 50 times / hour, and 7 memory blocks have an erase / write frequency of 20 times / hour. The preset intensity threshold is 40 times / hour. Therefore, the 5 memory blocks with an erase / write frequency of 80 times / hour are high-load memory blocks, and the remaining 15 are low-load memory blocks. Thus, some tasks (such as non-urgent data storage tasks) on these 5 high-load memory blocks are transferred to the 7 low-load memory blocks with an erase / write frequency of 20 times / hour, resulting in a memory block rotation scheduling result, reducing the erase / write frequency of the high-load memory blocks to below 50 times / hour.

[0107] Step 4044: Update the garbage collection triggering mechanism of the flash memory chip based on the storage block rotation scheduling result, and perform garbage collection frequency adjustment based on the garbage collection triggering mechanism.

[0108] Furthermore, the energy optimization device updates the garbage collection triggering mechanism of the flash memory chip based on the storage block rotation scheduling results. The garbage collection triggering mechanism refers to the conditions that trigger the flash memory chip to perform invalid data cleanup and storage space reorganization operations, such as the proportion of invalid data in the storage block and the number of free storage blocks. Further, based on the usage status of each storage block after the storage block rotation, the energy optimization device adjusts the threshold parameters in the triggering mechanism (such as increasing the invalid data proportion threshold and decreasing the free storage block number threshold), and performs garbage collection frequency adjustment based on the updated garbage collection triggering mechanism to reduce the number of unnecessary garbage collection operations.

[0109] Continuing with the above embodiments, based on the storage block rotation scheduling results, the original garbage collection triggering mechanism was: garbage collection was triggered when the proportion of invalid data in a storage block reached 50% or the number of free storage blocks was less than 5. The energy consumption optimization device updated this to: garbage collection was triggered when the proportion of invalid data in a storage block reached 70% and the number of free storage blocks was less than 3. Based on the updated triggering mechanism, the garbage collection operation frequency was adjusted from 3 times per hour to 1 time per hour, ensuring effective utilization of storage space while reducing the additional energy consumption caused by frequent garbage collection.

[0110] This invention integrates idle resources by dynamically grouping read and write units, reducing ineffective energy consumption. The voltage regulation of the hibernation group further reduces the power consumption of idle units. The storage block rotation scheduling balances the usage intensity of each storage block, extends the overall lifespan of the flash memory chip, and avoids additional energy consumption caused by excessive local consumption. The garbage collection frequency adjustment reduces unnecessary background operation energy consumption. This reduces the operating energy consumption of the flash memory chip while ensuring that its data processing capability meets the system requirements, thereby improving the stability and lifespan of the flash memory chip and achieving synergistic optimization of energy consumption, performance, and lifespan.

[0111] In one embodiment, steps 4045 to 4048 include:

[0112] Step 4045: Based on the state deviation degree of the main control chip, detect the load balancing status of the core computing unit of the main control chip in the current working mode, obtain the core load distribution result, and based on the core load distribution result, migrate the data verification function from the main core to the idle auxiliary core to obtain the core function decomposition result.

[0113] Optionally, the energy consumption optimization device detects the load balancing status of the core computing units of the main control chip in its current operating mode based on the degree of state deviation. The core computing units include the main core and auxiliary cores. The load balancing status is measured by parameters such as the computing utilization rate of each core and the task queue length. By comparing the load data of different cores, the core load distribution result is obtained (e.g., the difference between the load rate of the main core and the load rate of the auxiliary core). Further, based on this distribution result, the energy consumption optimization device migrates the data verification functions (such as CRC check, ECC check, etc.) originally undertaken by the main core to the idle auxiliary cores, allowing the main core to focus on core tasks such as data scheduling, resulting in a core function decomposition.

[0114] Continuing with the above embodiment, the state deviation of the main control chip is 0.4, which includes one main core and three auxiliary cores. The core load distribution results show that the main core load rate is 85% (primarily responsible for data scheduling and data verification functions), auxiliary core 1 load rate is 30%, and auxiliary cores 2 and 3 load rates are both below 10% (idle). The energy optimization device migrates the data verification function from the main core to auxiliary core 2. After the migration, the core function decomposition results are: the main core load rate drops to 60%, the auxiliary core 2 load rate rises to 45%, and the overall core load distribution is more balanced.

[0115] Step 4046: Based on the core function breakdown results, the processing time ratio of different task types is statistically analyzed to obtain the task time distribution. Based on the task time distribution, tasks with priorities lower than the preset priority threshold are replaced by batch processing scheduling algorithm instead of real-time scheduling algorithm to obtain the scheduling algorithm switching result.

[0116] Furthermore, the energy consumption optimization device, based on the core function breakdown results, statistically analyzes the processing time percentages of different task types (such as data read / write tasks, status monitoring tasks, and error repair tasks) handled by the main control chip. The processing time percentage refers to the proportion of the total processing time of a certain type of task to the total processing time of all tasks, thus obtaining the task time distribution. A preset priority threshold is set, and tasks with priorities below this threshold (such as non-real-time status reporting tasks) are identified as low-priority tasks. Based on the task time distribution, the energy consumption optimization device switches the scheduling method of these low-priority tasks from a real-time scheduling algorithm (immediate response processing) to a batch processing scheduling algorithm (processing a certain number of tasks at once), obtaining the scheduling algorithm switching result.

[0117] Continuing with the above embodiments, based on the core function breakdown results, the energy consumption optimization device statistically determined the task time distribution: data read / write tasks accounted for 60% (high priority), error repair tasks accounted for 20% (medium priority), and status monitoring tasks accounted for 20% (low priority). Setting the preset priority threshold to medium priority, the status monitoring task was thus classified as a low-priority task. The scheduling algorithm for the status monitoring task was switched from real-time scheduling (processing each piece of status data immediately upon generation) to batch processing scheduling (processing all 10 pieces of status data at once). This change in scheduling algorithm reduced the computational overhead caused by frequent scheduling.

[0118] Step 4047: Based on the switching results of the scheduling algorithm, analyze the communication interval pattern between the main control chip and other components except itself to obtain the communication cycle characteristics, and adjust the interface clock frequency to the preset operating level during the communication gap based on the communication cycle characteristics to obtain the interface clock frequency adjustment result.

[0119] Furthermore, the energy consumption optimization device analyzes the communication interval patterns between the main control chip and other components (such as flash memory chips and cache chips) based on the switching results of the scheduling algorithm. These communication interval patterns are determined by parameters such as the number of communications per unit time and the time interval between two adjacent communications, thereby obtaining communication cycle characteristics (such as average communication interval and longest communication gap). Further, based on these communication cycle characteristics, the energy consumption optimization device adjusts the interface clock frequency from the normal operating frequency to a preset operating level (which is lower than the normal operating frequency, only maintaining a basic communication preparation state) during communication gaps (i.e., the idle period between two communications), obtaining the interface clock frequency adjustment results.

[0120] Continuing with the above embodiments, based on the scheduling algorithm switching results, the energy consumption optimization device analyzes and concludes that the communication cycle characteristics between the main control chip and other components are an average communication interval of 50 milliseconds and a maximum communication gap of 100 milliseconds. During the communication gap, the energy consumption optimization device adjusts the interface clock frequency from the normal operating frequency of 100MHz to a preset operating level of 50MHz. When the next communication request is detected, the clock frequency is restored to 100MHz 5 milliseconds in advance. The final interface clock frequency adjustment result is that the interface clock operates at a low frequency for approximately 40% of the communication gap time, reducing energy consumption during idle periods.

[0121] Step 4048: Optimize the instruction queue structure of the main control chip based on the interface clock frequency adjustment result, obtain the target instruction buffer mechanism, and perform instruction prefetch strategy adjustment based on the target instruction buffer mechanism.

[0122] Furthermore, the energy consumption optimization device optimizes the instruction queue structure of the main control chip based on the interface clock frequency adjustment results. The instruction queue structure optimization includes adjusting the queue length and classifying and storing different types of instructions (such as read, write, and instruction), so that the instruction scheduling is more adapted to the current interface clock state, and the target instruction buffer mechanism is obtained.

[0123] Furthermore, the energy consumption optimization device adjusts the instruction prefetch strategy based on the target instruction buffer mechanism, such as reducing the number of prefetched instructions during low clock frequency periods, increasing the prefetch weight of high-priority instructions, and avoiding invalid instruction prefetching operations that consume additional resources.

[0124] Continuing with the above embodiment, based on the interface clock frequency adjustment results, the main control chip's instruction queue is split from a single queue into a high-priority instruction queue (20 instructions) and a low-priority instruction queue (10 instructions), forming a target instruction buffer mechanism. The instruction prefetching strategy is adjusted synchronously: during the low-frequency period of 50MHz interface clock, only the next two high-priority instructions are prefetched; during the normal frequency period of 100MHz interface clock, the next five high-priority instructions and two low-priority instructions are prefetched. This adjustment avoids excessive prefetching during low-frequency periods, reducing invalid instruction cache usage and power consumption.

[0125] This invention balances the load of each computing unit by splitting core functions, avoiding excessive consumption of the main core. The scheduling algorithm switching reduces the frequent processing overhead of low-priority tasks, the interface clock adjustment reduces the ineffective energy consumption during communication gaps, and the instruction prefetching strategy optimizes the resource consumption of instruction processing. This reduces the operating energy consumption of the main control chip while ensuring that the data processing efficiency and task response speed of the main control chip meet the system requirements. At the same time, by optimizing the resource allocation and scheduling mechanism, the overall operating efficiency and stability of the main control chip are improved, achieving synergistic optimization of energy consumption and performance.

[0126] In one embodiment, steps 4049 to 40412 include:

[0127] Step 4049: Evaluate the difference in hit rate of cache chips in the current cache partition based on the state deviation of cache chips, obtain partition efficiency results, and reduce the storage space allocation of partitions with hit rates lower than preset values ​​based on partition efficiency results, to obtain cache space remapping results.

[0128] Optionally, the energy optimization device evaluates the difference in hit rate of the cache chip in the current cache partition (such as low jitter sub-cache area, high jitter sub-cache area, etc.) based on the degree of state deviation of the cache chip. The hit rate refers to the proportion of data requests that directly hit the cache and directly obtain data. The difference in hit rate is reflected by the standard deviation of the hit rate of each partition. By statistically analyzing the actual hit rate of each cache partition, the partition efficiency result is obtained.

[0129] Furthermore, a preset value (such as 60%) is set, and partitions with a hit rate lower than this value are identified as inefficient partitions. Based on the partition efficiency results, the energy consumption optimization device reduces the storage space allocation of these inefficient partitions and allocates the freed space to efficient partitions with high hit rates, thus forming a cache space remapping result.

[0130] Continuing with the above embodiment, the state deviation of the cache chip is 0.2, and it contains four cache partitions: a low-jitter sub-cache with a hit rate of 85%, a high-jitter sub-cache with a hit rate of 70%, a regular-cycle sub-cache with a hit rate of 55%, and an irregular-cycle sub-cache with a hit rate of 50%. The preset hit rate is set to 60%, therefore the regular-cycle and irregular-cycle sub-caches are inefficient partitions. Thus, the storage space of the regular-cycle sub-cache is reduced from 20% to 10%, and the storage space of the irregular-cycle sub-cache is reduced from 20% to 5%. The freed-up 15% space is allocated to the low-jitter sub-cache (increased from 30% to 40%) and the high-jitter sub-cache (increased from 30% to 35%), resulting in a cache space remapping.

[0131] Step 40410: Analyze the access interval of different data blocks based on the cache space remapping results to obtain the data activity cycle. Then, based on the data activity cycle, extend the refresh interval of inactive data blocks to obtain the cache refresh mechanism modification result.

[0132] Furthermore, the energy consumption optimization device analyzes the access interval duration of different data blocks in the cache chip based on the cache space remapping results. The access interval duration refers to the time interval between two accesses of the same data block, which is calculated by recording the access timestamps of each data block. Based on the distribution characteristics of the access interval duration, the data activity cycle is obtained (e.g., high-frequency activity cycle ≤ 10 seconds, medium-frequency activity cycle 10-60 seconds, low-frequency activity cycle > 60 seconds). Further, based on the data activity cycle, the energy consumption optimization device adopts a strategy of extending the refresh interval (the refresh interval refers to the time interval for cache data updates) for inactive data blocks (i.e., data blocks in the low-frequency activity cycle), thus obtaining the cache refresh mechanism modification result.

[0133] Continuing with the above embodiments, based on the cache space remapping results, the energy consumption optimization device analyzes and determines the data activity cycle: data in the low-jitter sub-cache area is mainly active at high frequencies (access interval ≤ 10 seconds), data in the high-jitter sub-cache area is mainly active at medium frequencies (access interval 10-60 seconds), and the remaining data in the regular and irregular period sub-cache areas is mainly active at low frequencies (access interval > 60 seconds). The energy consumption optimization device keeps the refresh interval of high-frequency active data blocks unchanged at 1 second, extends the refresh interval of medium-frequency active data blocks from 2 seconds to 5 seconds, and extends the refresh interval of low-frequency active data blocks from 5 seconds to 30 seconds, thus obtaining the result of modifying the cache refresh mechanism and reducing invalid refresh operations on inactive data blocks.

[0134] Step 40411: Based on the cache refresh mechanism, modify the result to detect the bank conflict frequency inside the cache chip to obtain the bank contention result. Based on the bank contention result, increase the access interval of the conflicting banks to obtain the memory interleaving parameter adjustment result.

[0135] Furthermore, the energy optimization device modifies the cache refresh mechanism based on the result of detecting the bank conflict frequency within the cache chip to obtain the bank contention result. A bank (memory unit) is an independent storage unit within the cache chip. Bank conflict is a waiting phenomenon caused by multiple data requests accessing the same bank simultaneously. The conflict frequency is measured by the number of conflicts occurring per unit time. Based on the bank contention result, the energy optimization device increases the access interval (i.e., the minimum time interval between two consecutive accesses to the same bank) for banks with high conflict frequencies, adjusting the timing parameters of memory interleaving access to obtain the memory interleaving parameter adjustment result.

[0136] Continuing with the above embodiment, based on the cache refresh mechanism modification results, the power optimization device detected that among the eight banks of the cache chip, bank3 and bank5 had the highest conflict frequency (15 conflicts per second), while the conflict frequency of other banks was less than 5 times per second. The power optimization device increased the access interval of bank3 and bank5 from the original 10 nanoseconds to 20 nanoseconds, while keeping the other banks unchanged at 10 nanoseconds. After the adjustment, the conflict frequency of bank3 and bank5 decreased to 8 times per second, resulting in the memory interleaving parameter adjustment result, which reduced the performance loss and additional power consumption caused by bank conflicts.

[0137] Step 40412: Analyze the idle state determination conditions of the cache chip based on the results of the memory interleaving parameter adjustment, obtain the idle detection rules, and perform low-power mode switching based on the idle detection rules.

[0138] Furthermore, based on the memory interleaving parameter adjustment results, the power optimization device analyzes the idle state determination conditions of the cache chip. These conditions include parameters such as the total cache access frequency, the idle duration of each bank, and the instruction queue length. By setting threshold ranges for these parameters, idle detection rules are obtained (e.g., when the total access frequency is below 50 times / second and all banks are continuously idle for 100 milliseconds, it is determined to be a deep idle state). Further, based on the idle detection rules, when the cache chip meets the corresponding idle conditions, the power optimization device switches it from normal operating mode to low-power mode (e.g., shutting down some clock circuits, reducing core voltage, etc.), performing a low-power mode switching operation.

[0139] Continuing with the above embodiments, based on the memory interleaving parameter adjustment results, the power optimization device sets idle detection rules: when the total cache access frequency is less than 30 times / second and all banks are continuously idle for 50 milliseconds, it is determined to be a light idle state; when the total access frequency is less than 10 times / second and all banks are continuously idle for 200 milliseconds, it is determined to be a deep idle state. During light idle, it switches to standby mode (core voltage drops from 1.0V to 0.9V); during deep idle, it switches to sleep mode (60% of the clock circuit is turned off). During periods of low system load, when the cache chip meets the deep idle condition, the power optimization device switches it to sleep mode, resulting in a low-power mode switching outcome, significantly reducing power consumption in the idle state.

[0140] The embodiments of this invention improve the utilization efficiency of storage resources by remapping the cache space of the Palace Museum, avoid the waste of resources in inefficient partitions, reduce invalid operations on inactive data by modifying the cache refresh mechanism, reduce unnecessary energy consumption, alleviate bank conflicts by adjusting the storage interleaving parameters, improve data access efficiency, and reduce energy consumption in idle state by switching to low power mode. This reduces the overall energy consumption of the cache chip while ensuring that the data hit rate and access speed of the cache chip meet the system requirements. At the same time, by optimizing resource allocation and operation mechanism, the stability and lifespan of the cache chip are improved, and the synergistic optimization of energy consumption, performance and resource utilization is achieved.

[0141] Furthermore, the solid-state drive power consumption optimization device provided by the present invention will be described below. The solid-state drive power consumption optimization device described below can be referred to in correspondence with the solid-state drive power consumption optimization method described above.

[0142] Optional, refer to Figure 2 , Figure 2 This is a schematic diagram of the solid-state drive power consumption optimization device provided by the present invention. The solid-state drive power consumption optimization device includes:

[0143] The link throttling module 210 is used to throttle the transmission bandwidth of the PCIe link if the first data transmission rate of the PCIe link between the solid-state drive and the host is found to be insufficient to meet the transmission rate requirements, so as to obtain the throttled PCIe link.

[0144] The cache space stratification module 220 is used to perform stratification operations on the cache space of the solid-state drive based on the link transmission status of the PCIe link after throttling, so as to obtain the stratified cache structure.

[0145] The task migration module 230 is used to determine the migrateable tasks in each cache layer based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, and migrate the migrateable tasks of each cache layer to the target cache area to obtain the cache layout after task migration.

[0146] The working mode adjustment module 240 is used to adjust the working mode of each component in the solid-state drive based on the second data transfer rate and cache layout if the second data transfer rate of the PCIe link after throttling is detected to meet the transfer rate requirements, so as to reduce the power consumption of the solid-state drive.

[0147] This invention monitors the real-time data transmission volume of the PCIe link and performs throttling operations to obtain the transmission status of the PCIe link after throttling, reducing energy consumption during data transmission. Based on this result, the cache space is intelligently layered to store data rationally, improving cache utilization efficiency and reducing unnecessary cache access energy consumption. Based on the layered cache structure, the invention monitors and obtains information on migrateable idle tasks, and migrates these idle tasks to obtain a new storage layout, further optimizing the data storage and task execution methods within the solid-state drive (SSD) and reducing energy consumption in the storage area. Based on the storage layout after task migration, the PCIe link transmission status is further optimized to continuously reduce data transmission energy consumption. Finally, based on the optimized PCIe link transmission status and the storage layout after task migration, the operating modes of each component of the SSD are dynamically adjusted, reducing the overall energy consumption of the SSD. This achieves efficient optimization of SSD energy consumption in complex working scenarios, as well as improving read / write performance and lifespan.

[0148] Please see Figure 3 , Figure 3 An embodiment diagram of an electronic device provided in accordance with the present invention. For example... Figure 3 As shown, this embodiment of the invention provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor 320. When the processor 320 executes the computer program 311, it performs the following steps:

[0149] If the first data transfer rate of the PCIe link between the solid-state drive and the host is found to be insufficient to meet the transfer rate requirements, the transfer bandwidth of the PCIe link is throttled to obtain the throttled PCIe link.

[0150] Based on the link transmission status of the PCIe link after throttling, the cache space of the solid-state drive is layered to obtain the layered cache structure.

[0151] Based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, the transferable tasks in each cache layer are determined, and the transferable tasks of each cache layer are migrated to the target cache area to obtain the cache layout after task migration.

[0152] If the second data transfer rate of the PCIe link after throttling is found to meet the transfer rate requirements, the operating mode of each component in the solid-state drive is adjusted based on the second data transfer rate and cache layout to reduce the power consumption of the solid-state drive.

[0153] Please see Figure 4 , Figure 4 An embodiment diagram of a computer-readable storage medium provided in accordance with an embodiment of the present invention is shown. Figure 4As shown, this embodiment provides a computer-readable storage medium 400 on which a computer program 311 is stored. When the computer program 311 is executed by a processor, it performs the following steps:

[0154] If the first data transfer rate of the PCIe link between the solid-state drive and the host is found to be insufficient to meet the transfer rate requirements, the transfer bandwidth of the PCIe link is throttled to obtain the throttled PCIe link.

[0155] Based on the link transmission status of the PCIe link after throttling, the cache space of the solid-state drive is layered to obtain the layered cache structure.

[0156] Based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, the transferable tasks in each cache layer are determined, and the transferable tasks of each cache layer are migrated to the target cache area to obtain the cache layout after task migration.

[0157] If the second data transfer rate of the PCIe link after throttling is found to meet the transfer rate requirements, the operating mode of each component in the solid-state drive is adjusted based on the second data transfer rate and cache layout to reduce the power consumption of the solid-state drive.

[0158] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the solid-state drive power consumption optimization method provided by the above methods, the method including:

[0159] If the first data transfer rate of the PCIe link between the solid-state drive and the host is found to be insufficient to meet the transfer rate requirements, the transfer bandwidth of the PCIe link is throttled to obtain the throttled PCIe link.

[0160] Based on the link transmission status of the PCIe link after throttling, the cache space of the solid-state drive is layered to obtain the layered cache structure.

[0161] Based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, the transferable tasks in each cache layer are determined, and the transferable tasks of each cache layer are migrated to the target cache area to obtain the cache layout after task migration.

[0162] If the second data transfer rate of the PCIe link after throttling is found to meet the transfer rate requirements, the operating mode of each component in the solid-state drive is adjusted based on the second data transfer rate and cache layout to reduce the power consumption of the solid-state drive.

[0163] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0164] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for optimizing the power consumption of a solid-state drive, characterized in that, include: If the first data transfer rate of the PCIe link between the solid-state drive and the host is found to be insufficient to meet the transfer rate requirements, the transfer bandwidth of the PCIe link is throttled to obtain the throttled PCIe link. Based on the link transmission status of the PCIe link after throttling, the cache space of the solid-state drive is layered to obtain a layered cache structure. The cache space includes a low-jitter sub-cache area, a high-jitter sub-cache area, a regular-cycle sub-cache area, and an irregular-cycle sub-cache area; The steps for constructing the hierarchical cache structure include: Based on the difference in transmission characteristics between the low-jitter sub-buffer and the high-jitter sub-buffer, the data interaction threshold between the two buffers is analyzed to obtain the cross-buffer transmission triggering condition. Based on the cross-buffer transmission triggering condition, the independent transmission channels of the two buffers are configured to obtain the buffer isolation mechanism. Based on the differences in task characteristics between the regular periodic sub-cached area and the irregular periodic sub-cached area, the resource contention risk of the two cache areas is analyzed to obtain the resource conflict assessment result. Based on the resource conflict assessment result, the priorities of the two cache areas are divided to obtain the cache area priorities. Based on the buffer isolation mechanism and the buffer priority, the collaborative response strategy of the low-jitter sub-buffer and the regular periodic sub-buffer is analyzed to obtain the synchronization processing rules. Based on the synchronization processing rules, the advance time for the low-jitter sub-buffer to prepare associated data when the regular periodic sub-buffer triggers a periodic task is determined to obtain the linkage scheduling result. Based on the linkage scheduling results, the emergency handling mechanism of the high jitter sub-buffer and the irregular periodic sub-buffer is optimized to obtain a burst response scheme. Based on the burst response scheme, a preset proportion of cache space is reserved in each of the two buffers to construct the layered cache structure. Based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, the transferable tasks in each cache layer are determined, and the transferable tasks of each cache layer are migrated to the target cache area to obtain the cache layout after task migration. If the second data transmission rate of the PCIe link after the throttling is detected to meet the transmission rate requirement, then based on the second data transmission rate and the cache layout, the working mode of each component in the solid-state drive is adjusted to reduce the power consumption of the solid-state drive. The steps for adjusting the operating modes of the various components in the solid-state drive include: Based on the stability and fluctuation range of the second data transmission rate, the theoretical optimal operating frequency range of each component at the second data transmission rate is determined. Based on the data read / write frequency and data access pattern of each cache layer in the cache layout, the actual workload distribution of each component when processing cache data is analyzed. Based on the theoretical optimal operating frequency range and actual workload distribution of each component, determine the degree of deviation between the current operating mode and the optimal state of each component. The current working mode of each component is adjusted based on the degree of state deviation, resulting in the adjusted working mode of each component.

2. The solid-state drive power consumption optimization method according to claim 1, characterized in that, The components include flash memory chips; the steps for adjusting the operating mode based on the degree of state deviation include: Based on the degree of state deviation of the flash memory chip, the matching degree between the number of active read and write units of the flash memory chip in the current working mode and the actual needs is identified, and the read and write unit configuration deviation result is obtained. Based on the read and write unit configuration deviation result, continuously idle read and write units are merged into a sleep group to obtain the dynamic grouping result of read and write units. Based on the dynamic grouping results of the read and write units, the hibernation triggering conditions of the read and write units in the hibernation group are analyzed to obtain hibernation control parameters. Based on the hibernation control parameters, the power supply voltage of the read and write units in the hibernation group is adjusted to the preset standby level to obtain the voltage regulation result. Based on the voltage regulation results, the operating status of the flash memory chip is analyzed to determine the difference in erase and write frequencies in different memory blocks, thereby obtaining the memory block usage intensity distribution. Based on the memory block usage intensity distribution, tasks of memory blocks with usage intensity greater than a preset intensity threshold are transferred to memory blocks with usage intensity less than or equal to the preset intensity threshold, thus obtaining the memory block rotation scheduling result. The garbage collection triggering mechanism of the flash memory chip is updated based on the storage block rotation scheduling result, and the garbage collection frequency is adjusted based on the garbage collection triggering mechanism.

3. The solid-state drive energy consumption optimization method according to claim 1, characterized in that, The components include a main control chip; the steps for adjusting the operating mode based on the degree of state deviation include: Based on the state deviation degree of the main control chip, the load balancing status of the core computing unit of the main control chip in the current working mode is detected, the core load distribution result is obtained, and based on the core load distribution result, the data verification function is migrated from the main core to the idle auxiliary core, and the core function decomposition result is obtained. Based on the core function breakdown results, the processing time ratio of different task types is statistically analyzed to obtain the task time distribution. Based on the task time distribution, tasks with priority lower than the preset priority threshold are replaced by batch processing scheduling algorithm instead of real-time scheduling algorithm to obtain scheduling algorithm switching results. Based on the switching results of the scheduling algorithm, the communication interval pattern between the main control chip and other components (excluding itself) is analyzed to obtain the communication cycle characteristics. Based on the communication cycle characteristics, the interface clock frequency is adjusted to a preset operating level during the communication gap to obtain the interface clock frequency adjustment result. Based on the interface clock frequency adjustment results, the instruction queue structure of the main control chip is optimized to obtain the target instruction buffer mechanism, and the instruction prefetch strategy is adjusted based on the target instruction buffer mechanism.

4. The solid-state drive power consumption optimization method according to claim 1, characterized in that, The components include a cache chip; The steps for adjusting the operating mode based on the degree of state deviation include: The cache chip's hit rate difference in the current cache partition is evaluated based on the state deviation of the cache chip to obtain the partition efficiency result. Based on the partition efficiency result, the storage space allocation of partitions with a hit rate lower than a preset value is reduced to obtain the cache space remapping result. Based on the cache space remapping results, the access interval duration of different data blocks is analyzed to obtain the data activity cycle; and based on the data activity cycle, the refresh interval of inactive data blocks is extended to obtain the cache refresh mechanism modification results. Based on the cache refresh mechanism modification result, the bank conflict frequency inside the cache chip is detected to obtain the bank contention result; based on the bank contention result, the access interval of the conflicting bank is increased to obtain the memory interleaving parameter adjustment result; Based on the results of the memory interleaving parameter adjustment, the idle state determination condition of the cache chip is analyzed to obtain the idle detection rule, and the low-power mode switching is performed based on the idle detection rule.

5. The solid-state drive energy consumption optimization method according to any one of claims 1 to 4, characterized in that, The process of performing a layered operation on the cache space of the solid-state drive based on the link transmission status of the PCIe link after throttling, to obtain a layered cache structure, includes: Based on the length of the data transmission continuity parameter in the link transmission state, the cache space of the solid-state drive is divided into a continuous transmission cache area and a non-continuous transmission cache area. Based on the magnitude of the transmission jitter parameter in the link transmission state, the continuous transmission buffer is divided into a low jitter sub-buffer and a high jitter sub-buffer. Based on the regularity of the transmission period parameters in the link transmission state, the discontinuous transmission buffer is divided into a regular period sub-buffer and an irregular period sub-buffer. The hierarchical cache structure is constructed based on the low-jitter sub-cache area, the high-jitter sub-cache area, the regular-period sub-cache area, and the irregular-period sub-cache area.

6. A solid-state drive power consumption optimization device, characterized in that, Applied to the solid-state drive power consumption optimization method as described in any one of claims 1 to 5; The solid-state drive power consumption optimization device includes: The link throttling module is used to throttle the transmission bandwidth of the PCIe link if the first data transfer rate of the PCIe link between the solid-state drive and the host is found to be insufficient to meet the transmission rate requirements, so as to obtain the throttled PCIe link. The cache space tiering module is used to perform tiering operations on the cache space of the solid-state drive based on the link transmission status of the PCIe link after throttling, so as to obtain a tiered cache structure. The task migration module is used to determine the migrateable tasks in each cache layer based on the data storage status of each cache layer in the hierarchical cache structure and the task execution status of the solid-state drive, and migrate the migrateable tasks of each cache layer to the target cache area to obtain the cache layout after task migration. The working mode adjustment module is used to adjust the working mode of each component in the solid-state drive based on the second data transmission rate and the cache layout if the second data transmission rate of the PCIe link after the throttling is detected to meet the transmission rate requirement, so as to reduce the power consumption of the solid-state drive.

7. An electronic device, comprising: Memory, used to store computer software programs; A processor for reading and executing the computer software program, characterized in that, when the processor executes the computer software program, it implements the solid-state drive power consumption optimization method as described in any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium, wherein a computer software program is stored therein, characterized in that, When the computer software program is executed by the processor, it implements the solid-state drive power consumption optimization method as described in any one of claims 1 to 5.

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