Method, system, device and medium for improving computing performance stability of hardware platform

Abstract

This invention provides a method, system, device, and medium for improving the computing performance stability of a hardware platform, belonging to the field of computer system performance optimization technology. The method includes: acquiring architectural characteristic data of the underlying hardware platform through hardware detection tools, and generating and loading a first-level system kernel parameter configuration based on the architectural characteristic data; reading the architectural characteristic data, performing behavioral analysis and type identification on running processes based on the architectural characteristic data, and generating a second-level process scheduling strategy accordingly; reading cache structure information from the architectural characteristic data, driving intelligent prefetching of the file system and reconstructing the storage layout of memory data based on the cache structure information; continuously collecting performance indicator stream data during system operation, performing real-time analysis of the performance indicator stream data using a performance degradation model, and generating feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy.

Description

Technical Field

[0001] This invention belongs to the field of computer system performance optimization technology, and more specifically relates to a method, system, device and medium for improving the stability of computing performance on a hardware platform. Background Technology

[0002] In high-intensity computing scenarios such as scientific computing, financial modeling, and large-scale data analysis, the long-term stability of the computing system's output performance is a crucial foundation for ensuring task success rates and result accuracy. However, on some hardware platforms employing non-mainstream architectures or specific instruction sets, the standardized Linux operating system often faces the challenge of fluctuating computing performance, manifested as abnormal fluctuations in processor core utilization and unstable memory access latency. This performance instability is particularly pronounced during long-duration, full-load tasks, potentially leading to job timeouts or introducing systematic errors due to the uncertainty of processing time.

[0003] A deeper reason for these problems lies in the incompatibility between the default resource management strategy of the general-purpose Linux kernel and the microarchitecture of specific hardware platforms. The standard kernel's scheduling algorithm, cache model, and memory management mechanism are primarily optimized for mainstream homogeneous multi-core architectures, failing to adequately adapt to the specific characteristics of certain platforms in terms of physical core topology, cache coherence protocols, and Non-Unified Memory Access (NUMA) design. For example, the default process scheduler may not effectively perceive the performance differences between different computing units within the processor, leading to unintended migration of critical computing threads between heterogeneous cores, disrupting cache locality, and consequently causing a decrease in computational pipeline efficiency and severe fluctuations in memory subsystem response time.

[0004] Current industry optimization practices largely focus on empirical tuning of general Linux kernel parameters or localized patching for individual applications. These methods lack a systematic analysis and modeling of the underlying hardware microarchitecture characteristics, failing to construct a closed-loop optimization system that encompasses hardware feature awareness, system resource scheduling, and dynamic runtime feedback. Therefore, existing technologies struggle to fundamentally resolve the underlying performance instability introduced by hardware architecture differences, and cannot meet the stringent requirements of high-end applications for consistent computing performance output.

[0005] Therefore, there is an urgent need in this field for an innovative approach that can deeply understand the details of hardware architecture and achieve system-level closed-loop dynamic optimization to fill the gaps in existing technologies in ensuring the stability of high-performance computing tasks. Summary of the Invention

[0006] To address the above problems, the present invention aims to provide a method, system, device, and medium for improving the stability of computing performance on a hardware platform. By adjusting hardware characteristic adaptation parameters, optimizing process scheduling, optimizing caching mechanisms, and implementing performance monitoring and dynamic adjustment, the system software is optimized to stabilize computing performance evaluation results and meet the needs of various applications with high requirements for computing performance stability.

[0007] To achieve the above objectives, the present invention employs the following technical solution: In a first aspect, embodiments of this application provide a method for improving the stability of computing performance on a hardware platform, comprising: The architecture characteristics data of the underlying hardware platform are obtained through hardware detection tools, and the first-level system kernel parameter configuration is generated and loaded based on the architecture characteristics data. Read architecture characteristic data, perform behavior analysis and type identification on running processes based on the architecture characteristic data, and generate a second-level process scheduling strategy accordingly; Read the cache structure information from the architecture characteristic data, and drive the file system to intelligently prefetch and reconstruct the storage layout of memory data based on the cache structure information; The system continuously collects performance indicator stream data during system operation, performs real-time analysis of the performance indicator stream data using a performance degradation model, and generates feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy.

[0008] In an optional implementation, the step of obtaining the architecture characteristic data of the underlying hardware platform through hardware detection tools, and generating and loading the first-level system kernel parameter configuration based on the architecture characteristic data, includes: By executing a hardware detection script, the system interfaces / proc / cpuinfo and / proc / meminfo are read and parsed to generate a structured hardware description file. The hardware description file records the CPU's physical core topology, multi-level cache size and correlation, as well as memory channel and bandwidth information. The hardware description file is taken as input, and a set of optimized kernel tunable parameters are generated by the configuration policy engine. The kernel tunable parameters include intel_pstate or acpi_cpufreq driver parameters for CPU affinity and power management, and vm.swappiness parameters for controlling page swapping tendency. The kernel adjustable parameters are made effective by using sysctl or by directly writing to the / proc / sys interface, thus forming the first-level system kernel parameter configuration.

[0009] In an optional implementation, the step of reading architectural characteristic data, performing behavioral analysis and type identification on running processes based on the architectural characteristic data, and generating a second-level process scheduling strategy accordingly includes: The hardware description file is received by the process profiler in the kernel. By statically analyzing the symbol table of the process binary file and dynamically sampling its system call sequence, a type identifier is marked for the process. The type identifier includes compute-intensive and I / O-intensive processes. The type identifier is received through the Full Fair Scheduler and used as an input variable for the scheduling weight; For processes marked as computationally intensive, their weight values ​​are multiplied by a weight factor greater than 1, and their threads are preferentially bound to physical cores for execution based on the CPU's physical core topology.

[0010] In an optional implementation, the step of reading architectural characteristic data, performing behavioral analysis and type identification on running processes based on the architectural characteristic data, and generating a second-level process scheduling strategy accordingly, further includes: The type identifier is received through the block device I / O scheduling layer, and the I / O request queue depth of each process is monitored; when the queue depth of a process marked as I / O intensive continuously exceeds the first threshold, a scheduling policy switching event is generated. In response to the scheduling policy switching event, by sending a message to / sys / block / <device>Write the scheduler name to the / queue / scheduler file, switch the I / O scheduler for the corresponding block device from the multi-queue bfq to the low-latency none or mq-deadline, and assign high priority to the I / O requests of that process.

[0011] In an optional implementation, the step of reading the cache structure information from the architecture characteristic data, and driving the file system's intelligent prefetching and reconstructing the storage layout of memory data based on the cache structure information includes: The system receives memory capacity information from the hardware description file through the virtual file system layer and initializes an adaptive prefetcher accordingly. The adaptive prefetcher is used to identify the access pattern of the application by analyzing the file access sequence. When a sequential access pattern is identified and the system free memory is higher than the safety threshold calculated from the memory capacity information, an asynchronous prefetch operation is initiated to load subsequent data blocks into the page cache in advance. The kernel memory management subsystem receives CPU cache line size information from the hardware description file and performs forced address alignment allocation based on the CPU cache line size information when requesting memory for critical kernel data structures or applications through a preset interface, to ensure that a single data structure can exclusively occupy a cache line.

[0012] In one optional implementation, the continuous collection of performance metric stream data during system operation, and the real-time analysis of the performance metric stream data using a performance degradation model, includes: The built-in performance data collector collects low-level hardware performance events at fixed time intervals. These low-level hardware performance events include at least processor core stall cycles, last-level cache miss rate, and memory controller request queue depth. The raw data of the low-level hardware performance events is obtained by reading the perf_event interface and the / proc file system. After standardization processing, a time-stamped performance metric sequence is generated and written to the time-series database. Load the historical performance index sequence during normal operation from the time series database, use it as a benchmark, and train a normal performance range model using machine learning algorithms; During the real-time operation phase, the latest performance index sequence collected by the performance data collector is compared with the normal performance range model, a quantified performance deviation score is output, and the abnormal index that contributes the most is identified, generating a list of abnormal indicators.

[0013] In an optional implementation, the step of generating feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy includes: Read the performance deviation score and the list of abnormal indicators; when the performance deviation score continuously exceeds a preset threshold, start the built-in executor to generate system tuning instructions based on the list of abnormal indicators and a predefined indicator and action mapping rule table; By using the dynamic tuning executor to execute system tuning commands through the / sys and / proc file system interfaces, the system parameters during operation can be adjusted. The adjustment of system parameters during operation includes: If the list of abnormal indicators indicates that the last-level cache miss rate is too high, then a dynamic adjustment of the memory allocation strategy is triggered, expanding the scope of the forced address alignment allocation operation and applying it to the kernel data structure or anonymous memory region of user-mode process with an access frequency greater than a preset frequency threshold. If the list of abnormal indicators indicates an abnormal percentage of processor core idle cycles, then a signal is sent to the process scheduler to dynamically increase the weight factor value of the computationally intensive process.

[0014] Secondly, embodiments of this application also provide a system for improving the stability of hardware platform computing performance, including: Hardware feature adaptation parameter adjustment is used to obtain the architecture feature data of the underlying hardware platform through hardware detection tools, and generate and load the first-level system kernel parameter configuration based on the architecture feature data; The process scheduling optimization module is used to read architecture characteristic data, perform behavior analysis and type identification on running processes based on the architecture characteristic data, and generate a second-level process scheduling strategy accordingly. The caching mechanism optimization module is used to read the cache structure information in the architecture characteristic data, drive the file system to intelligently prefetch based on the cache structure information, and reconstruct the storage layout of memory data. The performance monitoring and dynamic adjustment module is used to continuously collect performance indicator stream data during system operation, perform real-time analysis of the performance indicator stream data using a performance degradation model, and generate feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy.

[0015] Thirdly, embodiments of this application also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method for improving the computing performance stability of the hardware platform as described in any of the above.

[0016] Fourthly, embodiments of this application also provide a storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the method for improving the computing performance stability of the hardware platform as described in any of the above claims.

[0017] As can be seen from the above technical solutions, the present invention has the following advantages: The method for improving the computing performance stability of the hardware platform provided in this application achieves a systematic improvement in computing performance stability by constructing a full-stack optimization system that ranges from hardware characteristic awareness to system resource scheduling. It generates precise kernel parameters and scheduling strategies through deep adaptation to the hardware architecture and forms a dynamic closed-loop control based on real-time performance monitoring and machine learning models. This effectively smooths out CPU utilization fluctuations and memory access latency, significantly enhancing the output consistency and reliability of the system under long-term high-load tasks, thereby meeting the stringent requirements for high performance and stability in scenarios such as scientific computing.

[0018] This application achieves a high degree of synergy between system software and underlying hardware through in-depth exploration of specific hardware architectures and customization of kernel parameters. This effectively solves performance bottlenecks caused by software-hardware mismatches, allowing the hardware's potential to be fully realized. For example, in scientific computing scenarios, this technology significantly improves the accuracy of computation results and the predictability of task completion time.

[0019] This application utilizes an intelligent scheduling algorithm and cache optimization mechanism based on application characteristics to achieve precise allocation of system resources. By differentiating between computationally intensive and I / O-intensive tasks and implementing differentiated scheduling strategies, resource contention and waiting latency are significantly reduced, ensuring stable performance for various applications in a multi-task concurrent environment.

[0020] This application achieves real-time perception and adaptive optimization of system status through performance metric stream analysis and machine learning model prediction. When performance deviations are detected, the system can automatically trigger parameter adjustments, effectively responding to scenarios such as sudden load changes and ensuring the long-term reliability of the system.

[0021] All optimizations in this application are implemented at the system's underlying level, fully maintaining compatibility with standard API interfaces. Upper-layer applications can enjoy the benefits of improved performance and stability without any modifications, greatly reducing deployment costs and the barrier to entry.

[0022] This application organically combines multiple levels, including hardware detection, resource scheduling, cache management, and dynamic adjustment, forming a complete optimization chain from hardware characteristic awareness to software resource management. This full-stack collaborative design enables the system to maintain stable high-performance output under different workloads, meeting the needs of application scenarios with extremely high requirements for computational stability. Attached Figure Description

[0023] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating the method for improving the computing performance stability of the hardware platform provided in this application.

[0025] Figure 2 A schematic diagram of the structure of the system for improving the computing performance stability of the hardware platform provided in this application.

[0026] Figure 3 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0027] The various embodiments of this disclosure will be described more fully in the following detailed steps of methods for improving the computing performance stability of hardware platforms. This disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of this disclosure to the specific embodiments disclosed herein, but rather this disclosure should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of this disclosure.

[0028] In the following, the terms "comprising" or "may include" as used in the various embodiments of this disclosure indicate the presence of the disclosed functions, operations, or elements, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in the various embodiments of this disclosure, the terms "comprising," "having," and their cognates are intended only to indicate a particular feature, number, step, operation, element, component, or combination of the foregoing, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing, or the possibility of adding one or more combinations of features, numbers, steps, operations, elements, components, or combinations of the foregoing.

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Please see Figure 1 The diagram shows a flowchart of a method for improving the computing performance stability of a hardware platform in a specific embodiment. The method includes: S1: Obtain the architecture characteristics data of the underlying hardware platform through hardware detection tools, and generate and load the first-level system kernel parameter configuration based on the architecture characteristics data.

[0031] In a specific implementation, an automated hardware detection script is first executed. This script uses system tools such as lscpu and lstopo to deeply parse the cpuinfo file in the proc filesystem, accurately obtaining the CPU's physical core topology, including the size and relationships of each core's L1, L2, and L3 caches. Simultaneously, by parsing the meminfo file and using the dmidecode tool, it comprehensively obtains the memory capacity, operating frequency, number of channels, and bandwidth characteristics. All extracted hardware information is then structured and stored as a JSON-formatted hardware profile file, hardware_profile.json.

[0032] Subsequently, the parameter configuration tool is launched to read the hardware description file and perform parameter mapping through the built-in intelligent rule engine. For the Phytium processor's unique dual-core cluster architecture, the tool automatically generates corresponding CPU affinity parameters to guide the system in rationally allocating processes with different load characteristics to different computing core clusters. For Loongson processors with large L2 or L3 caches, the tool recommends appropriately increasing the dirty page ratio thresholds such as `vm.dirty_ratio` and `vm.dirty_background_ratio` to fully utilize cache space. Simultaneously, based on the detected high memory bandwidth characteristics, the system-wide `vm.swappiness` parameter value is appropriately reduced from the default 60 to 10-30, effectively reducing unnecessary memory and disk swapping operations.

[0033] Finally, the generated optimized kernel parameters take effect in two ways: one is that the system administrator manually reviews them and then loads them in batches using the sysctl command; the other is that after confirmation by the tool, the parameters are automatically written to the etc sysctl.d configuration directory or directly to the corresponding node under proc sys, and the configuration takes effect immediately by executing the sysctl command, forming a complete first-level system kernel parameter configuration.

[0034] S2: Read architecture characteristic data, perform behavior analysis and type identification on running processes based on the architecture characteristic data, and generate a second-level process scheduling strategy accordingly.

[0035] In a specific implementation, this step constructs an intelligent process classification and scheduling mechanism to achieve optimal allocation of computing resources. The specific implementation includes: A process profiling module is added to the process creation logic within the kernel scheduling code. When a new process is created via the fork or exec system call, the profiler statically analyzes the symbol table characteristics of its binary file, checks whether it links to mathematical computation libraries such as libm and libblas, and dynamically samples its initial runtime system call sequence to monitor for frequent read or write system calls. Based on this comprehensive analysis of characteristics, the kernel labels processes with computationally intensive or I / O-intensive type identifiers.

[0036] For identified computationally intensive processes, a type check is added to the weight calculation logic of the Completely Fair Scheduler, multiplying its scheduling weight `se.load.weight` by a weight boost factor of 1.5. Simultaneously, based on the obtained CPU physical core topology information, the `sched_setaffinity` system call is used to preferentially bind the process thread to a physical core for execution, avoiding the use of hyper-threaded logical cores and ensuring that the computational task receives continuous and stable processing resources.

[0037] For I / O-intensive processes, the system establishes a monitoring mechanism at the block device I / O scheduling layer to continuously track the I / O request queue depth of each process. When the queue depth of an I / O-intensive process is detected to be greater than 32 for five consecutive sampling periods, a scheduling policy switching event is automatically generated. In response to this event, the kernel writes the scheduler name to the sysblock device queuescheduler file, switches the default bfq scheduler to mqdeadline, and calls the ioprio_set system call to assign the process's I / O requests a high priority of IOPRIO_CLASS_BE level 0, ensuring timely response to I / O operations.

[0038] S3: Read the cache structure information in the architecture characteristic data, and drive the file system to intelligently prefetch and reconstruct the storage layout of memory data based on the cache structure information.

[0039] In a specific implementation, on the one hand, the virtual file system layer initializes the adaptive prefetcher based on the memory capacity information in the hardware description file, setting a dynamic safety threshold that the system's free memory must be greater than 20% of the total capacity. When it detects that applications such as data analysis are frequently and sequentially reading large files in a specific directory, the prefetcher starts kswapd or a dedicated prefetch thread if the memory safety condition is met. This thread accurately predicts the next 1MB data block and other potentially accessed file regions based on the current file's read offset and historical access patterns, and asynchronously prefetches the data into the page cache via the readahead system call.

[0040] Meanwhile, the SLAB or SLUB allocator in the kernel memory management subsystem receives CPU cache line size information. When allocating memory for critical kernel data structures such as `task_struct` and `inode`, or for user-space applications requesting memory through the `posix_memalign` interface, the allocator adds alignment logic to the `kmalloc` or `kmem_cache_alloc` functions. This logic ensures that the starting address of the allocated memory is strictly aligned to the cache line size and that the size of critical data structures is adapted to the cache line boundaries, thereby effectively eliminating the false sharing problem during concurrent access by multiple cores and significantly improving the CPU cache hit rate.

[0041] S4: Continuously collect performance indicator stream data during system operation, perform real-time analysis of the performance indicator stream data using a performance degradation model, and generate feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy.

[0042] In this specific implementation, this step establishes a complete closed-loop feedback system to achieve intelligent regulation of system performance. The specific implementation includes: Deploy the performance monitoring daemon perfd, developed in C or Python. This process runs in a multi-threaded architecture and collects low-level hardware events such as processor core idle cycles and last-level cache miss rates every 5 seconds via the perf_event_open system call. Simultaneously, it reads system files such as proc stat, proc meminfo, and proc diskstats to obtain performance metrics such as CPU utilization, memory read / write speed, and disk I / O rate. The collected raw data is standardized to generate a timestamped sequence of performance metrics, which is then stored in a time-series database such as an InfluxDB instance or a memory circular buffer.

[0043] The system routinely initiates a model training process daily, using Python and the scikit-learn machine learning framework to train a model with normal performance range based on historical stable performance data from a time-series database. The Isolation Forest algorithm is employed to learn the multidimensional distribution characteristics of normal performance metrics and establish a performance benchmark. During real-time operation, the daemon process inputs the latest collected performance metric sequences into the trained model. The model outputs a performance deviation score quantized from 0 to 1 and identifies the most contributing anomalous metrics, such as abnormally high last-level cache miss rates, generating a detailed list of anomalous metrics.

[0044] When the dynamic adjustment executor detects that the performance deviation score exceeds the threshold of 0.8 for three consecutive cycles, it generates system tuning instructions based on a predefined indicator action mapping rule table. If the abnormal indicator list indicates an excessively high last-level cache miss rate, it expands the scope of forced address alignment allocation by writing relevant parameters to the proc sys vm or calling the memory management subsystem interface. If it indicates an abnormal percentage of processor core idle cycles, it dynamically increases the scheduling weight of compute-intensive processes through real-time signals or netlink sockets. Through this intelligent closed-loop control mechanism, the system can automatically and precisely correct performance fluctuations, continuously maintaining a stable state of computational performance.

[0045] In this embodiment, by automatically detecting hardware architecture characteristics and generating customized kernel parameters, the system's underlying layer achieves deep integration with the hardware platform. Differentiated scheduling strategies are implemented based on intelligently identified process types, ensuring that computationally intensive and I / O-intensive tasks are allocated appropriately. Intelligent prefetching and data layout optimization, combined with memory capacity and cache characteristics, effectively eliminate I / O bottlenecks and cache failures. Finally, through machine learning-driven real-time monitoring and dynamic feedback control, a closed-loop management mechanism for early detection, precise localization, and rapid response to performance issues is formed, thereby significantly improving task execution efficiency, result accuracy, and system reliability in high-performance application scenarios such as scientific computing.

[0046] like Figure 2 As shown, the following are embodiments of a hardware platform computing performance stability improvement system provided in this disclosure. This system and the hardware platform computing performance stability improvement methods described above belong to the same inventive concept. For details not described in detail in the embodiments of the hardware platform computing performance stability improvement system, please refer to the embodiments of the hardware platform computing performance stability improvement methods described above.

[0047] A system for improving the stability of computing performance on a hardware platform, comprising: Hardware feature adaptation parameter adjustment is used to obtain the architecture feature data of the underlying hardware platform through hardware detection tools, and generate and load the first-level system kernel parameter configuration based on the architecture feature data.

[0048] The process scheduling optimization module is used to read architecture characteristic data, perform behavior analysis and type identification on running processes based on the architecture characteristic data, and generate a second-level process scheduling strategy accordingly.

[0049] The caching mechanism optimization module is used to read the cache structure information in the architecture characteristic data, drive the file system to intelligently prefetch based on the cache structure information, and reconstruct the storage layout of memory data.

[0050] Performance monitoring and dynamic adjustment are used to continuously collect performance indicator stream data during system operation, perform real-time analysis of the performance indicator stream data using a performance degradation model, and generate feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy.

[0051] The hardware platform computing performance stability improvement system provided in this embodiment achieves a systematic improvement in computing performance stability by constructing a full-stack optimization system from hardware characteristic awareness to system resource scheduling. This is achieved through deep adaptation to specific hardware architectures to generate precise kernel parameters, intelligent scheduling and caching optimization based on application characteristics to achieve precise resource allocation, and the establishment of a dynamic closed-loop control mechanism driven by real-time monitoring and machine learning to cope with load changes, while maintaining complete system compatibility without modifying upper-layer applications. Ultimately, this significantly improves task execution efficiency, result accuracy, and system reliability in high-performance scenarios such as scientific computing, effectively meeting the application requirements for extremely high computing stability.

[0052] Figure 3 A schematic diagram of the hardware structure of an electronic device for implementing various embodiments of the present invention.

[0053] The method for improving the computing performance stability of a hardware platform provided in this application can be applied to electronic devices. Those skilled in the art will understand that the electronic device structure involved in the embodiments of this invention does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. In the embodiments of this invention, electronic devices include, but are not limited to, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of this application described and / or claimed herein.

[0054] Electronic devices may include processors, external memory interfaces, internal memory, universal serial bus (USB) interfaces, charging management modules, power management modules, batteries, wireless communication modules, audio modules, speakers, microphones, sensor modules, buttons, cameras, displays, and SIM card interfaces, etc.

[0055] A processor may include one or more processing units, such as: a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0056] The processor can serve as the nerve center and command center of an electronic device. The controller can generate operation control signals based on the instruction opcode and timing signals to control the fetching and execution of instructions.

[0057] The processor may also include memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to use the instruction or data again, it can retrieve it directly from this memory. This avoids repeated accesses, reduces processor latency, and thus improves system efficiency.

[0058] An external storage interface (ESI) can be used to connect external memory cards, such as microSD cards, to expand the storage capacity of electronic devices. The external memory card communicates with the processor through the ESI to perform data storage functions, such as saving music and video files on the external memory card.

[0059] Internal memory can be used to store computer executable program code, which includes instructions. The processor executes various functional applications and data processing of electronic devices by running the instructions stored in internal memory. Internal memory can include a program storage area and a data storage area. Internal memory can include high-speed random access memory, and can also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc.

[0060] Wireless communication functionality in electronic devices can be achieved through antennas, wireless communication modules, modem processors, and baseband processors.

[0061] Wireless communication modules can provide solutions for wireless communication applications in electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies.

[0062] Electronic devices can implement audio functions through audio modules, speakers, receivers, microphones, headphone jacks, and application processors.

[0063] Electronic devices can achieve shooting functions through ISPs, cameras, video codecs, GPUs, displays, and application processors.

[0064] Electronic devices can achieve display functions through GPUs, displays, and application processors.

[0065] A GPU is a microprocessor for image processing, connected to the display screen and application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering. A processor may include one or more GPUs, which execute program instructions to generate or modify display information.

[0066] A display screen is used to display images, videos, etc. A display screen includes a display panel.

[0067] The aforementioned electronic device realizes the method for improving the computing performance stability of the hardware platform of this application by constructing a full-stack optimization system covering deep hardware feature adaptation, intelligent resource scheduling, cache optimization, and dynamic closed-loop control based on machine learning. This achieves a comprehensive and beneficial effect, including significantly improving the system's computing performance stability, enhancing task execution timeliness and result accuracy, ensuring reliable operation under multi-load environments, and maintaining full compatibility with upper-layer applications.

[0068] The storage medium provided in this application stores a program product that enables methods to improve the stability of computing performance on a hardware platform.

[0069] Methods to improve the stability of hardware platform computing performance include: The architecture characteristics data of the underlying hardware platform are obtained through hardware detection tools, and the first-level system kernel parameter configuration is generated and loaded based on the architecture characteristics data. Read architecture characteristic data, perform behavior analysis and type identification on running processes based on the architecture characteristic data, and generate a second-level process scheduling strategy accordingly; Read the cache structure information from the architecture characteristic data, and drive the file system to intelligently prefetch and reconstruct the storage layout of memory data based on the cache structure information; The system continuously collects performance indicator stream data during system operation, performs real-time analysis of the performance indicator stream data using a performance degradation model, and generates feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy.

[0070] In some possible implementations, the method for improving the computing performance stability of the hardware platform disclosed herein can be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0071] The storage medium disclosed herein may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0072] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.< / device>

Claims

1. A method for improving the stability of computing performance on a hardware platform, characterized in that, include: The architecture characteristics data of the underlying hardware platform are obtained through hardware detection tools, and the first-level system kernel parameter configuration is generated and loaded based on the architecture characteristics data. The system reads architectural characteristic data, performs behavioral analysis and type identification on running processes based on this data, and generates a second-level process scheduling policy accordingly. This includes: receiving hardware description files through a process profiler in the kernel; statically analyzing the symbol table of the process binary file and dynamically sampling its system call sequence to label processes with type identifiers; these type identifiers include compute-intensive and I / O-intensive processes; receiving the type identifiers through the Completely Fair Scheduler (CFS) and using them as an input variable for scheduling weights; for processes labeled as compute-intensive, multiplying their weight value by a weight factor greater than 1, and prioritizing binding their threads to physical cores based on the CPU's physical core topology; receiving the type identifiers through the block device I / O scheduling layer and monitoring the I / O request queue depth of each process; generating a scheduling policy switching event when the queue depth of a process labeled as I / O-intensive continuously exceeds a first threshold; and responding to the scheduling policy switching event by sending a message to / sys / block / <device> Write the scheduler name to the / queue / scheduler file, switch the I / O scheduler of the corresponding block device from the multi-queue bfq to the low-latency none or mq-deadline, and assign high priority to the I / O requests of the process.< / device> Read the cache structure information from the architecture characteristic data, and drive the file system to intelligently prefetch and reconstruct the storage layout of memory data based on the cache structure information; The system continuously collects performance indicator stream data during system operation, performs real-time analysis on the performance indicator stream data using a performance degradation model, and generates feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy. The continuous acquisition of performance metric stream data during system operation, and the real-time analysis of the performance metric stream data using a performance degradation model, includes: The built-in performance data collector collects low-level hardware performance events at fixed time intervals. These low-level hardware performance events include at least processor core stall cycles, last-level cache miss rate, and memory controller request queue depth. The raw data of the low-level hardware performance events is obtained by reading the perf_event interface and the / proc file system. After standardization processing, a time-stamped performance metric sequence is generated and written to the time-series database. Load the historical performance index sequence during normal operation from the time series database, use it as a benchmark, and train a normal performance range model using machine learning algorithms; During the real-time operation phase, the latest performance index sequence collected by the performance data collector is compared with the normal performance range model, a quantified performance deviation score is output, and the abnormal index that contributes the most is identified, generating a list of abnormal indicators.

2. The method for improving the computing performance stability of a hardware platform according to claim 1, characterized in that, The step of obtaining the architecture characteristic data of the underlying hardware platform through hardware detection tools, and generating and loading the first-level system kernel parameter configuration based on the architecture characteristic data, includes: By executing a hardware detection script, the system interfaces / proc / cpuinfo and / proc / meminfo are read and parsed to generate a structured hardware description file. The hardware description file records the CPU's physical core topology, multi-level cache size and correlation, as well as memory channel and bandwidth information. The hardware description file is taken as input, and a set of optimized kernel tunable parameters are generated by the configuration policy engine. The kernel tunable parameters include intel_pstate or acpi_cpufreq driver parameters for CPU affinity and power management, and vm.swappiness parameters for controlling page swapping tendency. The kernel adjustable parameters are made effective by using sysctl or by directly writing to the / proc / sys interface, thus forming the first-level system kernel parameter configuration.

3. The method for improving the computing performance stability of a hardware platform according to claim 1, characterized in that, The step of reading the cache structure information from the architecture characteristic data, and using the cache structure information to drive intelligent prefetching of the file system and reconstruct the storage layout of memory data includes: The system receives memory capacity information from the hardware description file through the virtual file system layer and initializes an adaptive prefetcher accordingly. The adaptive prefetcher is used to identify the access pattern of the application by analyzing the file access sequence. When a sequential access pattern is identified and the system free memory is higher than the safety threshold calculated from the memory capacity information, an asynchronous prefetch operation is initiated to load subsequent data blocks into the page cache in advance. The kernel memory management subsystem receives CPU cache line size information from the hardware description file and performs forced address alignment allocation based on the CPU cache line size information when requesting memory for critical kernel data structures or applications through a preset interface, to ensure that a single data structure can exclusively occupy a cache line.

4. The method for improving the computing performance stability of a hardware platform according to claim 1, characterized in that, The step of generating feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy includes: Read the performance deviation score and the list of abnormal indicators; when the performance deviation score continuously exceeds a preset threshold, start the built-in executor to generate system tuning instructions based on the list of abnormal indicators and a predefined indicator and action mapping rule table; By using the dynamic tuning executor to execute system tuning commands through the / sys and / proc file system interfaces, the system parameters during operation can be adjusted. The adjustment of system parameters during operation includes: If the list of abnormal indicators indicates that the last-level cache miss rate is too high, then a dynamic adjustment of the memory allocation strategy is triggered, expanding the scope of the forced address alignment allocation operation and applying it to the kernel data structure or anonymous memory region of user-mode process with an access frequency greater than a preset frequency threshold. If the list of abnormal indicators indicates an abnormal percentage of processor core idle cycles, then a signal is sent to the process scheduler to dynamically increase the weight factor value of the computationally intensive process.

5. A system for improving the stability of computing performance on a hardware platform, characterized in that, The system employs the method for improving the computing performance stability of the hardware platform as described in any one of claims 1 to 4; The system includes: Hardware feature adaptation parameter adjustment is used to obtain the architecture feature data of the underlying hardware platform through hardware detection tools, and generate and load the first-level system kernel parameter configuration based on the architecture feature data; The process scheduling optimization module is used to read architecture characteristic data, perform behavior analysis and type identification on running processes based on the architecture characteristic data, and generate a second-level process scheduling strategy accordingly. The caching mechanism optimization module is used to read the cache structure information in the architecture characteristic data, drive the file system to intelligently prefetch based on the cache structure information, and reconstruct the storage layout of memory data. The performance monitoring and dynamic adjustment module is used to continuously collect performance indicator stream data during system operation, perform real-time analysis of the performance indicator stream data using a performance degradation model, and generate feedback control instructions based on the analysis results to dynamically correct the first-level system kernel parameter configuration and the second-level process scheduling strategy.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method for improving the computing performance stability of the hardware platform as described in any one of claims 1 to 4.

7. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for improving the computing performance stability of the hardware platform as described in any one of claims 1 to 4.

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