Power integrity repair method, device and storage medium

Abstract

The application discloses a power integrity repair method, device and storage medium, and belongs to the technical field of semiconductors. The power integrity repair method comprises the following steps: acquiring layout power distribution network data, performing voltage drop analysis and electromigration analysis, and generating voltage drop distribution data and electromigration hotspot data; identifying an intersection region in adjacent metal layers as a candidate punching region, wherein the intersection region meets a minimum punching rule and is associated with a voltage drop difference value and an electromigration value; for each candidate region, when the region has no through hole, calculating a maximum number of through holes based on the voltage drop difference value, and when the region already has a through hole, calculating a maximum number of through holes based on the electromigration value; and performing a through hole adding operation according to the calculation results to generate optimized layout data. The application dynamically determines the number of through holes through collaborative analysis of the voltage drop and the electromigration, improves the power integrity, reduces the influence of parasitic parameters, ensures the process reliability and prevents the antenna effect, and realizes comprehensive optimization of the power network.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a power integrity repair method, apparatus, and storage medium. Background Technology

[0002] Currently, most integrated circuit designs employ automated via-drilling optimization technology, which uses computer-aided design software to automatically add vias in the metal-layer intersection areas of the power network. However, this approach has three major drawbacks: First, it blindly generates a large number of redundant vias, introducing unnecessary parasitic capacitances. Second, high via density can lead to etching process defects (such as bridging or incomplete etching). Third, the charge accumulation in vias can exacerbate the antenna effect. These defects can lead to increased chip power consumption, decreased yield, and reliability risks. Existing solutions (such as manual inspection or fixed rule constraints) cannot effectively avoid redundant via problems while ensuring power integrity. Summary of the Invention

[0003] This application provides a power integrity repair method, apparatus, and storage medium, aiming to solve problems such as increased parasitic capacitance, process defects, and antenna effects caused by redundant holes in the drilling technology.

[0004] Firstly, a power integrity restoration method is provided, including:

[0005] Obtain power distribution network data from the map;

[0006] Voltage drop analysis and electromigration analysis are performed on the power distribution network data to obtain voltage drop distribution data containing voltage drop differences in each region and electromigration hotspot data with labeled electromigration values.

[0007] The intersecting regions in adjacent metal layers that meet the preset minimum drilling rules and have associated voltage drop difference and electromigration value are identified from the power distribution network data as candidate drilling regions.

[0008] For each candidate punching region, a punching rule is determined based on the voltage drop difference and the electromigration value. The punching rule is as follows: when there are no through holes in the candidate punching region, the maximum number of through holes is calculated based on the voltage drop difference; when there are already through holes in the candidate punching region, the maximum number of through holes is calculated based on the electromigration value.

[0009] Perform a via addition operation based on the maximum number of vias to generate optimized layout data.

[0010] Secondly, a power integrity restoration device is also provided, comprising:

[0011] The data acquisition module is configured to acquire power distribution network data in the layout.

[0012] The analysis module is configured to perform voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data including voltage drop differences in each region and electromigration hotspot data with labeled electromigration values.

[0013] The candidate region identification module is configured to identify, from the power distribution network data, intersecting regions in adjacent metal layers that meet the preset minimum drilling rule and have associated voltage drop difference and electromigration value as candidate drilling regions.

[0014] The drilling rule determination module is configured to determine the drilling rule for each candidate drilling area based on the voltage drop difference and the electromigration value. The drilling rule is as follows: when there are no through holes in the candidate drilling area, the maximum number of through holes is calculated based on the voltage drop difference; when there are already through holes in the candidate drilling area, the maximum number of through holes is calculated based on the electromigration value.

[0015] The via optimization module is configured to perform a via addition operation based on the maximum number of vias, and generate optimized layout data.

[0016] Thirdly, a computer-readable storage medium is also provided, on which a computer program is stored, the computer program being loaded by a processor to perform the steps of the power integrity restoration method described in any one of the first aspects.

[0017] Beneficial effects:

[0018] This application effectively solves the technical problem caused by blindly adding vias in traditional power network repair by using intelligent dynamic via rules: First, it dynamically determines the maximum number of vias in each candidate region based on voltage drop difference and electromigration value, avoiding blindly adding vias based on experience and fundamentally eliminating the problem of increased parasitic capacitance caused by redundant vias; Second, by identifying candidate regions that meet the preset minimum via rules and have associated electrical parameters, it ensures that newly added vias are located in electrically sensitive areas, avoiding process risks caused by drilling vias in unnecessary locations; Finally, for regions without vias, the number of vias is calculated based on the voltage drop difference to ensure the necessity of adding vias; for regions with existing vias, the number of new vias is calculated based on electromigration value to prevent local current density from exceeding the limit; the dual constraint mechanism effectively controls the via density and reduces the occurrence rate of antenna effects. Furthermore, the preset minimum via rules already include process design rules (such as minimum spacing, size, etc.), ensuring that the generated via layout meets manufacturing process requirements and avoiding process defects caused by improper design.

[0019] Therefore, this application dynamically determines the number of vias through the synergistic analysis of voltage drop and electromigration, which improves power integrity, reduces the impact of parasitic parameters, ensures process reliability, and prevents antenna effects, thus achieving comprehensive optimization of the power network. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating a power integrity restoration method provided in some embodiments of this application;

[0022] Figure 2 This is a schematic diagram illustrating the determination of drilling rules provided in some embodiments of this application;

[0023] Figure 3 This is a schematic diagram of a drilling solution provided by existing technology;

[0024] Figure 4 This is one of the schematic diagrams of the drilling scheme provided in this application;

[0025] Figure 5 This is the second schematic diagram of the drilling scheme provided in this application;

[0026] Figure 6 This is a structural block diagram of a power integrity repair device provided in some embodiments of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0030] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0031] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0032] In integrated circuit power integrity design, vias are a key technology for connecting power networks across different metal layers. Their importance lies primarily in three aspects: First, vias effectively reduce the parasitic resistance of the power distribution network. By reducing IR drop (ΔV = I × R) through multi-level parallel conduction, transistors can obtain a stable supply voltage. Second, a reasonable via layout can balance current distribution, avoiding electromigration (EM) effects caused by excessively high local current density, thus improving chip reliability. Finally, vias enable three-dimensional interconnect optimization of the power network, constructing low-impedance power supply paths with limited wiring resources. However, traditional indiscriminate vias can lead to redundant vias, increasing parasitic capacitance, worsening antenna effects, and causing process defects (such as incomplete etching).

[0033] Based on this, this application dynamically determines the optimal number of vias through voltage drop and electromigration synergistic analysis. That is, it uses electrical characteristic-driven drilling rules to replace traditional empirical drilling, which improves power integrity, reduces the impact of parasitic parameters, ensures process reliability, and prevents antenna effects, thus achieving comprehensive optimization of the power network.

[0034] On the one hand, this embodiment provides a power integrity restoration method, such as Figure 1 As shown, it includes:

[0035] S101: Obtain power distribution network data in the layout.

[0036] Understandably, power distribution network (PDN) data refers to the geometric and electrical parameters of the power network (PDN) extracted from the integrated circuit layout design system. Specifically, this includes: 1) Physical structure data: metal layer interconnect topology, power / ground line width and spacing, existing via locations and sizes, and other layout geometric information; 2) Electrical characteristic data: parasitic resistance (R) and parasitic capacitance (C) parameters extracted based on process documents (such as interconnect process technology format files ITF / library exchange format files LEF); 3) Design constraint data: manufacturing constraints such as minimum drilling rules (e.g., minimum via size and spacing), metal layer stacking relationships, etc.

[0037] S102: Perform voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data containing voltage drop differences in each region and electromigration hotspot data with labeled electromigration values.

[0038] For example, step S102 includes: extracting parasitic resistance and capacitance parameters of the metal interconnects in the layout; performing power distribution network simulation based on the parasitic resistance and capacitance parameters to obtain the voltage and current density values ​​of all electrical nodes; defining the difference between the voltage value and a preset nominal power supply voltage as a voltage drop difference, and generating the voltage drop distribution data through spatial interpolation; converting the current density value into an electromigration value, and marking electrical nodes exceeding the maximum allowable electromigration value as electromigration hotspots to form the electromigration hotspot data. The voltage drop distribution data and electromigration hotspot data are used for subsequent identification of candidate punching areas.

[0039] Understandably, the voltage drop (IR Drop) and electromigration (EM) analysis in step S102 refers to the quantitative evaluation of the power network through the following process: First, extract the parasitic resistance (R) and parasitic capacitance (C) parameters of the metal interconnects from the layout (based on ITF / LEF process files) and input them into simulation tools such as Ansys Totem or Cadence Voltus_FI; Second, perform power distribution network (PDN) simulation under the conditions of applying operating current and nominal voltage (e.g., VDD = 1.2V) to generate the voltage values ​​(V_actual) and current densities (J) of all electrical nodes on the entire chip; Next, calculate the difference between the voltage of each electrical node and the nominal value δV = V_nominal - V_actual, and form a global voltage drop distribution heatmap through spatial interpolation techniques (e.g., Kriging algorithm) to generate the voltage drop distribution data.

[0040] Simultaneously, the current density value J of each node is obtained through power distribution network simulation; when the node current density exceeds the maximum allowable value of the process (J>J_max, such as J_max=1mA / μm), the current density value J is determined. 2 When the current density exceeds the limit (EM = (J - J_max) / J_max × 100%), the node is marked as an electromigration hotspot. The current density exceedance rate of the electromigration hotspot (EM = (J - J_max) / J_max × 100%) is used as the electromigration value, and the hotspot coordinates and EM value are recorded to form structured electromigration hotspot data. The structured data (δV distribution and EM hotspot coordinates) output by this step provides a decision-making basis for subsequent hole drilling, thereby achieving accurate localization of power network problems, avoiding the risk of missed detections in traditional manual inspection, and replacing empirical rules with quantitative simulation.

[0041] S103: Identify intersecting regions in adjacent metal layers that meet the preset minimum drilling rules and have associated voltage drop difference and electromigration value from the power distribution network data as candidate drilling regions.

[0042] For example, step S103 includes: determining whether the intersecting area between metal layers belongs to the overlapping area of ​​the same electrical node; determining whether the area of ​​the overlapping area meets the minimum drilling size requirement of the process; determining whether the distance between the overlapping area and the existing through hole meets the design rule requirements; when all the determinations are positive, the intersecting area is determined as a candidate drilling area.

[0043] It should be noted that selecting intersecting regions that meet all conditions as candidate drilling regions means that the following three conditions must be met simultaneously: 1) Electrical node consistency condition. Detect overlapping regions belonging to the same electrical node in adjacent metal layers (e.g., Metal1 and Metal2 are both connected to the same power network VDD at layout coordinates (x,y)). Exclude overlapping regions of different electrical nodes (e.g., the intersection of VDD and GND). 2) Manufacturability condition. Exclude regions with an overlapping area smaller than the preset minimum drilling size (e.g., if the process rule requires a via size ≥0.1μm×0.1μm, then the overlapping area must be ≥0.01μm). 2 3) Design rule compliance conditions. Verify that the spacing between the remaining area and the existing through holes conforms to the preset design rules (e.g., through hole spacing must be ≥0.05μm, and the spacing between through holes and metal edges must be ≥0.03μm). Prevent short circuits or reliability issues caused by non-compliant spacing.

[0044] Understandably, the candidate punching region identification in step S103 is a key step in achieving accurate positioning through multi-dimensional condition filtering: firstly, based on physical verification tools such as Calibre, adjacent metal layers (such as...) are detected. Figure 2 The diagram shows geometrically overlapping regions (i.e., electrically connected regions) belonging to the same power node (e.g., net1, while net2 is a different metal structure) within adjacent metal layers (e.g., yellow and blue metal layers). Then, process constraint filtering is performed to eliminate regions with overlapping areas smaller than the minimum via size defined in the process document (LEF) (e.g., 0.1μm × 0.1μm) to ensure manufacturability. Next, spacing rule verification is performed to check whether the spacing between the remaining regions and existing metal structures (e.g., the metal lines in net2) meets design rules (e.g., minimum via spacing = 0.05μm) to avoid bridging defects caused by excessive density. The final retained regions must be correlated with the voltage drop difference (δV) and electromigration value (EM) data generated in step S102 to form candidate drilling regions that meet both electrical requirements and process compliance. Figure 2The red diagonal stripe area is shown. For example, a candidate area must satisfy δV>0.3%VDD and EM>80%J_max. This step replaces traditional indiscriminate drilling with a triple screening mechanism (electrical connectivity → process dimensions → spacing rules), avoiding redundant holes from the source and ensuring that newly added vias are precisely applied to areas with IR drop / EM problems.

[0045] S104: For each candidate punching area, a punching rule is determined based on the voltage drop difference and the electromigration value. The punching rule is that when there are no through holes in the candidate punching area, the maximum number of through holes is calculated based on the voltage drop difference; when there are already through holes in the candidate punching area, the maximum number of through holes is calculated based on the electromigration value.

[0046] For example, step S104 includes: for areas without vias, multiplying the ratio of the voltage drop difference to a preset voltage drop safety threshold by a preset process correction coefficient to obtain the maximum number of vias; for areas with existing vias, multiplying the ratio of the measured electromigration value to a preset electromigration threshold by a preset electromigration correction coefficient to obtain the maximum number of vias; wherein the maximum number of vias is not less than the minimum number of vias required by the process. The drilling rules are used to guide subsequent via addition operations.

[0047] Understandably, the core of the dynamic drilling rule proposed in step S104 lies in distinguishing the initial state of the candidate region (whether there is a through hole) and adopting a differentiated calculation strategy:

[0048] 1) IR Drop Strategy in Through-Hole Regions. By quantifying the voltage drop difference δV between adjacent metal layers (e.g., Layer M2 = 1.18V vs Layer M3 = 1.15V → δV = |1.18V - 1.15V| = 30mV) and the voltage drop safety threshold Threshold_V set by the process (if the design VDD = 1.2V, Threshold_V is set to 0.5% VDD, then Threshold_V = 1.2V × 0.5% = 6mV), the through-hole requirement base is calculated proportionally, and then multiplied by the process correction factor k_v (e.g., k_v is set to 1.2-1.5 to compensate for the impact of photolithography on the yield of the multi-hole array). For example, when δV / Threshold_V=30mV / 6mV=5 and k_v=1.3, 6.5 (i.e. 5×1.3) vias are generated (rounded up to 7). At the same time, the final maximum number of vias must meet the minimum number of vias required in the Design Rule Manual (DRM). Taking TSMC's 7nm process as an example, its metal interconnect layer design rules clearly require that any valid connection must contain at least 2 vias (i.e. N_min≥2).

[0049] 2) EM strategy for existing via regions. First, extract the electromigration value (EM) of the current via in the candidate region. The electromigration value (EM) is the current density exceedance rate obtained through power network simulation (calculation formula: EM = (J_measured - J_max) / J_max × 100%), where J_max is the maximum allowable current density defined in the process document (e.g., 1 mA / μm). 2 Next, the electromigration value (EM) is compared with a preset electromigration threshold (Threshold_EM, e.g., 100%) (EM / Threshold_EM) to quantify the severity of the current electromigration risk. For example, if EM = 150%, the ratio is 150% / 100% = 1.5; if EM = 80%, the ratio is 80% / 100% = 0.8. Finally, the above ratio is multiplied by the electromigration correction factor k_em (this electromigration correction factor k_em is determined by process reliability requirements, e.g., k_em ≥ 1) to obtain the theoretical maximum number of vias. Simultaneously, the minimum number of vias in the process must also be met (e.g., the design rulebook requires per μm). 2 (At least 2 through holes) to avoid violations of hole spacing regulations.

[0050] For example, suppose a candidate region has the following parameters: EM = 120%, Threshold_EM = 100%, k_em = 1.2, and the minimum number of vias required by the process is N_min = 3; then:

[0051] Theoretical value: 1.2 × (120% / 100%) = 1.44, rounded up to 2;

[0052] Final value: max(2,3) = 3 (meets the minimum process requirements).

[0053] Therefore, step S104 serves to intelligently calculate the number of vias based on IR Drop (voltage drop difference) for areas without vias, and dynamically adjust the number of vias based on electromigration (EM) risk for areas with vias to avoid redundant vias; it controls the upper limit of vias by the ratio of the voltage drop threshold and the EM threshold, while forcibly meeting the minimum number of vias required by the process, balancing performance and reliability; and it automatically calculates vias using formulaic rules (e.g., no-via formula: k_v*δV / Threshold_V, with-via formula: k_em*EM / Threshold_EM), replacing manual experience judgment and reducing the number of design iterations.

[0054] S105: Perform a via addition operation based on the maximum number of vias to generate optimized layout data.

[0055] For example, step S105 includes: when the calculated maximum number of vias is lower than the minimum number of vias required by the process, the via size is reduced proportionally before adding them; when the calculated maximum number of vias is not lower than the minimum number of vias required by the process, standard via size and spacing are used for adding them; after performing the via addition operation, optimized layout data is generated. The optimized layout data is used for subsequent design rule checks and electrical rule checks.

[0056] Understandably, step S105 involves intelligent via addition based on dynamically calculated maximum via quantity. If the calculated value is lower than the minimum process quantity (e.g., design rules require at least two vias per area), the via size is proportionally reduced (e.g., diameter reduced by 20%) to meet the quantity requirement and avoid violating design rules. When the calculated value meets or exceeds the minimum quantity, standard via sizes and spacings defined in the process library (e.g., 0.1μm diameter, 0.2μm spacing) are directly used for via addition, ensuring connection reliability. Through flexible size adjustment, IR drop / EM repair requirements are precisely matched while meeting process constraints, avoiding redundancy or insufficiency issues caused by "fixed-size drilling" in existing technologies.

[0057] In other words, through-hole addition is performed based on the dynamically calculated maximum number of through-holes (N_max), which is divided into two scenarios: when N_max < the minimum number of through-holes in the process (N_min), the through-hole size is reduced to match the quantity requirement; when N_max ≥ N_min, through-holes are added according to the standard size / spacing.

[0058] For example, suppose the calculated N_max = 1 (because EM = 80%, Threshold_EM = 100%, k_em = 1.2 → rounded to 0.96), while the process requires N_min = 2 (per μm). 2 (At least 2 vias); standard via diameter D = 0.1 μm, spacing P = 0.2 μm. Therefore: proportionally reduce the size, such as reducing the via diameter to D' = 0.07 μm; add 2 smaller vias to meet the quantity requirement while maintaining current carrying capacity (J_max constraint). This avoids triggering DRC errors due to insufficient via count, and the parasitic capacitance of the smaller vias is reduced.

[0059] For example, suppose the calculated N_max = 4 (rounded down from δV = 2%, Threshold_V = 0.5%, k_v = 1.0 → 4.0), and the process requirement is N_min = 2; standard via parameters: D = 0.1μm, P = 0.2μm. Then: adding vias according to standard rules, i.e., evenly distributing 4 vias (0.2μm spacing) in the intersecting area. This maximizes the current path, alleviates the voltage drop problem, and does not introduce redundant vias.

[0060] In some embodiments, the power integrity restoration method further includes: after performing a via addition operation, performing a design rule check to verify whether the via spacing and the distance between the via and the metal edge meet process requirements; and performing an electrical rule check to verify whether the via current density and the metal line current density exceed the process upper limit; when violations are found, for violations of the design rule check, maintaining the original number of vias and adjusting the position of the violating vias to meet the minimum spacing requirements; for violations of the electrical rule check, increasing the number of vias or increasing the width of the connecting metal lines to reduce the current density below the safety threshold; the results of the design rule check and the electrical rule check are used to update the optimized layout data to make it meet process requirements and electrical safety standards. The check results are used to update the optimized layout data so that the power integrity restoration meets design requirements.

[0061] Understandably, after adding dynamic vias, a dual verification process is performed: 1) Design Rule Check (DRC). Verify that the via spacing (Via-to-Via) and via-to-metal distance (Via-to-Metal) comply with the process documentation (e.g., TSMCN28 DRC Rule). If violations are found, adjust the non-compliant vias by position shifting (keeping the total number unchanged) to avoid etching defects; 2) Electrical Rule Check (ERC). Detect whether the via / metal line current density exceeds the limit (e.g., >1mA / μm). 2 If the current density is exceeded, the number of through holes or the metal wires can be increased to reduce the current density.

[0062] In some other embodiments, the power integrity repair method further includes: establishing a layout change record table to record via coordinates, dimensions, change types, and their corresponding voltage drop improvement rates and electromigration risk levels; the layout change record table is used as reference data for subsequent iterative optimization.

[0063] Understandably, by establishing a structured layout change log table, the technical parameters and optimization effects of each via operation can be fully tracked. For example, the log content includes: 1) Geometric attributes: via coordinates (e.g., (X,Y)=(10.2μm,5.7μm)), dimensions (e.g., diameter 0.1μm→0.07μm); 2) Change type: distinguishing between addition, scaling, or shift operations; 3) Performance indicators: quantifying voltage drop improvement rate (e.g., IR Drop reduced by 35%) and electromigration risk level (e.g., EM from high→medium). This enables traceable optimization, guiding subsequent via drilling strategies through historical data; and it also verifies the effectiveness of the k_v / k_em correction coefficient (e.g., if the log table shows that the EM risk still exceeds the limit when k_em=1.2 in a certain area, then it will be adjusted to 1.5 in the next iteration).

[0064] In some other specific examples, the power integrity repair method further includes: after performing the via addition operation, re-performing voltage drop analysis and electromigration analysis on the power distribution network data; when the analysis results do not meet the preset power integrity design requirements, iteratively executing the power integrity repair method until the optimized layout data meets the requirements.

[0065] Understandably, after adding vias, the following process is used to ensure the effectiveness of power integrity restoration: 1) Secondary verification. Using simulation tools (such as Cadence Voltus), the optimized power network is re-analyzed for IR Drop and EM to verify whether it meets design requirements (e.g., voltage drop ≤ 2%, EM ≤ 100%); 2) Iterative optimization. If the analysis results are unsatisfactory (e.g., EM in a certain area is still 120%), the dynamic via-punching process is executed again based on the new layout data (e.g., determining via-punching rules) until all constraints are met. For example, if a power network still has a local IR Drop of 3% (threshold 2%) after the first restoration, the system automatically triggers secondary via-punching, increasing the number of vias from 3 to 5 by increasing the k_v coefficient, ultimately reducing the IR Drop to 1.8%.

[0066] Please refer to Figures 3-5 . Figure 3 This indicates that in existing technology, under low current conditions, there are two through holes before optimization, but redundant holes appear after automatic drilling (marked in red). This demonstrates the defect of "redundancy generated by automatic drilling" in existing technology, which may lead to problems such as etching defects and antenna effects. Figure 4 This application's technical solution, also targeting scenarios with low current, is consistent with existing technologies before optimization. However, after automatic drilling, the number of through-holes is not increased, maintaining the original two through-holes. This indicates that this application, based on dynamic calculations (such as voltage drop differences or electromigration values), avoids the addition of redundant holes, thus solving the redundant hole problem in existing technologies. Figure 5 The technical solution of this application indicates that, under high current scenarios, there were two vias before optimization, and the number of vias increased after automatic drilling. This demonstrates that this application can reasonably increase the number of vias according to actual conditions (such as high electromigration risk or large voltage drop under high current) and rules (such as calculating the maximum number of vias based on electromigration values ​​and not less than the minimum number of vias required by the process) to meet power integrity requirements, reflecting the advantage of this application in "dynamic optimization, balancing performance and reliability".

[0067] Through the above Figures 3-5 The scenario comparison intuitively demonstrates the technical characteristics of this application compared to the prior art, which can avoid redundant vias and reasonably optimize the number of vias as needed under different current conditions, thereby achieving power integrity repair.

[0068] In summary, this application proposes a dynamically constrained power integrity repair method. Through joint analysis of voltage drop (IRDrop) and electromigration (EM), it intelligently determines via rules in intersecting power network regions: for regions without vias, it dynamically calculates the maximum number of vias based on the voltage drop difference; for regions with existing vias, it adjusts the number of vias based on electromigration values ​​and enforces minimum via constraints (such as TSMC DRC rules). Its advantages include: avoiding redundant vias and reducing parasitic capacitance in existing technologies through dynamic constraints of both voltage drop and EM (such as k_v*δV / Threshold_V and k_em*EM / Threshold_EM formulas); automated via rules replacing manual inspection, reducing the number of iterations; and adapting to different process nodes (such as 7nm and 28nm) with k_v / k_em correction coefficients, addressing the lack of customized rules in existing technologies.

[0069] On the other hand, such as Figure 6 As shown, this embodiment provides a power integrity repair device, including a data acquisition module 601, an analysis module 602, a candidate region identification module 603, a hole drilling rule determination module 604, and a through-hole optimization module 605.

[0070] For example, the data acquisition module 601 is configured to acquire power distribution network data in the layout.

[0071] For example, the analysis module 602 is configured to perform voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data including voltage drop differences in each region and electromigration hotspot data with labeled electromigration values.

[0072] For example, the candidate region identification module 603 is configured to identify intersecting regions in adjacent metal layers that meet the preset minimum drilling rules and have associated voltage drop difference and electromigration value as candidate drilling regions from the power distribution network data.

[0073] For example, the drilling rule determination module 604 is configured to determine the drilling rule for each candidate drilling area based on the voltage drop difference and the electromigration value. The drilling rule is that when there are no through holes in the candidate drilling area, the maximum number of through holes is calculated based on the voltage drop difference; when there are already through holes in the candidate drilling area, the maximum number of through holes is calculated based on the electromigration value.

[0074] For example, the via optimization module 605 is configured to perform a via addition operation based on the maximum number of vias to generate optimized layout data.

[0075] This embodiment also provides a computer-readable storage medium storing a computer program thereon, which is loaded by a processor to perform the steps in the power integrity repair method described in any of the above embodiments.

[0076] In the embodiments of this application, the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0078] The above provides a detailed description of a power integrity repair method, apparatus, and storage medium provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power integrity restoration method, characterized in that, include: Obtain power distribution network data from the map; Voltage drop analysis and electromigration analysis are performed on the power distribution network data to obtain voltage drop distribution data containing voltage drop differences in each region and electromigration hotspot data with labeled electromigration values. The intersecting regions in adjacent metal layers that meet the preset minimum drilling rules and have associated voltage drop difference and electromigration value are identified from the power distribution network data as candidate drilling regions. For each candidate punching region, a punching rule is determined based on the voltage drop difference and the electromigration value. The punching rule is as follows: when there are no through holes in the candidate punching region, the maximum number of through holes is calculated based on the voltage drop difference; when there are already through holes in the candidate punching region, the maximum number of through holes is calculated based on the electromigration value. Perform a via addition operation based on the maximum number of vias to generate optimized layout data.

2. The power integrity restoration method according to claim 1, characterized in that, The voltage drop analysis and electromigration analysis performed on the power distribution network data to obtain voltage drop distribution data containing voltage drop differences in each region and electromigration hotspot data with labeled electromigration values ​​include: Extract the parasitic resistance and parasitic capacitance parameters of the metal interconnects in the layout; Based on the parasitic resistance parameters and the parasitic capacitance parameters, a power distribution network simulation is performed to obtain the voltage and current density values ​​of all electrical nodes. The difference between the voltage value and the preset nominal power supply voltage value is defined as the voltage drop difference, and the voltage drop distribution data is generated by spatial interpolation. The current density value is converted into an electromigration value, and electrical nodes that exceed the maximum electromigration value allowed by the process are marked as electromigration hotspots, thus forming the electromigration hotspot data.

3. The power integrity restoration method according to claim 1, characterized in that, The process of determining the drilling rules for each candidate drilling region based on the voltage drop difference and the electromigration value includes: For areas without vias, the maximum number of vias is obtained by multiplying the ratio of the voltage drop difference to the preset voltage drop safety threshold by a preset process correction coefficient. For an existing via region, the maximum number of vias is obtained by multiplying the ratio of the measured electromigration value to the preset electromigration threshold by a preset electromigration correction coefficient. The maximum number of through holes shall not be less than the minimum number of through holes required by the process.

4. The power integrity restoration method according to claim 1, characterized in that, The step of identifying intersecting regions in adjacent metal layers that meet the preset minimum drilling rule and have associated voltage drop difference and electromigration value as candidate drilling regions from the power distribution network data includes: Determine whether the intersecting areas between metal layers belong to the overlapping areas of the same electrical node; Determine whether the area of ​​the overlapping region meets the minimum drilling size requirement of the process; Determine whether the distance between the overlapping area and the existing through hole meets the design requirements; When all the judgments are positive, the intersecting region is determined as a candidate punching region.

5. The power integrity restoration method according to claim 1, characterized in that, The step of performing a via addition operation based on the maximum number of vias to generate optimized layout data includes: When the calculated maximum number of through holes is lower than the minimum number of through holes required by the process, the through hole size is reduced proportionally before adding them; When the calculated maximum number of through holes is not less than the minimum number of through holes required by the process, standard through hole size and spacing shall be used for addition; After performing the via addition operation, optimized layout data is generated.

6. The power integrity restoration method according to claim 1, characterized in that, Also includes: After performing the through-hole addition operation, perform a design rule check to verify that the through-hole spacing and the distance between the through-hole and the metal edge meet the process requirements. In addition, electrical rule checks are performed to verify whether the via current density and metal line current density exceed the process limits; When violations are found during inspection, for violations of the design rules, the original number of vias is maintained, and the positions of the non-compliant vias are adjusted to meet the minimum spacing requirements; for violations of the electrical rules, the number of vias is increased or the width of the connecting metal line is increased to reduce the current density below the safety threshold. The results of the design rule check and electrical rule check are used to update the optimized layout data.

7. The power integrity restoration method according to claim 1, characterized in that, Also includes: Establish a layout change record table to record via coordinates, dimensions, change type, and corresponding voltage drop improvement rate and electromigration risk level; wherein, the layout change record table is used as reference data for subsequent iterative optimization.

8. The power integrity restoration method according to claim 1, characterized in that, Also includes: After performing the via addition operation, voltage drop analysis and electromigration analysis were performed again on the power distribution network data; When the analysis results do not meet the preset power integrity design requirements, the power integrity repair method described in any one of claims 1-7 is iteratively executed until the optimized layout data meets the requirements.

9. A power integrity restoration device, characterized in that, include: The data acquisition module is configured to acquire power distribution network data in the layout. The analysis module is configured to perform voltage drop analysis and electromigration analysis on the power distribution network data to obtain voltage drop distribution data including voltage drop differences in each region and electromigration hotspot data with labeled electromigration values. The candidate region identification module is configured to identify, from the power distribution network data, intersecting regions in adjacent metal layers that meet the preset minimum drilling rule and have associated voltage drop difference and electromigration value as candidate drilling regions. The drilling rule determination module is configured to determine the drilling rule for each candidate drilling area based on the voltage drop difference and the electromigration value. The drilling rule is as follows: when there are no through holes in the candidate drilling area, the maximum number of through holes is calculated based on the voltage drop difference; when there are already through holes in the candidate drilling area, the maximum number of through holes is calculated based on the electromigration value. The via optimization module is configured to perform a via addition operation based on the maximum number of vias to generate optimized layout data.

10. A computer-readable storage medium, characterized in that, It stores a computer program, which is loaded by a processor to perform the steps of the method according to any one of claims 1-8.

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