Non-volatile memory and method of data erasure thereof

Abstract

Embodiments of the present application disclose a non-volatile memory and a data erasing method. The memory comprises a plurality of memory cell strings, each of which comprises a selected gate transistor and a memory cell connected in series. The method comprises: applying a step erase voltage with a stepped rising voltage waveform to a memory cell string to be subjected to an erasing operation; during the step erase voltage rising from a middle level to a peak level, raising a voltage of the selected gate transistor from a starting level to a predetermined peak level, and raising a voltage of a predetermined region from a starting level to a predetermined peak level, so as to generate a gate-induced drain leakage current in the memory cell string, the predetermined region being adjacent to the selected gate transistor and comprising at least one memory cell. By applying a bias voltage to the selected gate transistor and the predetermined region adjacent to the selected gate transistor, the gate-induced drain leakage current can be generated in a channel of the memory cell string, so as to effectively erase data.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202111323249.2, filed on November 5, 2021, entitled "Non-volatile memory and data erasure method thereof". Technical Field

[0002] This application relates to the field of semiconductor technology, and more specifically, to a non-volatile memory and a method for erasing data from a non-volatile memory. Background Technology

[0003] Recently, non-volatile memories with "vertically" (i.e., in three-dimensional (3D)) stacked memory cells have been widely used in electronic devices. These typically consist of multiple vertically stacked levels (e.g., a top and bottom level in a non-volatile memory formed using a double-stack process), with multiple vertically stacked memory cells present in each level. To efficiently read, write, and erase in a non-volatile memory with multiple levels, each level can be erased individually.

[0004] Furthermore, as the number of stacked layers in non-volatile memory continues to increase, the connection method at the bottom of its channel layer has evolved from the traditional selective epitaxial structure to lateral interconnection and the latest bottom interconnection method. Forming a highly doped semiconductor layer at the bottom (typically with the same type of doping as the channel layer) to connect the channel layer has become the mainstream method for fabricating non-volatile memory. However, non-volatile memory obtained based on this method is not suitable for body erasure. Therefore, gate-induced drain leakage (GIDL) is needed to generate an auxiliary body bias voltage to assist in the layer-level erasure operation and achieve data erasure of the non-volatile memory.

[0005] Therefore, how to achieve efficient non-volatile memory level erase operations and gate-induced drain leakage erase operations is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] To address or partially address the aforementioned or other problems, various embodiments of the present application, which will be further described below, are proposed.

[0007] One aspect of this application provides a data erasure method for a non-volatile memory, the memory including a plurality of memory cell strings, each memory cell string being formed on a well-doped region of a substrate and including a selected gate transistor and a memory cell connected in series, the method including: applying a stepped erase voltage to the memory cell string to be erased, the stepped erase voltage having a stepped rising voltage waveform; and during the period when the stepped erase voltage rises from its intermediate level to its peak level, increasing the voltage of the selected gate transistor from its initial level to its predetermined peak level, and increasing the voltage of a predetermined region from its initial level to its predetermined peak level, thereby generating a gate-induced drain leakage current in the memory cell string, wherein the predetermined region is adjacent to the selected gate transistor and includes at least one of the memory cells.

[0008] According to one embodiment of this application, the select gate transistor includes a top-level select gate transistor connected to the bit line and a bottom-level select gate transistor connected to the well doped region; and the predetermined region includes at least a first predetermined region and a second predetermined region, wherein the first predetermined region is adjacent to the bottom-level select gate transistor and includes at least one of the memory cells, and the second predetermined region is adjacent to the top-level select gate transistor and includes at least one of the memory cells.

[0009] According to one embodiment of this application, raising the voltage of the select gate transistor from its initial level to its predetermined peak level and raising the voltage of a predetermined region from its initial level to its predetermined peak level includes: raising the voltage of a predetermined region of the memory cell string from its initial level to its peak level during the period of raising the voltage of the select gate transistor from its initial level to its peak level.

[0010] According to one embodiment of this application, increasing the voltage of the select gate transistor from its initial level to its predetermined peak level and increasing the voltage of a predetermined region from its initial level to its predetermined peak level includes: while increasing the voltage of the select gate transistor from its initial level to its peak level, simultaneously increasing the voltage of a predetermined region of the memory cell string from its initial level to its peak level, and the peak level of the select gate transistor is equal to the peak level of the predetermined region.

[0011] According to one embodiment of this application, increasing the voltage of the select gate transistor from its initial level to its predetermined peak level and increasing the voltage of a predetermined region from its initial level to its predetermined peak level includes: after the voltage of the select gate transistor is increased from its initial level, increasing the voltage of a predetermined region of the memory cell string from its initial level.

[0012] According to one embodiment of this application, the memory cell includes a true memory cell and a pseudo memory cell, the first predetermined region being adjacent to the underlying select gate transistor and including at least one of the first pseudo memory cells.

[0013] According to one embodiment of this application, the pseudo memory cell includes a first pseudo memory cell located between the underlying selected gate transistor and the well doped region, wherein at least one first pseudo memory cell is spaced between the first predetermined region and the substrate.

[0014] According to one embodiment of this application, the method further includes setting at least one of the first pseudo-memory cells used for spacing to a floating state during the erase operation.

[0015] According to one embodiment of this application, the method further includes: applying the step erase voltage to at least one of the first pseudo memory cells used for spacing.

[0016] According to one embodiment of this application, the memory cell includes a true memory cell and a pseudo memory cell, the pseudo memory cell including a selection level pseudo memory cell adjacent to the selection gate transistor, and the method further includes: during the period when the step erase voltage rises from its intermediate level to its peak level, increasing the voltage of the selection level pseudo memory cell from its initial level to its peak level.

[0017] According to one embodiment of this application, the method further includes: increasing the voltage of the selected level pseudo memory cell from its initial level to its peak level while increasing the voltage of the selected gate transistor from its initial level to its predetermined peak level.

[0018] According to one embodiment of this application, the method further includes: simultaneously increasing the voltage of the selected gate transistor from its initial level to its predetermined peak level; or, after the voltage of the selected gate transistor has increased from its initial level, increasing the voltage of the selected level pseudo memory cell from its initial level.

[0019] According to one embodiment of this application, raising the voltage of the select gate transistor from its initial level to its predetermined peak level and raising the voltage of a predetermined region from its initial level to its predetermined peak level includes: raising the voltage of the first predetermined region from its initial level to its peak level while raising the voltage of the bottom select gate transistor from its initial level to its peak level; and raising the voltage of the second predetermined region from its initial level to its peak level while raising the voltage of the top select gate transistor from its initial level to its peak level.

[0020] According to one embodiment of this application, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of the predetermined region from its starting level to its predetermined peak level includes: raising the voltage of the first predetermined region from its starting level after raising the voltage of the bottom select gate transistor from its starting level; and raising the voltage of the second predetermined region from its starting level to its predetermined peak level while raising the voltage of the top select gate transistor from its starting level to its predetermined peak level, wherein the predetermined peak level of the top select gate transistor is equal to the predetermined peak level of the second predetermined region.

[0021] According to one embodiment of this application, raising the voltage of the select gate transistor from its starting level to its predetermined peak level and raising the voltage of a predetermined region from its starting level to its predetermined peak level includes: raising the voltage of the bottom select gate transistor from its starting level to its predetermined peak level while raising the voltage of the first predetermined region from its starting level to its predetermined peak level, and the predetermined peak level of the bottom select gate transistor is equal to the predetermined peak level of the first predetermined region; and raising the voltage of the second predetermined region from its starting level after the voltage of the top select gate transistor has been raised from its starting level.

[0022] According to one embodiment of this application, raising the voltage of the select gate transistor from its initial level to its predetermined peak level and raising the voltage of a predetermined region from its initial level to its predetermined peak level includes: simultaneously raising the voltage of the bottom select gate transistor from its initial level to its predetermined peak level, raising the voltage of the first predetermined region from its initial level to its peak level, and the predetermined peak level of the bottom select gate transistor is equal to the predetermined peak level of the first predetermined region; and simultaneously raising the voltage of the top select gate transistor from its initial level to its predetermined peak level, raising the voltage of the second predetermined region from its initial level to the predetermined peak level, and the predetermined peak level of the top select gate transistor is equal to the predetermined peak level of the second predetermined region.

[0023] According to one embodiment of this application, increasing the voltage of the select gate transistor from its starting level to its predetermined peak level and increasing the voltage of the predetermined region from its starting level to its predetermined peak level includes: increasing the voltage of the first predetermined region from its starting level after the voltage of the bottom select gate transistor is increased from its starting level; and increasing the voltage of the second predetermined region from its starting level after the voltage of the top select gate transistor is increased from its starting level.

[0024] Another aspect of this application provides a non-volatile memory, the non-volatile memory comprising: a memory array formed on a well-doped region of a substrate and including a plurality of memory cells, wherein a string of memory cells in each column is connected to the same bit line to form a memory cell string, the plurality of memory cell strings are formed into a memory block, the memory block including a plurality of vertically stacked layers in a direction perpendicular to the substrate, the memory cell string including a plurality of sub-memory cell strings belonging to different layers; and a control circuit coupled to the memory array and configured to control the selection of layers, and to perform a layer erasure operation and a gate-induced drain leakage (GIDL) erasure operation on the selected layer as described in any one of the data erasure methods for non-volatile memory provided in one aspect of this application.

[0025] According to one embodiment of this application, the storage array is a three-dimensional NAND storage array, and the non-volatile memory is a three-dimensional NAND memory.

[0026] Another aspect of the embodiments of this application provides a storage system, including a controller and a non-volatile memory provided in another aspect of the embodiments of this application, wherein the controller is coupled to the memory and is used to control the memory to store data.

[0027] Another aspect of the embodiments of this application provides an electronic device, including a non-volatile memory provided in another aspect of the embodiments of this application.

[0028] According to at least one embodiment of the non-volatile memory and its data erasure method provided in this application, as well as a storage system and electronic device, the data erasure method may include two time periods, wherein during a first time period, the erasure voltage applied to the memory cell string increases from a starting level to an intermediate level, and during a second time period, the erasure voltage increases from the intermediate level to a peak level. By applying an auxiliary voltage (a predetermined peak level) to the select gate transistor of the memory cell string and a predetermined region adjacent to the select gate transistor during the second time period, a gate-induced drain leakage current can be generated, thereby achieving efficient non-volatile memory level erasure operation and gate-induced drain leakage erasure operation.

[0029] Furthermore, according to at least one embodiment of this application, during the application of an auxiliary voltage device to the select gate transistor of the memory cell string, an auxiliary voltage is applied to a predetermined region adjacent to the select gate transistor. Specifically, when auxiliary voltages are applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor respectively (e.g., applying auxiliary voltages to the select gate transistor of the memory cell string first, and then applying auxiliary voltages to the predetermined region adjacent to the select gate transistor), the switching performance of the select gate transistor as a selector switch of the memory cell string can be improved, and crosstalk and leakage between adjacent memory cell strings can be avoided; when auxiliary voltages are applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor simultaneously, the control circuit of the non-volatile memory can be simplified, and the operability of the non-volatile memory data erasure method can be improved.

[0030] Furthermore, according to at least one embodiment of this application, moving a predetermined region adjacent to the bottom-level select gate transistor closer to the layer to be erased can improve the gate-induced drain leakage current and achieve efficient data erasure of non-volatile memory. Attached Figure Description

[0031] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein: Figure 1 This is a block diagram of a non-volatile memory according to one embodiment of this application; Figure 2 This is a partial structural cross-sectional view of a non-volatile memory according to one embodiment of this application; Figure 3 This is a partial equivalent circuit diagram of a storage array according to one embodiment of this application; Figure 4 This is a flowchart of a data erasure method for a non-volatile memory according to one embodiment of this application; Figure 5 This is a partial circuit diagram of a non-volatile memory according to one embodiment of this application; Figure 6 This is a partial circuit diagram of a non-volatile memory according to another embodiment of this application; Figure 7 This is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of this application; Figure 8 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application; Figure 9 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application; Figure 10 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application; Figure 11 This is a schematic diagram of a storage system structure according to one embodiment of this application; and Figure 12 This is a schematic diagram of an electronic device structure according to one embodiment of this application. Detailed Implementation

[0032] Exemplary embodiments of the invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are illustrated. However, the invention may be embodied in various forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0033] It should also be understood that when a component or layer is referred to as being "on" another component or layer, "connected to," or "attached to" another component or layer, it may be directly on or directly connected to the other component or layer, or there may be a component or layer between them. However, when a component or layer is referred to as being "directly on" another component or layer, "directly connected to," or "directly attached to" another component or layer, there is no intermediate component or layer. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without an intermediary element.

[0034] Throughout the specification, the same reference numerals denote the same components. In the accompanying drawings, the thickness of layers and regions is exaggerated for clarity.

[0035] While the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of one or more embodiments, the first level discussed below may be referred to as the second level. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," etc., may also be used herein to distinguish elements of different classes or groups. For the sake of brevity, the terms "first," "second," etc., may respectively represent "first class (or first group)," "second class (or second group)," etc.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the term "comprising" specifies the presence of the described features, areas, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, areas, steps, operations, elements, components, and / or groups thereof.

[0037] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, depending on the specific orientation of the figure, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0038] Figure 1 A block diagram of a non-volatile memory 100 according to one embodiment of this application is shown. Figure 1 As shown, the non-volatile memory 100 includes a memory array 1021 and a control circuitry 1011 coupled together. In some embodiments, the memory array 1021 and the control circuitry 1011 may be arranged on the same chip. In other embodiments, the memory array 1021 may be arranged on an array chip, and the control circuitry 1011 may be arranged on a different chip (e.g., implemented using complementary metal-oxide-semiconductor (CMOS) technology, and referred to as a CMOS chip). The array chip and the CMOS chip may be electrically coupled together via processes such as bonding. In some embodiments, the non-volatile memory 100 is an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0039] The non-volatile memory 100 can be configured to store data in the memory array 1021 and perform operations in response to received commands (CMDs). In some embodiments, the non-volatile memory 100 can receive write commands, read commands, erase commands, etc., and can perform operations accordingly.

[0040] In one implementation, the non-volatile memory 100 receives an erase command with an address, and then the non-volatile memory 100 resets one or more memory cells at that address to an unprogrammed state (or erased state), such as "1" for a NAND memory cell.

[0041] Typically, the storage array 1021 may include one or more storage planes 160, and each storage plane 160 may include multiple storage blocks (e.g., Figure 1 The block shown 1 to block N). Each storage block may also include multiple vertically stacked levels (e.g., Figure 1 The block shown 1 includes levels 1 to M. In some examples, concurrent operations may occur at different storage planes 160. In some implementations, each of levels 1 to M is the smallest unit for performing an erase operation.

[0042] In some implementations, the storage array 1021 is a flash memory array and is implemented using 3D NAND flash memory technology. In some implementations, the control circuitry 1011 includes a row decoder 110, a page buffer circuitry 120, a data input / output (I / O) circuitry 130, a voltage generator 140, and control circuitry 150 coupled together. The row decoder 110 can receive what is referred to as a row address (R). The address of the ADDR is used to generate word line (WL) signals and selection signals (such as top select gate (TSG) signals, bottom select gate (BSG) signals, etc.) based on the row address, and the WL signals and selection signals are provided to the memory array 1021. Furthermore, during the erase operation, the row decoder 110 provided in this application can provide appropriate WL signals and selection signals.

[0043] Page buffer circuitry 120 is coupled to the bit line (BL) of memory array 1021 and is configured to buffer data during read and write operations. Data I / O circuitry 130 is coupled to page buffer circuitry 120 via data line DL. In one example (e.g., during a write operation), data I / O circuitry 130 is configured to receive data from external circuitry of non-volatile memory 100 and provide the received data to memory array 1021 via page buffer circuitry 120.

[0044] Voltage generator 140 is configured to generate voltages of appropriate levels for appropriate operation of the non-volatile memory 100. For example, during a data erase operation, voltage generator 140 can generate voltages of appropriate levels for bit line voltages, well-doped region voltages, various word line voltages, select voltages, predetermined region voltages, etc., suitable for the erase operation. For example, during a data erase operation, a step erase voltage is provided to the well-doped regions of the memory array 1021. A step erase auxiliary voltage is provided to the row decoder 110, so that the row decoder 110 can output a top select gate signal at an appropriate voltage level during the data erase operation. A peak voltage of a predetermined region is provided to the row decoder 110, so that the row decoder 110 can output a predetermined region signal at an appropriate voltage level during the data erase operation. A step erase voltage is provided to the page buffer circuit 120, so that the page buffer circuit 120 can drive the bit lines (BL) at an appropriate voltage level during the erase operation. Alternatively, the step erase voltage can also be applied to the bit lines without passing through the page buffer circuit 120.

[0045] Control circuit 150 is configured to receive commands (CMD) and addresses (ADDR), and based on these commands and addresses, to provide control signals to circuits such as row decoder 110, page buffer circuit 120, data I / O circuit 130, and voltage generator 140. For example, control circuit 150 can generate row address R based on address ADDR. ADDR and column address C ADDR, and set row address R The ADDR is provided to the row decoder 110, and the column address is provided to the data I / O circuitry 130. In another embodiment, the control circuitry 150 can control the voltage generator 140 to generate an appropriate voltage level based on the received CMD. The control circuitry 150 can coordinate other circuits to provide signals to the memory array 1021 at the appropriate time and according to the appropriate voltage level.

[0046] The control circuit 150 may include a first portion of control circuitry 155, configured to generate appropriate control signals to control other circuitry to provide appropriate signals to the memory array 1021 for an erase operation. This erase operation uses a hierarchical erase mechanism and a GIDL erase mechanism; in other words, the first portion of control circuitry 155 is a control circuitry for hybrid erase. Signals with appropriate timing and voltage levels for the memory array 1021 can utilize the hierarchical erase mechanism and the GIDL erase mechanism for data erase operations on non-volatile memory. This application will refer to... Figures 4 to 12 The waveform of the signal will be described in detail below.

[0047] Figure 2A partial structural cross-sectional view of a non-volatile memory 200 according to one embodiment of this application is shown. Figure 2 As shown, in one embodiment of this application, the non-volatile memory 200 may include a three-dimensional memory array chip 202 and a peripheral circuit chip 201 electrically coupled together by processes such as bonding.

[0048] In some embodiments, the non-volatile memory 200 may include a plurality of array chips 202 and peripheral circuit chips 201. The array chips 202 include a substrate 203 and a stacked structure 290 formed on the substrate 203. The peripheral circuit chips 201 include a substrate and peripheral circuitry formed on the substrate. For simplicity, the main surface of the substrate 203 is referred to as X. The Y-plane, and the direction perpendicular to the main surface, is called the Z-direction.

[0049] The substrates of substrate 203 and peripheral circuit chip 201 can be any suitable substrate, such as silicon (Si) substrates, germanium (Ge) substrates, silicon-germanium (SiGe) substrates, and / or silicon-on-insulator (SOI) substrates. In other words, the substrates of substrate 203 and peripheral circuit chip 201 can each comprise semiconductor materials, such as group IV semiconductors, group III semiconductors, etc. Group V compound semiconductors or II Group VI oxide semiconductors. Group IV semiconductors may include Si, Ge, or SiGe. Alternatively, the substrates of substrate 203 and peripheral circuit chip 201 may also be bulk wafers or epitaxial layers, respectively.

[0050] The stacked structure 290 includes alternately stacked gate layers 295 and insulating layers 294. Gate layers 295 are made of gate stacking materials such as a high-k gate insulator layer and a metal gate (MG) electrode. Insulating layers 294 are made of insulating materials such as silicon nitride or silicon dioxide. Gate layers 295 and insulating layers 294 are configured to form vertically stacked transistors in the Z direction, with gate layer 295 corresponding to the gate of the transistor.

[0051] The non-volatile memory 200 may include a cell array and peripheral circuitry (e.g., a line decoder 110, a page buffer circuitry 120, a data I / O circuitry 130, a voltage generator 140, control circuitry 150, etc.). The peripheral circuitry is formed in a peripheral circuitry chip 201, and the cell array is formed in an array chip 202. The array chip 202 may include a core region 01 and a stepped region 02. The cell array is formed in the portion of the stacked structure 290 located in the core region 01 and includes a plurality of vertical cell strings 280. The stepped region 02 facilitates connections, for example, to the gates of the cell arrays in the cell strings 280, the gates of select gate transistors, etc. The gates of the cell arrays in the cell strings 280 correspond to word lines in the memory architecture.

[0052] The memory cell string 280 is formed by a channel structure 281 that extends through the stacked structure 290 and vertically (along the Z direction) into the substrate 203. In other words, the channel structure 281 and the stacked structure 290 together form the memory cell string 280.

[0053] Channel structure 281 may be included in X A functional layer and a semiconductor layer, circular in shape in the Y-plane and extending in the Z-direction to the substrate 203, are present. The functional layer may include a barrier insulating layer (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride), and a tunneling insulating layer (e.g., silicon oxide). The semiconductor layer may be fabricated from any suitable semiconductor material (such as polycrystalline silicon or monocrystalline silicon), and the semiconductor material may be undoped or may include P-type or N-type doped impurities. In one embodiment, a barrier insulating layer may be formed on the sidewalls of a hole for the channel structure 281 (which may penetrate the stacked structure 290 and extend into the substrate 203), and then the charge storage layer, tunneling insulating layer, semiconductor layer, and insulating fill layer are sequentially stacked from the sidewalls. The insulating fill layer may be formed from an insulating material such as silicon oxide and / or silicon nitride, and / or may be formed as an air gap.

[0054] The substrate 203 may include a well-doped region, such as a highly doped semiconductor layer 205 (or well-doped region 205), for forming an electrical connection with the semiconductor layer in the channel structure 281. Alternatively, the semiconductor layer 205 may be electrically connected to the bottom of the semiconductor layer in the channel structure 281; alternatively, the semiconductor layer 205 may be electrically connected to the sidewalls of the semiconductor layer in the channel structure 281, or form an electrical connection with both the bottom and sidewalls of the semiconductor layer in the channel structure 281.

[0055] Semiconductor layer 205 may be formed as a source conductive connection for memory cell string 280. Semiconductor layer 205 may include one or more layers. Semiconductor layer 205 may be fabricated using, for example, silicon materials, such as intrinsic polysilicon, doped polysilicon (such as N-type doped silicon or P-type doped silicon, etc.). Alternatively, semiconductor layer 205 may also include metal silicides to improve conductivity. Semiconductor layer 205 is similarly conductively connected to the sources of other memory cell strings 280, and thus forms an array common source (ACS). In some embodiments, when memory cell string 280 is configured for layer-by-layer erasure, semiconductor layer 205 may extend and cover the core region and step region of the memory block to which the layer belongs.

[0056] In some embodiments, the vertically stacked transistors formed by the gate layer 295 and the insulating layer 294 may include memory cells (or memory cell transistors) and select gate transistors (e.g., one or more bottom-level select gate transistors, or one or more top-level select gate transistors, etc.). The semiconductor layer of the channel structure 281 described above corresponds to the channel portion of the transistors in the memory cell string 280, while the gate layer 295 corresponds to the gate of the transistors in the memory cell string 280.

[0057] The memory cells can have different threshold voltages based on carrier capture in a portion of the charge storage layer of the channel structure 281 described above, which corresponds to the floating gate of the memory cell. For example, when a large number of holes are captured (stored) in the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor is lower than a predefined value, and the memory cell transistor is in an unprogrammed state corresponding to logic "1" (also known as an erased state). When holes are expelled from the floating gate, the threshold voltage of the memory cell is higher than the predefined value, and therefore the memory cell transistor is in a programmed state corresponding to logic "0".

[0058] A typical transistor includes a gate for controlling a channel, and a drain and a source on each side of the channel. Alternatively, the upper side of the transistor's channel can be called the drain, and the lower side the channel can be called the source. Alternatively, the drain and source can be interchanged in certain drive configurations. Furthermore, the aforementioned top-level select-gate transistor can be connected to the drain above it, and the bottom-level select-gate transistor can be connected to the source below it.

[0059] One or more top-level select-gate transistors are configured to couple / decouple memory cells in memory cell string 280 to bit lines. One or more bottom-level select-gate transistors are configured to couple / decouple memory cells in memory cell string 280 to ACS (common source line).

[0060] The bottom-level select-gate transistor is controlled by the bottom-level select-gate. For example, when the bottom-level select-gate voltage (the voltage applied to the bottom-level select-gate) is greater than the threshold voltage of the bottom-level select-gate transistor, the bottom-level select-gate transistor is turned on, and the memory cell is coupled to the ACS. When the bottom-level select-gate voltage is less than the threshold voltage of the bottom-level select-gate transistor, the bottom-level select-gate transistor is turned off, and the memory cell is decoupled from the ACS. Similarly, the top-level select-gate transistor is controlled by the top-level select-gate.

[0061] In some embodiments, the channel structure 281 in X It has a circular shape in the Y-plane and in the X-plane... Z-plane and Y-plane It has a cylindrical shape in the Z-plane. In the X... In the Y-plane, multiple channel structures 281 can be arranged separately from each other to form a memory cell array. The array of channel structures 281 can have any suitable array shape, such as a matrix array shape along the X and Y directions, a sawtooth array shape along the X or Y directions, a honeycomb (e.g., hexagonal) array shape, etc. The memory cell array can be divided into multiple memory blocks by gate line gap structures 270 having a spacing with respect to the channel structures 281 in the X direction. Each memory block includes multiple layers stacked from bottom to top (Z direction). In other words, multiple memory cell strings 280 are formed as memory blocks, and the memory blocks include multiple vertically stacked layers in the direction perpendicular to the substrate 203 (Z direction), so the memory cell strings 280 can include multiple sub-memory cell strings belonging to different layers.

[0062] In some implementations, redundant layers are further provided between the multiple layers, and the redundant layers include at least one pseudo-memory cell. The pseudo-memory cell and the memory cell are fabricated simultaneously and can be used for process and electrical buffering.

[0063] Figure 3 A partial equivalent circuit diagram of a memory array 300 according to one embodiment of this application is shown. Figure 3As shown, as an example, the three-dimensional storage device 300 can be divided into multiple storage blocks, each storage block including two levels, such as a top level 452 and a bottom level 450. The three-dimensional storage device 300 may also include a memory string 212 having multiple stacked memory cells 340. The memory string 212 may include multiple sub-memory stringes belonging to different levels, wherein a sub-memory string formed by multiple memory cells 340-1 is in the bottom level 450, and a sub-memory string formed by multiple memory cells 340-2 is in the top level 452. The three-dimensional storage device 300 also includes a conductive plug 460 between the top level 452 and the bottom level 450. Therefore, in the three-dimensional storage device 300 with multiple levels, memory cells 340-2 in the top level 452 can be electrically connected to memory cells 340-1 in the bottom level 450 to form the memory string 212. The memory string 212 may also include at least one field-effect transistor (e.g., MOSFET) at each end, controlled by a bottom-select gate 332 and a top-select gate 334, respectively. The two corresponding transistors are referred to as bottom-select gate transistor 332-T and top-select gate transistor 334-T. The stacked memory cell 340 may be controlled by a control gate 333, which includes a control gate 333-1 corresponding to memory cell 340-1 and a 333-2 corresponding to memory cell 340-2, wherein the control gate 333 is connected to a word line (not shown) of the three-dimensional memory device 300. The drain terminal of the top-select gate transistor 334-T may be connected to a bit line 341, and the source terminal of the bottom-select gate transistor 332-T may be connected to a well-doped region from which the ACS464 may be formed and may be shared by the memory string 212 throughout the memory block.

[0064] In non-volatile memory, the memory cells in each row of each level are connected to the same word line (WL), and the memory cells in each column are connected to the same bit line (BL). Each word line corresponds to a page, multiple pages form a block, and multiple blocks can form a plane. Furthermore, in non-volatile memory with multiple levels, each level can be processed independently for efficient reading, writing, and erasing. For example, in a three-dimensional non-volatile memory, each level can perform erasing operations independently of other levels. Additionally, read and write operations can be performed within memory pages that include memory cells sharing the same word line.

[0065] The three-dimensional non-volatile memory structure comprising two levels has been described above. The following will, in conjunction with the accompanying drawings, detail the data erasure method for the aforementioned three-dimensional non-volatile memory provided by embodiments of this application.

[0066] Figure 4This is a flowchart of a data erasure method 1000 for a non-volatile memory according to one embodiment of this application. Figure 4 As shown, the data erasure verification method 1000 for non-volatile memory includes: Step S1: Apply a stepped erase voltage to the string of memory cells to be erased. The stepped erase voltage has a voltage waveform that rises in a stepped manner.

[0067] Step S2, during the rise of the step erase voltage from its intermediate level to its peak level, the voltage of the select gate transistor is raised from its initial level to its predetermined peak level, and the voltage of the predetermined region is raised from its initial level to its predetermined peak level, thereby generating a gate-induced drain leakage current in the memory cell string, wherein the predetermined region is adjacent to the select transistor and includes at least one memory cell.

[0068] The steps described above will be described in detail below so that those skilled in the art can more readily understand the specific implementation of the above method 1000.

[0069] Step S1

[0070] Figure 5 This is a partial circuit diagram of a non-volatile memory according to one embodiment of this application. Figure 6 This is a partial circuit diagram of a non-volatile memory according to another embodiment of this application.

[0071] In step S1, the non-volatile memory may include multiple memory blocks, such as Figure 5 As shown, a storage block may include a string of storage cells 212 consisting of a top level 452 and a bottom level 450. Any level within the string of storage cells 212 to be erased can be selected as the first level for a hierarchical erasure operation, or the entire storage block containing the string of storage cells 212 can be erased. A hierarchical erasure operation means that only at least one level of the storage block is erased, rather than the entire storage block.

[0072] In one embodiment of this application, the memory cell string 212 may include serially connected memory cells, a top-level select gate transistor 334-T, and a bottom-level select gate transistor 332-T, wherein TSG represents an electrical signal applied to the top-level select gate of the top-level select gate transistor 334-T, and BSG represents an electrical signal applied to the bottom-level select gate of the bottom-level select gate transistor 332-T.

[0073] Furthermore, redundant layers are provided between the multiple layers, each including at least one pseudo memory cell (e.g., IDPDMY located between the top layer 452 and the bottom layer 450). The pseudo memory cell and the memory cell are fabricated simultaneously and can be used for process and electrical buffering.

[0074] For example, in one embodiment of this application, the memory cell string 212 may include at least one top-level select gate transistor 334-T, which may form a top-level select layer. Alternatively, the top-level select layer may include at least one top-level select gate transistor 334-T and at least one top-level pseudo-memory cell 334'. The top-level pseudo-memory cell 334' and the top-level select gate transistor 334-T may be fabricated simultaneously and used for process and electrical buffering, wherein TSG_DMY represents an electrical signal applied to the gate of the top-level pseudo-memory cell 334'.

[0075] Similarly, the memory cell string 212 may also include a bottom pseudo memory cell 332' adjacent to the bottom select gate transistor 332-T. The bottom pseudo memory cell 332' and the bottom select gate transistor 332-T may be fabricated simultaneously and used for process and electrical buffering, where BSG_DMY represents the electrical signal applied to the gate of the bottom pseudo memory cell 332'.

[0076] The top-level pseudo-memory unit 334' and the bottom-level pseudo-memory unit 332' can be referred to as the selection-level pseudo-memory unit.

[0077] In addition, such as Figure 6 As shown, a redundant layer comprising at least one first dummy memory cell 205' is further disposed between the bottom selected gate transistor 332-T and the well doped region 205 of the substrate. The dummy memory cell and the memory cell in this redundant layer are fabricated simultaneously and can be used for process and electrical buffering. DMY represents an electrical signal applied to a predetermined region of the redundant layer to which the dummy memory cell 205' belongs.

[0078] Figure 7 This is a voltage waveform timing diagram for a non-volatile memory according to one embodiment of this application. Figure 8 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application. Figure 9 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application. Figure 10 This is a voltage waveform timing diagram for a non-volatile memory according to another embodiment of this application.

[0079] Currently, the connection methods at the bottom of the channel layer in non-volatile memory have evolved from traditional selective epitaxial structures to lateral interconnection and the latest bottom interconnection methods. Connecting the channel layer by forming a highly doped semiconductor layer at the bottom (typically with the same type of doping as the channel layer) has become the mainstream method for fabricating non-volatile memory. However, non-volatile memory obtained using this method is not suitable for body erasure. Therefore, gate-induced drain leakage (GIDL) is required to generate an auxiliary body bias voltage to assist the erasure operation and achieve data erasure in non-volatile memory.

[0080] However, as the number of stacked layers of non-volatile memory continues to increase, erase carriers often struggle to reach the memory cell where the operation is to be performed, thus hindering effective GIDL erasure.

[0081] The non-volatile memory erasure method provided in this application generates gate-induced drain leakage current in the memory cell string to be erased by applying an auxiliary voltage (predetermined peak level) to a predetermined region of the select transistor and adjacent select transistor during the second time period of the data erasure operation, thereby achieving efficient hierarchical erasure operation and gate-induced drain leakage erasure operation.

[0082] Specifically, such as Figures 5 to 10 As shown, a stepped erase voltage with a stepped rising voltage waveform can be applied to multiple memory cell strings to be erased. For example, the stepped erase voltage signal can be applied to the bit line 341 and the well doped region 205 corresponding to the memory cell string 212, respectively.

[0083] by Figure 7 For example, BL represents the electrical signal applied to bit line 341. HVNW represents the electrical signal applied to the well doped region 205. The step erase voltage has a step-shaped voltage waveform, with the first step spanning the time period from T0 to T2, and the voltage rising from the initial level to the intermediate level Vepre.

[0084] The second stage spans the time period from T2 to T3, during which the voltage rises from the intermediate level Vepre to the peak level Vers. The intermediate level Vepre can be, for example, chosen between 1 volt and 4 volts. The peak level Vers can be, for example, chosen between 16 volts and 22 volts. The time period from T2 to T3 is approximately between 0.4 milliseconds and 0.9 milliseconds.

[0085] In addition, WLs represents the electrical signal applied to the gate of each memory cell in the memory cell string 212. Figures 7 to 10The voltage waveform timing diagram is shown when performing a data erase operation on the entire memory block to which memory cell string 212 belongs. When performing a data erase operation on the entire memory block, the gates of all memory cells in the memory block to be erased should be grounded or connected to a low level.

[0086] Alternatively, the data erasure method provided in this application is also applicable to hierarchical data erasure operations. When performing a hierarchical data erasure operation, the gate of the memory cell to be erased can be grounded or connected to a low level. Simultaneously, the gates of memory cells in other levels that are not being erased are set to a floating state. When other levels that are not being erased are in a floating state, the circuit structure does not perform circuit interconnection functions. Those skilled in the art will understand that, in this specification, when a component (or part, assembly, member, etc.) is referred to as being in a floating state, it is intended to indicate that the component (or part, assembly, member, etc.) does not form an electrical path with other components (or parts, assemblies, members, etc.).

[0087] Step S2

[0088] Combination Figure 5 , Figures 7 to 10 When the memory block formed by multiple memory cell strings 212 includes only a bottom level 450 and a top level 452, in step S2, during the rise of the step erase voltage from its intermediate level to its peak level, the voltage of the select gate transistor can be raised from its starting level to its predetermined peak level, and the voltage of a predetermined region can be raised from its starting level to its predetermined peak level, thereby generating a gate-induced drain leakage current in the memory cell string, wherein the predetermined region is adjacent to the select gate transistor and includes at least one memory cell, which may include, for example, the following: During the process of raising the voltage of the select gate transistors (e.g., top select gate transistor 334-T and bottom select gate transistor 332-T) from their initial level to their peak level (e.g., Vtsg and Vbsg), the voltage of a predetermined region of the memory cell string (e.g., the second predetermined region 102 and the first predetermined region 101) is raised from its initial level to its peak level (e.g., Vgidl and Vgidl).

[0089] In other words, during the period when the voltage of the bottom-level select gate transistor 332-T is increased from its initial level to its peak level Vbsg, the voltage of the first predetermined region 101 is increased from its initial level to its peak level Vgidl. Alternatively, during the period when the voltage of the top-level select gate transistor 334-T is increased from its initial level to its peak level Vtsg, the voltage of the second predetermined region 102 is increased from its initial level to its peak level Vgidl.

[0090] Specifically, such as Figure 5As shown, in one embodiment of this application, the select gate transistor includes a top-level select gate transistor 334-T connected to bit line 341 and a bottom-level select gate transistor 332-T connected to the well-doped region 205 in the substrate. Accordingly, the predetermined region may include at least a first predetermined region 101 and a second predetermined region 102, wherein the first predetermined region 101 is adjacent to the bottom-level select gate transistor 332-T and includes at least one memory cell, and the second predetermined region 102 is adjacent to the top-level select gate transistor 334-T and includes at least one memory cell. Further, the memory cells included in each of the predetermined regions (e.g., the first predetermined region 101 and the second predetermined region 102) may be dummy memory cells. GIDL represents an electrical signal applied to the gate of each memory cell in the predetermined region.

[0091] Combination Figure 5 , Figures 7 to 10 During the period from T2 to T3, when the electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, electrical signals TSG and BSG can be applied to the top-layer select-gate transistor 334-T and the bottom-layer select-gate transistor 332-T, respectively, to raise them from their initial levels to their peak levels Vtsg and Vbsg. Alternatively, the initial level of the top-layer select-gate transistor 334-T and the bottom-layer select-gate transistor 332-T can be 0 volts, and the values ​​of the peak levels Vtsg and Vbsg can be selected, for example, between 2 volts and 12 volts. Furthermore, during the period from T2 to T3, electrical signals GIDL can also be applied to the first predetermined region 101 and the second predetermined region 102, respectively, to raise them from their initial levels to their peak levels Vgidl. Alternatively, the initial level of the first predetermined region and the second predetermined region can be 0 volts, and the peak level Vgidl can be selected, for example, between 8 and 15 volts. During the second time period, applying an auxiliary voltage (predetermined peak level) to the select gate transistor of the memory cell string and a predetermined region adjacent to the select gate transistor can generate a gate-induced drain leakage current, thereby enabling efficient non-volatile memory level erase operation and gate-induced drain leakage erase operation.

[0092] Alternatively, while raising the voltage of the select gate transistor (e.g., top select gate transistor 334-T and bottom select gate transistor 332-T) from its initial level to its peak level (e.g., levels Vtsg and Vbsg), the voltage of a predetermined region of the memory cell string 212 (e.g., first predetermined region 101 and second predetermined region 102) can be raised from its initial level to its peak level Vgidl, with the peak level of the select gate transistor equal to the peak level of the predetermined region. Applying auxiliary voltages to both the select gate transistor of the memory cell string and the predetermined regions adjacent to the select gate transistor simplifies the control circuitry of the non-volatile memory and improves the operability of the non-volatile memory data erasure method.

[0093] Alternatively, after the voltage of the select gate transistor (e.g., top select gate transistor 334-T and bottom select gate transistor 332-T) is increased from its initial level to its peak level (e.g., levels Vtsg and Vbsg), the voltage of a predetermined region (e.g., first predetermined region 101 and second predetermined region 102) of the memory cell string 212 can be increased from its initial level to its peak level Vgidl. Applying auxiliary voltages to the select gate transistors of the memory cell string and the predetermined regions adjacent to the select gate transistors can improve the switching performance of the select gate transistors as selectors of the memory cell string and avoid crosstalk and leakage between adjacent memory cell strings.

[0094] Specifically, such as Figure 7 As shown by the dashed circle, in the top layer 452, after the voltage of the top-level select gate transistor 334-T is increased from its initial level, the voltage of the second predetermined region 102 can also be increased from its initial level. The interval between these two operations can be approximately between 0.1 milliseconds and 0.3 milliseconds. Subsequently, the voltage of the top-level select gate transistor 334-T rises to its predetermined peak level Vtsg, and the voltage of the second predetermined region 102 also rises to its predetermined peak level Vgidl. In the bottom layer 450, the voltage of the bottom-level select gate transistor 332-T can be increased from its initial level to its predetermined peak level Vbsg simultaneously with the voltage of the first predetermined region 101 rising from its initial level to its predetermined peak level Vgidl. These two operations are performed simultaneously, and the predetermined peak level Vbsg is equal to the predetermined peak level Vgidl.

[0095] In addition, alternatively, such as Figure 8As shown by the dashed circle, in the top layer 452, simultaneously raising the voltage of the top-level select gate transistor 334-T from its initial level to its predetermined peak level Vtsg, the voltage of the second predetermined region 102 is also raised from its initial level to its predetermined peak level Vgidl. These two operations occur concurrently, and the predetermined peak level Vtsg is equal to the predetermined peak level Vgidl. In the bottom layer 450, after the voltage of the bottom-level select gate transistor 332-T is raised from its initial level, the voltage of the first predetermined region 101 can be raised from its initial level. The interval between these two operations is approximately between 0.1 milliseconds and 0.3 milliseconds. Afterward, the voltage of the bottom-level select gate transistor 332-T rises to its predetermined peak level Vbsg, and the voltage of the first predetermined region 102 also rises to its predetermined peak level Vgidl.

[0096] In addition, alternatively, such as Figure 9 As shown by the dashed circle, in the top layer 452, after the voltage of the top-level select gate transistor 334-T is increased from its initial level, the voltage of the second predetermined region 102 can also be increased from its initial level. The interval between these two operations is approximately between 0.1 ms and 0.3 ms. Then, the voltage of the top-level select gate transistor 334-T rises to its predetermined peak level Vtsg, and the voltage of the second predetermined region 102 also rises to its predetermined peak level Vgidl. In the bottom layer 450, after the voltage of the bottom-level select gate transistor 332-T is increased from its initial level, the voltage of the first predetermined region 101 can also be increased from its initial level. The interval between these two operations is approximately between 0.1 ms and 0.3 ms. Then, the voltage of the bottom-level select gate transistor 332-T rises to its predetermined peak level Vbsg, and the voltage of the first predetermined region 102 also rises to its predetermined peak level Vgidl.

[0097] In addition, alternatively, such as Figure 10 As shown by the dashed circle, in the top layer 452, while simultaneously raising the voltage of the top-level select gate transistor 334-T from its initial level to its predetermined peak level Vtsg, the voltage of the second predetermined region 102 is also raised from its initial level to its predetermined peak level Vgidl. These two operations are performed simultaneously, and the predetermined peak level Vtsg is equal to the predetermined peak level Vgidl. In the bottom layer 450, while simultaneously raising the voltage of the bottom-level select gate transistor 332-T from its initial level to its predetermined peak level Vbsg, the voltage of the first predetermined region 101 is also raised from its initial level to its predetermined peak level Vgidl. These two operations are performed simultaneously, and the predetermined peak level Vbsg is equal to the predetermined peak level Vgidl.

[0098] Furthermore, refer again Figure 5 , Figures 7 to 10 In one embodiment of this application, the memory cell string 212 may further include selection-level pseudo-memory cells, wherein the selection-level pseudo-memory cells include bottom pseudo-memory cells 332' adjacent to the bottom selection gate transistor 332-T and top pseudo-memory cells 334' adjacent to the top selection gate transistor 334-T. The selection-level pseudo-memory cells are fabricated simultaneously with the selection gate transistors and are used for process and electrical buffering.

[0099] Alternatively, during the T2-T3 period when electrical signals BL and HVNW rise from their intermediate level Vepre to their peak level Vers, electrical signals TSG_DMY and BSG_DMY can be applied to the top-level pseudo-memory cell 334' and the bottom-level pseudo-memory cell 332', respectively, causing them to rise from their initial levels to their peak levels Vtsg_dmy and Vbsg_dmy. Alternatively, the initial level of the top-level pseudo-memory cell 334' and the bottom-level pseudo-memory cell 332' can be 0 volts, and the values ​​of the peak levels Vtsg_dmy and Vbsg_dmy can be selected, for example, between 2 volts and 12 volts. Applying voltage to the adjacent selected-level pseudo-memory cells can increase the gate-induced drain leakage (GIDL) current caused by inter-band tunneling, achieving effective gate-induced drain leakage (GIDL) erasure, thereby improving the data erasure efficiency of the non-volatile memory.

[0100] In one embodiment of this application, while the voltage of the select gate transistor (e.g., top select gate transistor 334-T and bottom select gate transistor 332-T) is increased from its initial level to its predetermined peak level (e.g., Vtsg and Vbsg), the voltage of the select hierarchy pseudo memory cell (e.g., top pseudo memory cell 334' and bottom pseudo memory cell 332') is increased from its initial level to its peak level (e.g., Vtsg_dmy and Vbsg_dmy).

[0101] For example, as an option, during the period from T2 to T3, such as Figure 7 As shown in the TSG and TSG_DMY curves, the step of applying pressure to the selected level pseudo memory cell can be performed simultaneously with the step of applying pressure to the selected gate transistor. When the two steps are performed simultaneously, the control circuit of the non-volatile memory can be simplified, and the operability of the non-volatile memory data erasure method can be improved.

[0102] As an alternative, during the period from T2 to T3, such as Figure 7As shown in the BSG and BSG_DMY curves, the step of applying pressure to the pseudo memory cell of the selection level can be performed after the step of applying pressure to the selection gate transistor. When the above two steps are performed separately, the switching performance of the selection gate transistor as the selection switch of the memory cell string can be improved while improving the gate-induced drain leakage current.

[0103] Furthermore, combined Figure 6 , Figure 9 and Figure 10 In one embodiment of this application, a redundant layer comprising at least one first dummy memory cell 205' is further disposed between the bottom selected gate transistor 332-T and the well doped region 205 of the substrate. The dummy memory cell and the memory cell in this redundant layer are fabricated simultaneously and can be used for process and electrical buffering. DMY represents an electrical signal applied to a predetermined region of the redundant layer to which the dummy memory cell 205' belongs.

[0104] Alternatively, at least one first pseudo memory cell 205' may be spaced between the first predetermined region 101 and the well doped region 205 of the substrate. This arrangement avoids the adverse effects of process defects in the substrate on the potential of the first predetermined region, thereby reducing the adverse effects of substrate process defects on the gate-induced drain leakage (GIDL) current.

[0105] Furthermore, during the data erasure operation, the potential of the well-doped region 205 of the substrate can be conducted out by setting the first pseudo-memory cell 205' to a floating state. This simplifies the control circuit of the non-volatile memory and improves the operability of the non-volatile memory data erasure method while improving the gate-induced drain leakage current. In other words, during the data erasure operation, the floating first pseudo-memory cell 205' can obtain a predetermined peak level of the well-doped region 205 of the substrate through voltage coupling, thereby achieving better data erasure performance while avoiding the adverse effects of substrate process defects.

[0106] Alternatively, an electrical signal DMY can be directly applied to the first pseudo memory cell 205' that serves as a spacer. This electrical signal DMY can have the same step-shaped voltage waveform as the step erase voltage applied to the bit line 341 and the well doped region 205 of the substrate.

[0107] According to at least one embodiment of this application, an auxiliary voltage device is applied to the select gate transistor of the memory cell string, and an auxiliary voltage is applied to a predetermined region adjacent to the select gate transistor. Specifically, when the auxiliary voltage is applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor respectively (for example, the auxiliary voltage is applied to the select gate transistor of the memory cell string first, and then the auxiliary voltage is applied to the predetermined region adjacent to the select gate transistor), the switching performance of the select gate transistor as a selector switch of the memory cell string can be improved, and crosstalk and leakage between adjacent memory cell strings can be avoided; when the auxiliary voltage is applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor simultaneously, the control circuit of the non-volatile memory can be simplified, and the operability of the non-volatile memory data erasure method can be improved.

[0108] Furthermore, according to at least one embodiment of this application, moving a predetermined region adjacent to the bottom-level select gate transistor closer to the layer to be erased can improve the gate-induced drain leakage current and achieve efficient data erasure of non-volatile memory.

[0109] Figure 11 This is a schematic diagram of the structure of a storage system 10000 according to one embodiment of this application.

[0110] like Figure 11 As shown, at least one embodiment of this application also provides a memory system 10000. The memory system 10000 may include a memory 4000 and a controller 6000. The memory 4000 may be the same as the memory described in any of the embodiments above, and will not be described again in this application. The memory system 10000 may be a two-dimensional memory system or a three-dimensional memory system; the following description uses a three-dimensional memory system as an example.

[0111] The three-dimensional memory system 10000 may include a three-dimensional memory 4000, a host 5000, and a controller 6000. The three-dimensional memory 4000 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be repeated here. The controller 6000 controls the three-dimensional memory 4000 via channel CH, and the three-dimensional memory 4000 can perform operations based on the control of the controller 6000 in response to requests from the host 5000. The three-dimensional memory 4000 receives commands CMD and addresses ADDR from the controller 5000 via channel CH and accesses a region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 4000 can perform internal operations corresponding to commands on the region selected by the address.

[0112] In some implementations, the three-dimensional memory system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC and Micro MMC, a Secure Digital Card in the form of SD, Mini SD and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0113] Figure 12 This is a schematic diagram of the structure of the electronic device 20000 provided in the embodiments of this application.

[0114] like Figure 12 As shown, at least one embodiment of this application also provides an electronic device 20000. The electronic device 20000 includes a memory 4000. The memory 4000 may be the same as the memory described in any of the embodiments above, and will not be repeated here. The electronic device 20000 may be a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, power bank, or other device with storage function. Therefore, the control module 8000 of the electronic device 20000 can be determined according to the specific device type of the electronic device 20000. The control module 8000 can control the three-dimensional memory 4000 through a channel, and the three-dimensional memory 4000 can receive commands CMD and addresses ADDR from the control module 8000 through a channel, and access the region selected from the memory cell array in response to the address. This application does not limit this.

[0115] This application provides a memory, a storage system, and an electronic device. Since it employs the data erasure method for non-volatile memory provided in any of the above embodiments of this application, it has the same beneficial effects as the data erasure method for non-volatile memory described above, and will not be elaborated here.

[0116] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for erasing data from a non-volatile memory, characterized in that, The memory includes a string of memory cells, the string of memory cells including a first select gate transistor, a second select gate transistor, and a plurality of memory cells located between the first select gate transistor and the second select gate transistor, the method including: An erase voltage is applied to the source line or bit line coupled to the memory cell string to perform an erase operation; wherein the first select gate transistor and the second select gate transistor are located between the source line and the bit line; and During the period when the erase voltage increases from its initial level to its peak level, the voltage of the first select gate transistor or the voltage of the second select gate transistor is increased from its initial level, and then the voltage of the predetermined region is increased from the initial level of the predetermined region to the predetermined peak level of the predetermined region. Wherein, the predetermined peak level of the predetermined region is less than the peak level of the erase voltage, and the predetermined region is located between the first select gate transistor and the source line; or, the predetermined region is located between the second select gate transistor and the bit line.

2. The method according to claim 1, characterized in that, The predetermined region includes at least a first predetermined region and a second predetermined region, wherein the first predetermined region is located between the first selected gate transistor and the well doped region coupled to the source line, and the second predetermined region is located between the second selected gate transistor and one end of the memory cell string coupled to the bit line.

3. The method according to claim 2, characterized in that, Increasing the voltage of the selected gate transistor from its initial level and then increasing the voltage of the predetermined region from the initial level of the predetermined region to the predetermined peak level of the predetermined region includes: After increasing the voltage of the first selected gate transistor from its initial level, the voltage of the first predetermined region is increased from its initial level to the peak level of the first predetermined region; and During the erase operation, the second select gate transistor is floated.

4. The method according to claim 3, characterized in that, The process of increasing the voltage of the selected gate transistor from its initial level and then increasing the voltage of the predetermined region from the initial level of the predetermined region to the predetermined peak level of the predetermined region further includes: During the erase operation, the bit line is floated.

5. The method according to claim 1, characterized in that, in, The erase voltage has a stepped-up voltage waveform, and applying the erase voltage to the source line or the bit line includes: In the first period, the erase voltage is raised from the initial level to the intermediate level; In the second period, the erase voltage is maintained at the intermediate level; and In the third period, the erase voltage is raised from the intermediate level to the peak level of the erase voltage.

6. The method according to claim 2, characterized in that, The memory cell string includes at least one pseudo memory cell, the pseudo memory cell being located between the first predetermined region and the source-line coupled well-doped region, and the method further includes: During the erase operation, word lines coupled to the pseudo memory cells are floated.

7. The method according to claim 2, characterized in that, The memory includes a first level and a second level stacked together. The memory cell string includes a first sub-memory cell string located in the first level and a second sub-memory cell string located in the second level. The first sub-memory cell string is adjacent to the first select gate transistor, and the second sub-memory cell string is adjacent to the second select gate transistor. The method further includes: Apply the erase voltage to the source line to erase the memory cells in the first sub-memory cell string; and The erase voltage is applied to the bit line to erase the memory cells in the second sub-memory cell string.

8. The method according to claim 2, characterized in that, Increasing the voltage of the selected gate transistor from its initial level and then increasing the voltage of the predetermined region includes: After increasing the voltage of the first selected gate transistor from its initial level, the voltage of the first predetermined region is then increased; and During the voltage rise of the first selected gate transistor, the voltage of the second selected gate transistor is increased from the initial level to the peak level of the second selected gate transistor.

9. The method according to claim 8, characterized in that, Increasing the voltage of the selected gate transistor from its initial level and then increasing the voltage of the predetermined region further includes: During the period when the voltage of the second selected gate transistor is increased from the initial level to the peak level of the second selected gate transistor, the voltage of the second predetermined region is increased from the initial level to the peak level of the second predetermined region.

10. The method according to claim 9, characterized in that, The method further includes: While increasing the voltage of the second selected gate transistor from the initial level to the peak level of the second selected gate transistor, the voltage of the second predetermined region is also increased from the initial level to the peak level of the second predetermined region.

11. A non-volatile memory, characterized in that, The non-volatile memory includes: A memory array includes a string of memory cells, the string of memory cells including a first select-gate transistor, a second select-gate transistor, and a plurality of memory cells located between the first select-gate transistor and the second select-gate transistor; and The control circuitry, coupled to the storage array, is configured as follows: An erase voltage is applied to the source line or bit line coupled to the memory cell string to perform an erase operation; wherein the first select gate transistor and the second select gate transistor are located between the source line and the bit line; and During the period when the erase voltage increases from its initial level to its peak level, the voltage of the first select gate transistor or the voltage of the second select gate transistor is increased from its initial level, and then the voltage of the predetermined region is increased from the initial level of the predetermined region to the predetermined peak level of the predetermined region. Wherein, the predetermined peak level of the predetermined region is less than the peak level of the erase voltage, and the predetermined region is located between the first select gate transistor and the source line; or, the predetermined region is located between the second select gate transistor and the bit line.

12. The non-volatile memory according to claim 11, characterized in that, The predetermined region includes at least a first predetermined region and a second predetermined region, wherein the first predetermined region is located between the first selected gate transistor and the well doped region coupled to the source line, and the second predetermined region is located between the second selected gate transistor and one end of the memory cell string coupled to the bit line.

13. The non-volatile memory according to claim 12, characterized in that, Increasing the voltage of the selected gate transistor from its initial level and then increasing the voltage of the predetermined region from the initial level of the predetermined region to the predetermined peak level of the predetermined region includes: After increasing the voltage of the first selected gate transistor from its initial level, the voltage of the first predetermined region is increased from its initial level to the peak level of the first predetermined region; and During the erase operation, the second select gate transistor is floated.

14. The non-volatile memory according to claim 13, characterized in that, The control circuit is further configured to: After increasing the voltage of the selected gate transistor from its initial level, increase the voltage of the predetermined region from the initial level of the predetermined region to a predetermined peak level of the predetermined region; During the erase operation, the bit line is floated.

15. The non-volatile memory according to claim 11, characterized in that, in, The erase voltage has a stepped-up voltage waveform, and applying the erase voltage to the source line or the bit line includes: In the first period, the erase voltage is raised from the initial level to the intermediate level; In the second period, the erase voltage is maintained at the intermediate level; and In the third period, the erase voltage is raised from the intermediate level to the peak level of the erase voltage.

16. The non-volatile memory according to claim 12, characterized in that, The memory cell string includes at least one pseudo memory cell located between the first predetermined region and the source-line coupled well-doped region, and the control circuit is further configured to: During the erase operation, word lines coupled to the pseudo memory cells are floated.

17. The non-volatile memory according to claim 12, characterized in that, The memory includes a first level and a second level stacked together. The memory cell string includes a first sub-memory cell string located in the first level and a second sub-memory cell string located in the second level. The first sub-memory cell string is adjacent to the first select gate transistor, and the second sub-memory cell string is adjacent to the second select gate transistor. The control circuit is further configured to: Apply the erase voltage to the source line to erase the memory cells in the first sub-memory cell string; and The erase voltage is applied to the bit line to erase the memory cells in the second sub-memory cell string.

18. The non-volatile memory according to claim 12, characterized in that, Increasing the voltage of the selected gate transistor from its initial level and then increasing the voltage of the predetermined region includes: After increasing the voltage of the first selected gate transistor from its initial level, the voltage of the first predetermined region is then increased; and During the voltage rise of the first selected gate transistor, the voltage of the second selected gate transistor is increased from the initial level to the peak level of the second selected gate transistor.

19. The non-volatile memory according to claim 18, characterized in that, Increasing the voltage of the selected gate transistor from its initial level and then increasing the voltage of the predetermined region further includes: During the period when the voltage of the second selected gate transistor is increased from the initial level to the peak level of the second selected gate transistor, the voltage of the second predetermined region is increased from the initial level to the peak level of the second predetermined region.

20. The non-volatile memory according to claim 19, characterized in that, The control circuit is further configured to: While increasing the voltage of the second selected gate transistor from the initial level to the peak level of the second selected gate transistor, the voltage of the second predetermined region is also increased from the initial level to the peak level of the second predetermined region.

21. The non-volatile memory according to claim 11, characterized in that, The storage array is a three-dimensional NAND storage array, and the non-volatile memory is a three-dimensional NAND memory.

22. A storage system, characterized in that, It includes a controller and a memory according to any one of claims 11-21, wherein the controller is coupled to the memory and is used to control the memory.

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