A gallium oxide power device and a method of manufacturing the same

Abstract

The application provides a gallium oxide power device and a manufacturing method thereof, and relates to the technical field of semiconductors, and comprises a drain, an n-doped gallium oxide substrate and an n-type gallium oxide drift region; the drift region comprises a first n-type gallium oxide drift region, a second n-type gallium oxide drift region and a fin-shaped channel; high-k gate dielectric layers, gates, insulating layers and sources are arranged on both sides of the fin-shaped channel in sequence; an n-type heavily doped top contact region is arranged in the middle of the insulating layer; in a first direction, the second n-type gallium oxide drift region, the fin-shaped channel and the n-type heavily doped top contact region are arranged in sequence in a laminated manner; the maximum height of the high-k gate dielectric layer is equal to the maximum height of the fin-shaped channel, the maximum height of the gate is equal to the difference between the maximum height of the fin-shaped channel and the thickness of the high-k gate dielectric layer; the maximum height of the first n-type gallium oxide drift region is equal to the maximum height of the second n-type gallium oxide drift region; and the width of the second n-type gallium oxide drift region in a second direction is greater than the width of the fin-shaped channel.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gallium oxide power device and its manufacturing method. Background Technology

[0002] Gallium oxide (GaO) power devices are metal-oxide-semiconductor field-effect transistors (MOSFETs) made from gallium oxide (Ga2O3) material. Gallium oxide is a wide-bandgap semiconductor with high breakdown voltage and thermal stability, making it suitable for electronic devices operating in extreme environments such as high power, high frequency, and high temperature. GaO power devices have broad application potential in power electronics, radio frequency communications, and automotive electronics.

[0003] Gallium oxide (GaO) power devices can operate stably at extremely high voltages and temperatures, exhibiting stronger tolerance than traditional silicon MOSFETs. With the increasing demand for high-voltage, high-power applications, GaO power devices offer a more ideal solution for high-efficiency power conversion and signal processing. Furthermore, they can improve system energy efficiency and reduce size, contributing to the development of high-tech industries such as new energy vehicles and 5G communications.

[0004] However, most current gallium oxide power devices use top or single-side gates, which are limited by the gate arrangement, resulting in weak electric field control and difficulty in completely depleting the channel. Moreover, at the same time, the low thermal conductivity of gallium oxide at the fin channel leads to significant self-heating, resulting in decreased mobility and high on-resistance. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a gallium oxide power device that can solve the technical problems of existing gallium oxide power devices, which mostly use top or single-side gates, resulting in weak electric field control and difficulty in completely depleting the channel due to the gate arrangement. Moreover, at the same time, due to the low thermal conductivity of gallium oxide, the self-heating of the fin channel is significant, leading to a decrease in mobility and high on-resistance.

[0006] In a first aspect, a gallium oxide power device is provided, comprising: a drain, an n-doped gallium oxide substrate, and an n-type gallium oxide drift region disposed sequentially.

[0007] The n-type gallium oxide drift region includes a first n-type gallium oxide drift region, a second n-type gallium oxide drift region, and a fin channel. The second n-type gallium oxide drift region and the fin channel are disposed on the center line of the gallium oxide power device. The doping concentration of the fin channel is the same as that of the first n-type gallium oxide drift region, and the doping concentration of the first n-type gallium oxide drift region is less than that of the second n-type gallium oxide drift region.

[0008] A high-k gate dielectric layer, a gate, an insulating layer, and a source are arranged sequentially on both sides of the fin channel, wherein the high-k gate dielectric layer, the gate, the insulating layer, and the source are stacked sequentially in the first direction.

[0009] An n-type heavily doped top contact region is provided in the middle of the insulating layer, with the center line of the gallium oxide power device as the central axis;

[0010] In the first direction, the second n-type gallium oxide drift region, the fin channel and the n-type heavily doped top contact region are stacked sequentially;

[0011] In the first direction, the maximum height of the high-k gate dielectric layer is equal to the maximum height of the fin channel, and the maximum gate height is equal to the difference between the maximum height of the fin channel and the thickness of the high-k gate dielectric layer.

[0012] In the first direction, the maximum height of the first n-type gallium oxide drift region is equal to the maximum height of the second n-type gallium oxide drift region;

[0013] The width of the second n-type gallium oxide drift region in the second direction perpendicular to the first direction is greater than the width of the fin channel.

[0014] A second aspect of this invention provides a method for fabricating a gallium oxide power device, comprising:

[0015] S1: Fabrication of an n-doped gallium oxide substrate;

[0016] S2: The drain electrode is fabricated on the first surface of the n-doped gallium oxide substrate;

[0017] S3: A first n-type gallium oxide drift region and a second n-type gallium oxide drift region are prepared on the second surface of an n-doped gallium oxide substrate;

[0018] S4: Using the centerline of the gallium oxide power device as the central axis, and combining the centrally symmetric gradient etching algorithm, fin-shaped channels are prepared above the second n-type gallium oxide drift region to obtain a boss surface;

[0019] S5: A high-k gate dielectric layer, gate, insulating layer and source are sequentially deposited on the boss surface to obtain a gallium oxide power device.

[0020] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0021] In this embodiment of the invention, a "symmetrical dual-side gate + high-k coated fin channel + partitioned doped drift region + top n" is adopted. +The "contact" combination structure features a high-k gate dielectric and gate plated at equal height on both sides of the fin, significantly improving potential control over the fin top / sidewalls, suppressing short-channel effects and corner electric field concentration, thereby achieving deep depletion and higher transconductance with lower gate voltage; the differentiated design of doping and width in the first / second drift regions maintains a lower electric field near the channel and reduces series resistance away from the channel, balancing breakdown and conduction losses; n + The top contact area, the second drift area, and the fin channel are connected in the first direction, which shortens the source access path, reduces the resistance of the contact and access areas, alleviates fin root current congestion and self-heating hot spots, and reduces the overall on-resistance and improves thermal stability margin and switching efficiency. Attached Figure Description

[0022] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a gallium oxide power device provided in an embodiment of the present invention;

[0024] Figure 2 This is a schematic flowchart of a gallium oxide power device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] The gallium oxide power device provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0027] Reference manual attached Figure 1 The diagram shows a schematic representation of a gallium oxide power device according to an embodiment of the present invention.

[0028] This invention provides a gallium oxide power device, comprising: a drain, an n-doped gallium oxide substrate, and an n-type gallium oxide drift region stacked sequentially.

[0029] The n-type gallium oxide drift region includes a first n-type gallium oxide drift region, a second n-type gallium oxide drift region, and a fin channel. The second n-type gallium oxide drift region and the fin channel are located on the center line of the gallium oxide power device. The doping concentration of the fin channel is the same as that of the first n-type gallium oxide drift region, and the doping concentration of the first n-type gallium oxide drift region is less than that of the second n-type gallium oxide drift region.

[0030] A high-k gate dielectric layer, a gate, an insulating layer, and a source are arranged sequentially on both sides of the fin-shaped channel, wherein the high-k gate dielectric layer, the gate, the insulating layer, and the source are stacked sequentially in the first direction.

[0031] An n-type heavily doped top contact region is provided in the middle of the insulating layer, with the center line of the gallium oxide power device as the central axis.

[0032] In the first direction, the second n-type gallium oxide drift region, the fin channel, and the n-type heavily doped top contact region are stacked sequentially.

[0033] In the first direction, the maximum height of the high-k gate dielectric layer is equal to the maximum height of the fin channel, and the maximum gate height is equal to the difference between the maximum height of the fin channel and the thickness of the high-k gate dielectric layer.

[0034] In the first direction, the maximum height of the first n-type gallium oxide drift region is equal to the maximum height of the second n-type gallium oxide drift region.

[0035] The width of the second n-type gallium oxide drift region in the second direction perpendicular to the first direction is greater than the width of the fin channel.

[0036] The drain, located at the bottom, forms the lower electrode of the longitudinal conduction path with the substrate / drift region. It withstands the main reverse voltage when off and collects electron current when on. The n-doped gallium oxide substrate provides mechanical support and a low-resistance longitudinal current channel. Its n-type background doping helps reduce longitudinal resistance and shares voltage with the drift region above. The n-type gallium oxide drift region, located between the channel and drain, is a critical region for withstanding high voltage and unfolding the depletion layer: the first n-type drift region (lower doping) has the same doping concentration as the fin channel, located close to the channel side, which facilitates electric field smoothing, suppresses corner electric field concentration, and increases breakdown voltage. The second n-type drift region (higher doping) is located on the centerline and stacked sequentially with the fin / top contact region along the first direction (thickness / height direction). Higher doping and a larger lateral width (second direction) are used to reduce series resistance and disperse current density. The fin channel, a three-dimensional fin-shaped channel formed along the centerline, has a narrower cross-section to enhance gate control. Its doping is consistent with the first drift region, facilitating continuous depletion and controllable conduction. High-k gate dielectric layers are respectively coated on both sides of the fin, with a maximum height equal to the maximum height of the fin. This results in a small equivalent oxide layer thickness, low leakage current, and stronger gate control, providing high capacitive coupling for the dual-gate. The gate is located outside the high-k dielectric and symmetrically distributed thereto, achieving an approximate dual-gate coating effect and significantly improving the ability to control the fin top / sidewall barrier. An insulating layer is located outside the gate, used to isolate and support the metal wiring / source above. Simultaneously, it provides dielectric support and an alignment window for the top contact opening at its center. The n-type heavily doped top contact region is arranged with the device centerline as the axis and penetrates the fin / second drift region in the first direction, providing a low-resistance ohmic contact and a short access path, reducing source-side series resistance and current congestion. The source is located at the outermost metal electrode, connected to the n-type through a contact opening in the insulating layer. + The top contact area provides a reliable ohmic connection. It forms a symmetrical stack with the dual gates. The height k is the same as the fin height, and the two drift regions are the same height, with the second drift region having a lateral width greater than the fin width. These features are used to ensure symmetrical gate control, consistent process alignment, and to reduce resistance and current congestion while maintaining breakdown capability.

[0037] Through rational partitioning doping and structural optimization, the electric field control capability is improved, the gate voltage requirement is reduced, and the switching performance is enhanced. The finned channel configuration allows the device to operate effectively at lower voltages, reducing short-channel effects. The use of a high-k gate dielectric layer and a symmetrical gate structure helps to enhance gate control capability, thereby improving transconductance and overall performance. + The reduced contact area decreases contact resistance, effectively lowering on-resistance.

[0038] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0039] In this embodiment of the invention, a "symmetrical dual-side gate + high-k coated fin channel + partitioned doped drift region + top n" is adopted. +The "contact" combination structure features a high-k gate dielectric and gate plated at equal height on both sides of the fin, significantly improving potential control over the fin top / sidewalls, suppressing short-channel effects and corner electric field concentration, thereby achieving deep depletion and higher transconductance with lower gate voltage. The differentiated design of doping and width in the first / second drift regions maintains a lower electric field near the channel and reduces series resistance away from the channel, balancing breakdown and conduction losses. + The top contact area, the second drift area, and the fin channel are connected in the first direction, which shortens the source access path, reduces the resistance of the contact and access areas, alleviates fin root current congestion and self-heating hot spots, and reduces the overall on-resistance and improves thermal stability margin and switching efficiency.

[0040] In one possible implementation, the insulating layer is specifically a silicon dioxide insulating layer.

[0041] It is understandable that the insulation layer is a silicon dioxide insulation layer, mainly because silicon dioxide has excellent electrical insulation properties, high withstand voltage and low leakage current.

[0042] In one possible implementation, the high-k gate dielectric layer is specifically an alumina gate dielectric layer.

[0043] It is understandable that the high-k gate dielectric layer is an alumina gate dielectric layer because alumina has a higher dielectric constant, which can provide stronger gate capacitive coupling with a smaller thickness compared to traditional silicon dioxide.

[0044] In one possible implementation, the doping concentration of the n-doped gallium oxide substrate is less than the doping concentration of the first n-type gallium oxide drift region. The doping concentration of the second n-type gallium oxide drift region is less than the doping concentration of the heavily doped n-type top contact region.

[0045] It should be noted that this doping relationship balances breakdown voltage and conduction by establishing a vertically increasing concentration gradient: the low-doped n-Ga2O3 substrate facilitates depletion and reduces leakage current. The first drift region (consistent with the fin channel) is slightly higher than the substrate to reduce resistance and maintain a smooth electric field. The second drift region further increases doping to further reduce series resistance. And n... + The top contact area is the most heavily doped to ensure excellent ohmic contact and extremely low access resistance, while avoiding electric field spikes caused by high doping intrusion into the drift region, thereby significantly reducing on-resistance while maintaining breakdown capability.

[0046] In one possible implementation, the gates on both sides of the centerline of the gallium oxide power device form a first depletion region and a second depletion region on the fin channel, respectively, wherein the sum of the width of the first depletion region and the width of the second depletion region in a first direction is equal to the width of the fin channel.

[0047] It should be noted that this design effectively controls the current flow in the channel by forming first and second depletion regions on both sides of the fin channel. When a voltage is applied to the gate, the first and second depletion regions form depletion regions on both sides of the fin channel, thereby creating a uniform electric field distribution in the channel and avoiding short-channel effects and current congestion caused by excessive current density. The sum of the widths of the first and second depletion regions is equal to the width of the fin channel, ensuring symmetrical electric fields on both sides of the channel, improving the gate control capability and conductivity of the device, and thus optimizing the overall performance of the gallium oxide power device.

[0048] In one possible implementation, the width of the first depletion region is the same as the width of the second depletion region. The width of the first depletion region is equal to the square root of the quotient of the first element and the second element, wherein the first element is twice the dielectric constant and surface potential of gallium oxide, and the second element is the product of the elementary charge and the doping concentration of the fin channel.

[0049] Among them, surface potential refers to the amount of potential that the semiconductor surface (fin channel surface) is bent relative to the fin channel body, which is determined by the work function difference, interface charge, and gate voltage.

[0050] It should be noted that this implementation optimizes the gate control effect by precisely controlling the widths of the first and second depletion regions. The widths of the first and second depletion regions are consistent and are adjusted based on the dielectric constant of gallium oxide and the surface potential (the change in the potential of the semiconductor surface). The surface potential is affected by the work function difference, interface charge, and gate voltage, influencing the electric field distribution within the channel. This design achieves more uniform electric field modulation, improves gate control capability, effectively reduces channel current non-uniformity, and optimizes device performance. Simultaneously, precise control of the depletion region width helps improve the device's conduction characteristics and reduce on-resistance.

[0051] Specifically, from bottom to top, the device consists of a drain, an n-doped gallium oxide substrate, a partitioned doped drift region, and a fin-shaped channel located at the center line. The fins are covered on both sides with a high-k (e.g., Al₂O₃) gate dielectric of equal height and a symmetrical gate, with a silicon dioxide insulating layer covering the outer side and leading out the source. A central window forms the n-doped channel. + The top contact area is connected to the fin / second drift region. In terms of operating principle, the dual-side gates, under high-k strong coupling, form equal-width first / second depletion regions on both sides of the fin. The sum of their widths is exactly equal to the fin width, achieving complete modulation of the fin cross-section and suppressing electric field concentration in short channels and corners. The drift region, characterized by "first low doping + second high doping and laterally widened," widens and depletes near the channel while reducing series resistance further away, balancing breakdown and conduction. +The top contact area shortens the source-side access path, reduces contact and access area resistance, and alleviates self-heating hotspots. This results in deep depletion and high transconductance at a lower gate voltage, significantly reducing on-resistance, improving thermal stability margin and switching efficiency, while the equal-height / symmetrical geometry facilitates process alignment and consistency.

[0052] Reference manual attached Figure 2 The diagram shows a flow chart of a gallium oxide power device fabrication method provided by an embodiment of the present invention.

[0053] This invention provides a method for fabricating a gallium oxide power device, the method comprising:

[0054] S1: Prepare an n-doped gallium oxide substrate.

[0055] Alternatively, gallium oxide can be doped via epitaxial growth to obtain an n-type gallium oxide substrate with appropriate electronic properties. This substrate provides the basic structure for the device, supporting the subsequent construction of drift regions and fin channels. By adjusting the doping concentration, the conductivity of the substrate can be controlled, thereby affecting the overall conductivity and breakdown voltage of the gallium oxide power device.

[0056] S2: The drain electrode is fabricated on the first surface of the n-doped gallium oxide substrate.

[0057] Optionally, the n-Ga2O3 surface is first deoxidized / plasma-cleaned and patterned using photolithography. Then, an ohmic metal stack is deposited by sputtering or evaporation. Finally, rapid annealing in an inert atmosphere activates the contacts, resulting in a drain with low contact resistance. This step ensures efficient longitudinal current collection and stable voltage division under high voltage, while also improving device conduction losses and heat transfer paths, thus enhancing reliability.

[0058] S3: A first n-type gallium oxide drift region and a second n-type gallium oxide drift region are prepared on the second surface of an n-doped gallium oxide substrate.

[0059] In one possible implementation, S3 specifically includes:

[0060] S301: A primary n-type gallium oxide drift region is prepared on the second surface.

[0061] S302: With the width of the second n-type gallium oxide drift region as a constraint, a strip-shaped photolithographic window is made on the primary n-type gallium oxide drift region with the center line of the gallium oxide power device as the axis, and the unwindowed part forms the first n-type gallium oxide drift region.

[0062] In one possible implementation, S302 specifically includes:

[0063] S3021: Establish a one-dimensional coordinate system along the second direction with the center line of the gallium oxide power device as the vertical axis.

[0064] S3022: Determine the window boundaries on both sides of the centerline of the gallium oxide power device in a one-dimensional coordinate system.

[0065]

[0066] in, Indicates the window boundary value. Indicates the width of the second n-type gallium oxide drift region. This represents the inverse function of the error function. and These represent the minimum and maximum development contrast of the photoresist, respectively.

[0067] It should be noted that in a one-dimensional coordinate system, the window boundary position consists of the ideal half-width plus a process correction displacement. The correction displacement compensates for exposure diffusion, defocusing, and process deviations by inversely mapping the development contrast of the photoresist to an equivalent offset on the Gaussian image strength edge through an error function, ensuring that the left and right boundaries are equidistant, the edges are steeper, and the actual linewidth is closer to the target value.

[0068] S3023: Combining Gaussian and rectangular functions, the window boundary values ​​are converted into light intensity values ​​of different photomask transmission areas.

[0069]

[0070] in, Represents position in a one-dimensional coordinate system The light intensity value at that location, This represents the light intensity value at the center line of the gallium oxide power device. This represents the standard deviation of the Gaussian beam. Represents a rectangle function.

[0071] It should be noted that this step transforms the geometric windowing range into a spatial dose distribution. A Gaussian function is used to characterize the beam's characteristics of being strongest at the center and smoothly attenuating towards the edges, and then a rectangular function is used to directly truncate the light intensity outside the boundaries to zero. Multiplying the two results in an exposure intensity map that is effective only within the window and has a smooth edge transition, which is beneficial for controlling the actual linewidth, reducing line edge roughness, and improving alignment consistency.

[0072] S3024: Perform strip-shaped photolithography windowing on the primary n-type gallium oxide drift region according to the light intensity value, and form the first n-type gallium oxide drift region in the unwindowed part.

[0073] S303: Deposit the second n-type gallium oxide drift region at the opening of the window according to the doping concentration of the second n-type gallium oxide drift region.

[0074] Specifically, the process first involves epitaxially forming a primary n-type drift layer on the second surface. Then, using the centerline as the axis of symmetry, strip windows are created on the primary layer according to the width of the target second region. Error function inversion and Gaussian dose distribution are used to compensate for the lithographic boundaries and exposure intensity, ensuring equidistant left and right boundaries with smooth edges. The unwindowed area is naturally retained as the first (low-doped) drift region. Finally, selective epitaxy / deposition and annealing are performed only at the windowed areas to obtain the second (high-doped, widenable) drift region. This process achieves high dimensional and alignment accuracy and low edge roughness, ensuring strict matching with subsequent fin channels. Simultaneously, it achieves independent adjustment of doping and width: maintaining a low field and improving breakdown capability near the channel, while reducing series resistance and on-resistance away from the channel, balancing breakdown voltage and loss.

[0075] S4: Using the centerline of the gallium oxide power device as the central axis, and combining the centrally symmetric gradient etching algorithm, fin-shaped channels are prepared above the second n-type gallium oxide drift region to obtain a boss surface.

[0076] In one possible implementation, S4 specifically includes:

[0077] S401: Obtain the target width of the fin channel.

[0078] S402: A primary fin channel is extended above the second n-type gallium oxide drift region, constrained by the maximum height of the fin channel and the doping concentration of the first n-type gallium oxide drift region.

[0079] S403: Determine the lateral etching rate by combining the doping concentration of the first n-type gallium oxide drift region and the target width.

[0080] The specific formula for calculating the lateral etching rate is as follows:

[0081]

[0082] in, This represents the pre-exponential factor of the etching reaction, which is related to the type of etching gas. This indicates the doping concentration of the first n-type gallium oxide drift region, determined by XPS characterization of the active atomic density of the etched surface. The relevant sensitivity coefficient, This represents the natural exponential function. This represents the etching reaction activation energy related to the dopant ion type in the first n-type gallium oxide drift region. Indicates the temperature of the etching chamber. Represents Boltzmann's constant. Indicates the doping concentration relative to the first n-type gallium oxide drift region. Related lateral etching rates.

[0083] It should be noted that this formula is used to calculate the lateral etching rate, and it considers multiple factors in the etching process. First, the etching rate is related to the doping concentration; the higher the doping concentration, the faster the etching rate generally is. The pre-factor and sensitivity coefficient in the formula characterize the influence of different gas and material surface activities on the etching rate. Furthermore, the activation energy and temperature of the etching reaction also affect the rate; higher temperatures generally accelerate the etching reaction. This calculation allows for precise control of the etching process, ensuring that the fin channel width meets the expected target and optimizing device performance.

[0084] S404: Determine the lateral etching rate correction coefficient based on the primary width of the primary fin channel, constrained by the target width.

[0085] The formula for calculating the correction factor is as follows:

[0086]

[0087] in, This represents the correction factor. and These represent the target width and the primary width, respectively. This indicates the preset etching duration.

[0088] It should be noted that those skilled in the art can set the preset etching duration according to actual needs, and this invention does not limit it.

[0089] Specifically, this correction factor is used to calibrate the theoretical lateral etching rate to meet the target linewidth. It is adjusted proportionally based on the difference between the primary linewidth and the target linewidth, while simultaneously considering the primary linewidth, the preset etching duration, and the intrinsic lateral etching rate of the material under given process conditions, compensating for over-etching or under-etching. This allows the width to converge to the target within a limited time, improving dimensional consistency and alignment accuracy.

[0090] S405: The lateral etching rate is corrected by the lateral etching rate correction factor to obtain the target lateral etching rate.

[0091]

[0092] in, This indicates the target lateral etching rate.

[0093] S406: Etch the primary fin channel at the target transverse etching rate to obtain the fin channel, i.e., obtain the boss surface.

[0094] Specifically, this process fabricates fin channels above the second n-type gallium oxide drift region through precise control of the etching process. First, the target fin channel width is determined, and a primary fin channel is epitaxially formed, constrained by the maximum height and the doping concentration of the first n-type drift region. Then, based on the doping concentration of the first n-type gallium oxide drift region and the target width, the lateral etching rate is calculated to ensure precise control of the etching depth and width. Further, the lateral etching rate is adjusted using a correction factor to match the target width, and etching is ultimately performed at this rate to obtain the fin channel of the desired width. This method ensures precise control of the fin channel dimensions, thereby optimizing the electrical performance of gallium oxide power devices, reducing short-channel effects, and improving the switching efficiency and stability of the devices.

[0095] S5: A high-k gate dielectric layer, gate, insulating layer and source are sequentially deposited on the boss surface to obtain a gallium oxide power device.

[0096] In practical applications, this method completes the epitaxy, patterning, and stacking of devices from the bottom up: First, an n-type gallium oxide substrate with appropriate electronic properties is obtained. The first side undergoes cleaning, photolithography, metal deposition, and annealing to form a drain with low contact resistance. Subsequently, a primary drift layer is epitaxially grown on the second side, and strip windows are created with the centerline as a symmetry reference. The unwindowed area is retained as the first drift region, while the windowed area is selectively epitaxially grown or deposited to form a more heavily doped second drift region, achieving precise partitioning of lateral and vertical doping. Next, a fin-shaped channel is fabricated above the second drift region using a centrosymmetric gradient etching strategy. By model correction of the etching rate, the fin width is made strictly consistent with the target, and smooth sidewalls and stable mesa are obtained. Finally, a high-dielectric-constant gate dielectric, patterned gate metal, a covering insulating layer, and openings are sequentially deposited on the boss surface and fin sidewalls. Then, the source and top heavily doped contact region are interconnected, completing the device. The overall process ensures symmetrical alignment and dimensional control, balancing high breakdown, low on-resistance, strong gate control, and good process consistency.

[0097] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0098] In this embodiment of the invention, a "symmetrical dual-side gate + high-k coated fin channel + partitioned doped drift region + top n" is adopted. + The "contact" combination structure features a high-k gate dielectric and gate plated at equal height on both sides of the fin, significantly improving potential control over the fin top / sidewalls, suppressing short-channel effects and corner electric field concentration, thereby achieving deep depletion and higher transconductance with lower gate voltage; the differentiated design of doping and width in the first / second drift regions maintains a lower electric field near the channel and reduces series resistance away from the channel, balancing breakdown and conduction losses; n +The top contact area, the second drift area, and the fin channel are connected in the first direction, which shortens the source access path, reduces the resistance of the contact and access areas, alleviates fin root current congestion and self-heating hot spots, and reduces the overall on-resistance and improves thermal stability margin and switching efficiency.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A gallium oxide power device, characterized in that, include: A drain, an n-doped gallium oxide substrate, and an n-type gallium oxide drift region are stacked sequentially. The n-type gallium oxide drift region includes a first n-type gallium oxide drift region, a second n-type gallium oxide drift region, and a fin channel. The second n-type gallium oxide drift region and the fin channel are disposed on the center line of the gallium oxide power device. The doping concentration of the fin channel is the same as that of the first n-type gallium oxide drift region, and the doping concentration of the first n-type gallium oxide drift region is less than that of the second n-type gallium oxide drift region. A high-k gate dielectric layer, a gate, an insulating layer, and a source are sequentially arranged on both sides of the fin-shaped channel, wherein the high-k gate dielectric layer, the gate, the insulating layer, and the source are stacked sequentially in a first direction; An n-type heavily doped top contact region is provided in the middle of the insulating layer, with the center line of the gallium oxide power device as the central axis; In the first direction, the second n-type gallium oxide drift region, the fin channel, and the n-type heavily doped top contact region are stacked sequentially. In the first direction, the maximum height of the high-k gate dielectric layer is equal to the maximum height of the fin channel, and the maximum gate height is equal to the difference between the maximum height of the fin channel and the thickness of the high-k gate dielectric layer. In the first direction, the maximum height of the first n-type gallium oxide drift region is equal to the maximum height of the second n-type gallium oxide drift region; The width of the second n-type gallium oxide drift region in the second direction perpendicular to the first direction is greater than the width of the fin channel.

2. The gallium oxide power device according to claim 1, characterized in that, The insulating layer is specifically a silicon dioxide insulating layer.

3. The gallium oxide power device according to claim 1, characterized in that, The high-k gate dielectric layer is specifically an alumina gate dielectric layer.

4. The gallium oxide power device according to claim 1, characterized in that, The doping concentration of the n-doped gallium oxide substrate is less than the doping concentration of the first n-type gallium oxide drift region; the doping concentration of the second n-type gallium oxide drift region is less than the doping concentration of the heavily doped n-type top contact region.

5. The gallium oxide power device according to claim 1, characterized in that, The two gates on either side of the centerline of the gallium oxide power device form a first depletion region and a second depletion region on the fin channel, wherein the sum of the width of the first depletion region and the width of the second depletion region in the first direction is equal to the width of the fin channel.

6. The gallium oxide power device according to claim 5, characterized in that, The width of the first depletion region is the same as the width of the second depletion region. The width of the first depletion region is equal to the square root of the quotient of the first element and the second element, wherein the first element is twice the dielectric constant and surface potential of gallium oxide, and the second element is the product of the elementary charge and the doping concentration of the fin channel.

7. A method for fabricating a gallium oxide power device, characterized in that, The method, applied to the gallium oxide power device according to any one of claims 1 to 6, comprises: S1: Prepare the n-doped gallium oxide substrate; S2: The drain electrode is prepared on the first surface of the n-doped gallium oxide substrate; S3: The first n-type gallium oxide drift region and the second n-type gallium oxide drift region are formed on the second surface of the n-doped gallium oxide substrate; S4: Using the centerline of the gallium oxide power device as the central axis, and combining the centrally symmetric gradient etching algorithm, the fin-shaped channel is prepared above the second n-type gallium oxide drift region to obtain the boss surface; S5: The high-k gate dielectric layer, the gate electrode, the insulating layer, and the source electrode are sequentially deposited on the boss surface to obtain the gallium oxide power device.

8. The method for fabricating a gallium oxide power device according to claim 7, characterized in that, S3 specifically includes: S301: A primary n-type gallium oxide drift region is prepared on the second surface; S302: Using the width of the second n-type gallium oxide drift region as a constraint, and taking the center line of the gallium oxide power device as an axis, a strip-shaped photolithographic window is made on the primary n-type gallium oxide drift region, and the unwindowed portion forms the first n-type gallium oxide drift region; S303: Deposit the second n-type gallium oxide drift region at the opening of the window according to the doping concentration of the second n-type gallium oxide drift region.

9. The method for fabricating a gallium oxide power device according to claim 8, characterized in that, S302 specifically includes: S3021: Establish a one-dimensional coordinate system along the second direction with the centerline of the gallium oxide power device as the vertical axis; S3022: Determine the window boundaries on both sides of the center line of the gallium oxide power device in the one-dimensional coordinate system; S3023: Combining Gaussian and rectangular functions, the window boundary values ​​are converted into light intensity values ​​of different photomask transmission areas; S3024: Perform strip-shaped photolithography windowing on the primary n-type gallium oxide drift region according to the light intensity value, and form the first n-type gallium oxide drift region in the unwindowed portion.

10. The method for fabricating a gallium oxide power device according to claim 7, characterized in that, S4 specifically includes: S401: Obtain the target width of the fin-shaped channel; S402: With the maximum height of the fin channel and the doping concentration of the first n-type gallium oxide drift region as constraints, an initial fin channel is extended above the second n-type gallium oxide drift region; S403: Determine the lateral etching rate by combining the doping concentration of the first n-type gallium oxide drift region and the target width; S404: Using the target width as a constraint, determine the lateral etching rate correction coefficient based on the primary width of the primary fin channel; S405: Correct the lateral etching rate using the lateral etching rate correction coefficient to obtain the target lateral etching rate; S406: Etch the primary fin channel at the target lateral etching rate to obtain the fin channel, i.e., obtain the boss surface.

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