A monolithically integrated GaN Cascode device and its fabrication method

Abstract

This invention discloses a monolithically integrated GaN Cascode device and its fabrication method, relating to the field of semiconductor device technology. It includes integrating an enhancement-mode GaN MOSFET and a depletion-mode GaN HEMT on the same silicon substrate, with electrode connections achieved through a metal interconnect layer. The fabrication method includes epitaxial growth, etching, doped region fabrication, metal electrode deposition, and the fabrication of a dielectric layer and interconnect metal. This application can significantly reduce the Cascode device area, eliminate parasitic parameters, improve switching speed and power density, while achieving normally-off characteristics, balancing reliability and ease of driving, providing a superior solution for high-frequency / high-power applications.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically, it relates to a monolithically integrated GaN Cascode device and its fabrication method. Background Technology

[0002] GaN is a wide-bandgap semiconductor material with advantages such as high critical breakdown electric field, high saturated electron mobility, and high thermal conductivity. It is considered one of the most promising semiconductor materials after Si. The charge carriers of HEMT devices based on GaN are two-dimensional electron gases (2DEG) generated by GaN / AlGaN polarization, which have high mobility and high density characteristics. Under gate voltage control, this can help the device achieve fast switching and ultra-low on-resistance. Compared with Si devices, GaN HEMTs have an order-of-magnitude improvement in device performance limits determined by the Baliga figure of merit ("the square of the breakdown voltage" divided by "specific on-resistance"), making them an ideal choice for high-speed, integrable switching devices.

[0003] Traditional cascode solutions achieve the complementary advantages of GaNHEMT and SiMOSFET through external packaging, but parasitic inductance, thermal coupling, and reliability issues limit their further improvement in high-frequency / high-power scenarios. Recent research on monolithic / heterogeneous integration (including Si-GaN, GaN-on-GaN, and SiC-GaN hybrids) has made significant progress in reducing parasitic parameters, improving thermal management, and achieving higher breakdown voltages, but key technical bottlenecks such as process temperature matching, overvoltage reliability, and threshold matching still need to be addressed. Traditional cascode solutions use a low-voltage SiMOSFET connected in series with a high-voltage GaNHEMT to achieve a combination of low threshold voltage and low on-resistance. However, parasitic inductance from external bonding and package leads limits switching speed and increases switching losses. Replacing SiMOSFETs with low-voltage enhancement-mode GaN MOSFETs and directly connecting them to a high-voltage depletion-mode GaNHEMT (D-mode) via a single-layer metal bridge enables full-width bandgap monolithic integration. Summary of the Invention

[0004] The purpose of this invention is to provide a monolithically integrated GaN Cascode device and its fabrication method, mainly to solve the technical problems of traditional cascaded Cascode devices in high-frequency / high-power applications, such as complex packaging, large parasitic parameters, low mobility, and limitations due to the performance of Si materials.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A monolithic integrated GaN Cascode device, comprising:

[0007] Substrate;

[0008] A GaN MOSFET device integrated on a substrate and a GaN HEMT device located on the GaN MOSFET device; the GaN MOSFET device and the GaN HEMT device are electrically connected through a metal interconnect structure; and

[0009] Dielectric layer covering GaN MOSFET devices and GaN HEMT devices;

[0010] The GaN MOSFET device includes a GaN MOSFET epitaxial structure consisting of a nucleation layer, a MOSFET buffer layer, and a p-GaN layer, from bottom to top, including a substrate, and a source doped region, a MOSFET source metal, a drain doped region, a MOSFET drain metal, a MOSFET gate oxide layer, and a MOSFET gate metal disposed on the p-GaN layer; wherein, the MOSFET gate metal serves as the gate of the GaN Cascode device;

[0011] The GaN HEMT device includes, from bottom to top, a HEMT buffer layer, a channel layer, and a barrier layer disposed on a p-GaN layer; and a HEMT source metal, a HEMT drain metal, a HEMT gate oxide layer, and a HEMT gate metal disposed on the barrier layer; wherein, the HEMT drain metal serves as the drain of the GaN Cascode device structure.

[0012] Furthermore, in this invention, the metal interconnect structure includes a first interconnect metal connecting the drain metal of the MOSFET and the source metal of the HEMT, and a second interconnect metal connecting the source metal of the MOSFET and the gate metal of the HEMT.

[0013] Furthermore, in this invention, the dielectric layer includes a first dielectric layer covering the upper surface of the MOSFET gate oxide layer and a second dielectric layer covering the upper surfaces of the first dielectric layer and the first interconnect metal; the first dielectric layer and the second dielectric layer are made of one or more insulating materials such as AlN, Al2O3, SiO2, Si3N4, AlON, and SiON, and their thickness is 100~300nm.

[0014] Furthermore, in this invention, the nucleation layer is made of either AlN or AlGaN, and its thickness ranges from 30 to 100 nm; the MOSFET buffer layer is made of any one or more combinations of AlN, AlGaN, InGaN, and GaN, and its thickness ranges from 1000 to 4000 nm; the p-GaN layer is a p-GaN layer doped with Mg, Zn, or Ca, and its thickness ranges from 500 to 1000 nm.

[0015] Furthermore, in this invention, the HEMT buffer layer is made of any one or more combinations of AlN, AlGaN, InGaN, and GaN, and its thickness ranges from 1000 to 4000 nm; the channel layer is made of undoped GaN, and its thickness ranges from 100 to 300 nm; the barrier layer is made of AlGaN, and its thickness ranges from 50 to 100 nm.

[0016] Furthermore, in this invention, the MOSFET gate oxide layer is made of one of the high-k dielectric materials Al2O3, SiO2, HfO2, Si3N4, and AlON, and its thickness ranges from 10 to 100 nm.

[0017] Furthermore, in this invention, both the source doped region and the drain doped region are N-type heavily doped, and the doping element is one of Si, O, Ge, and C.

[0018] Furthermore, in this invention, the MOSFET source metal, MOSFET drain metal, HEMT source metal, HEMT drain metal, first interconnect metal, and second interconnect metal are all made of ohmic contact metal.

[0019] Furthermore, in this invention, the MOSFET gate metal and HEMT gate metal are Schottky contact metals, and the material is a Ni / Au multilayer metal, wherein the thickness of Ni is 20~50nm and the thickness of Au is 50~100nm.

[0020] This invention also provides a method for fabricating a monolithically integrated GaN Cascode device, used in the aforementioned GaN Cascode device, comprising the following steps:

[0021] Step 1: Obtain a silicon substrate, and epitaxially grow a nucleation layer, a MOSFET buffer layer, and a p-GaN layer on the substrate in sequence as the epitaxial structure of a GaN MOSFET device. Then, continue to epitaxially grow a HEMT buffer layer, a channel layer, and a barrier layer as the epitaxial structure of a GaN HEMT device.

[0022] Step 2: Etch the epitaxial structure of the GaN MOSFET device: etch away part of the barrier layer, channel layer and HEMT buffer layer to expose the bottom p-GaN layer;

[0023] Step 3: Fabricate source-doped and drain-doped regions on the p-GaN layer;

[0024] Step 4: Fabricate MOSFET source metal and MOSFET drain metal on the source doped region and drain doped region, and fabricate HEMT source metal and HEMT drain metal on the barrier layer;

[0025] Step 5: Fabricate the MOSFET gate oxide layer and the HEMT gate oxide layer on the upper surface obtained in Step 4;

[0026] Step 6: Fabricate HEMT gate metal on the HEMT gate oxide layer, and fabricate MOSFET gate metal on the MOSFET gate oxide layer;

[0027] Step 7: Deposit the first dielectric layer and the second dielectric layer on the upper surface obtained in step 6;

[0028] Step 8: Etch vias and deposit metal interconnect structures above the electrodes of the GaN MOSFET device and the GaN HEMT device to connect the MOSFET drain metal to the HEMT source metal and the MOSFET source metal to the HEMT gate metal; wherein, the MOSFET source metal, after being connected to the HEMT gate metal, serves as the source of the GaN Cascode device.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) This invention directly grows GaN MOSFETs and GaNHEMTs on the same silicon substrate through a monolithic integrated structure and achieves internal electrical connection through a metal interconnect structure, completely eliminating parasitic parameters caused by external bonding wires. Experimental results show that the device switching speed is effectively improved and the switching loss is reduced, making it particularly suitable for high-frequency power conversion scenarios.

[0031] (2) This invention innovatively uses an enhanced GaN MOSFET to replace the Si MOSFET and forms a full GaN integration with the depletion-type GaN HEMT. By taking advantage of the high breakdown electric field and high electron mobility of GaN material, the breakdown voltage of the device is effectively improved, and the Baliga figure of merit is improved by two orders of magnitude compared with the traditional structure.

[0032] (3) In this invention, the GaN MOSFET uses a p-GaN layer to achieve enhancement-mode characteristics. Its gate metal is directly used as the gate of the Cascode device. By controlling the conduction state of the MOSFET, the HEMT is indirectly driven, so that the overall device exhibits normally-off characteristics. At the same time, the MOSFET gate oxide layer uses a high-k dielectric, and the gate leakage current is <10⁻ 9 The gate reliability is effectively improved by A / mm; the driving circuit is compatible with traditional Si MOSFET driving chips, eliminating the need for negative voltage power supply and reducing system cost.

[0033] (4) The present invention reduces the device area to 1 / 3 of the traditional structure by using a vertically stacked epitaxial structure; the dielectric layer has both insulation and heat dissipation functions, reducing thermal resistance and increasing power density, thus meeting the needs of high-density power modules such as new energy vehicles and 5G base stations. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a monolithically integrated GaN Cascode device provided in an embodiment of the present invention;

[0035] Figure 2 A schematic diagram of the process flow after the epitaxial layer growth is completed in the monolithic integrated GaN Cascode device structure provided in the embodiments of the present invention;

[0036] Figure 3 This is a schematic diagram of the etching process in the monolithic integrated GaN Cascode device structure provided in an embodiment of the present invention.

[0037] Figure 4 This is a schematic diagram of the fabrication process after the source and drain doped regions are completed in the monolithic integrated GaN Cascode device structure provided in the embodiments of the present invention;

[0038] Figure 5 This is a schematic diagram of the fabrication process of the source metal and drain metal in the monolithic integrated GaN Cascode device structure provided in the embodiments of the present invention.

[0039] Figure 6 A schematic diagram of the process flow after the gate oxide layer is fabricated in the monolithic integrated GaN Cascode device structure provided in the embodiments of the present invention;

[0040] Figure 7 This is a schematic diagram of the process flow after the gate metal is fabricated in the monolithic integrated GaN Cascode device structure provided in an embodiment of the present invention.

[0041] The names corresponding to the reference numerals in the attached figures are as follows:

[0042] 1-Substrate; 2-Nucleation layer; 3-MOSFET buffer layer; 4-p-GaN layer; 5-HEMT buffer layer; 6-Channel layer; 7-Barrier layer; 8-Source doped region; 9-Drain doped region; 10-MOSFET gate oxide layer; 11-MOSFET source metal; 12-MOSFET drain metal; 13-MOSFET gate metal; 14-HEMT source metal; 15-HEMT drain metal; 16-HEMT gate metal; 17-First dielectric layer; 18-Second dielectric layer; 19-First interconnect metal; 20-Second interconnect metal; 21-HEMT gate oxide layer. Detailed Implementation

[0043] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0044] This invention discloses a monolithic integrated GaN Cascode device and its fabrication method, such as... Figure 1 As shown, the GaNCascode device includes a GaN MOSFET device and a GaN HEMT device integrated on a silicon substrate 1. The GaN MOSFET device and the GaN HEMT device are electrically connected through a metal interconnect structure; the GaN MOSFET device and the GaN HEMT device are covered with a dielectric layer.

[0045] In this embodiment, the epitaxial structure of the GaN MOSFET device, from bottom to top, includes a silicon substrate 1, a nucleation layer 2, a MOSFET buffer layer 3, and a p-GaN layer 4. The p-GaN layer 4 is provided with a source doped region 8, a drain doped region 9, a MOSFET source metal 11, a MOSFET drain metal 12, a MOSFET gate oxide layer 10, and a MOSFET gate metal 13.

[0046] The epitaxial structure of the GaN HEMT device is located above the GaN MOSFET device. From bottom to top, the epitaxial structure includes an HEMT buffer layer 5, a channel layer 6, and a barrier layer 7. The barrier layer 7 contains an HEMT source metal 14, an HEMT drain metal 15, an HEMT gate oxide layer 21, and an HEMT gate metal 16. The MOSFET drain metal 12 is connected to the HEMT source metal 14 via a first interconnect metal 19. The MOSFET gate metal 13 serves as the gate of the entire GaN Cascode device. The MOSFET source metal 11 is connected to the HEMT gate metal 16 via a second interconnect metal 20 and serves as the source of the entire GaN Cascode device. The HEMT drain metal 15 serves as the drain of the entire GaN Cascode device.

[0047] The specific fabrication method of GaN Cascode devices includes the following steps:

[0048] S1, a nucleation layer 2, a MOSFET buffer layer 3, a p-GaN layer 4, a HEMT buffer layer 5, a channel layer 6, and a barrier layer 7 are sequentially grown on a silicon substrate 1. The growth of the above epitaxial layers is completed using metal-organic chemical vapor deposition (MOCVD) technology. Among them, the silicon substrate 1 is a

[111] oriented epitaxial substrate with p-type doped Si. The nucleation layer 2 is made of AlN or AlGaN, with a thickness ranging from 30 to 100 nm; the MOSFET buffer layer 3 is made of one or a combination of AlN, AlGaN, InGaN, or GaN, with a thickness ranging from 1000 to 4000 nm; the p-GaN layer 4 is a Mg, Zn, or Ca-doped p-GaN layer with a thickness ranging from 500 to 1000 nm; the HEMT buffer layer 5 is made of one or a combination of AlN, AlGaN, InGaN, or GaN, with a thickness ranging from 1000 to 4000 nm; the channel layer 6 is made of undoped GaN with a thickness ranging from 100 to 300 nm; and the barrier layer 7 is made of AlGaN with a thickness ranging from 50 to 100 nm. The structure after epitaxial layer growth is as follows: Figure 2 As shown.

[0049] S2, etching is performed on the epitaxial layer, removing part of the barrier layer 7, channel layer 6, and HEMT buffer layer 5 to expose the bottom p-GaN layer 4. Photolithography is used to define the etchable groove areas on the epitaxial layer, and inductively coupled plasma (ICP) etching is used to etch the barrier layer 7, channel layer 6, and HEMT buffer layer 5. After etching, the surface of the p-GaN layer 4 may have damage or oxide layers. It needs to be treated with boiling NaOH solution for 2 minutes to remove surface damage layers and ensure the ohmic contact surface is flattened. The structure after etching is shown below. Figure 3 As shown.

[0050] S3, Source doped region 8 and Drain doped region 9 are fabricated on p-GaN layer 4. Two high-concentration N+ doped regions are formed in p-GaN layer 4 using ion implantation technology, serving as source doped region 8 and drain doped region 9, respectively. The implanted donor impurity is Si ions, with an implantation concentration ranging from 10⁻⁶. 18 ~10 19 cm -3 The implantation depth ranged from 0.1 μm to 0.5 μm, and the implantation energy ranged from 50 keV to 500 keV. The structure after fabrication of source doped region 8 and drain doped region 9 is shown below. Figure 4 As shown.

[0051] In step S4, MOSFET source metal 11 and MOSFET drain metal 12 are fabricated on source-doped region 8 and drain-doped region 9, respectively. HEMT source metal 14 and HEMT drain metal 15 are fabricated on barrier layer 7. The metal regions are defined using photolithography, followed by electron beam evaporation deposition of multiple layers of Ti / Al / Ni / Au metal with thicknesses of 20 / 100 / 50 / 100 nm. MOSFET source metal 11, MOSFET drain metal 12, HEMT source metal 14, and HEMT drain metal 15 are formed using a lift-off process. The samples are annealed in a nitrogen or oxygen atmosphere at 400-800℃ for 30-200 s to form ohmic contacts. The structure after metal electrode fabrication is shown below. Figure 5 As shown.

[0052] S5, the upper surface obtained in step S4 is deposited with a MOSFET gate oxide layer 10 and a HEMT gate oxide layer 21 by plasma-enhanced chemical vapor deposition (PECVD). Both are made of high-k dielectric materials (such as Al2O3, SiO2, HfO2, etc.) with a thickness ranging from 10-100 nm. The gate metal region is defined using photolithography, and excess oxide layers are removed using reactive ion etching (RIE) or ICP etching techniques, retaining only the MOSFET gate oxide layer 10 in the MOSFET gate metal 13 region and the HEMT gate oxide layer 21 in the HEMT gate metal 16 region. The structure after fabrication of the MOSFET gate oxide layer 10 and the HEMT gate oxide layer 21 is as follows. Figure 6 As shown.

[0053] S6, HEMT gate metal 16 is fabricated on HEMT gate oxide layer 21, and MOSFET gate metal 13 is fabricated on MOSFET gate oxide layer 10. The gate metal region is defined using photolithography, and then multiple layers of Ni / Au metal are deposited using electron beam evaporation, with each layer having a thickness of 50 / 100 nm. The gate electrode is formed by a lift-off process. The structure after gate metal fabrication is as follows. Figure 7 As shown.

[0054] S7. A first dielectric layer 17 is deposited on the upper surface obtained in step S6 using PECVD. The first dielectric layer 17 is made of SiN, with a thickness ranging from 200-300 nm. NH3 and SiH4 are used as the reactant gases, the deposition reaction temperature is 270°C, the RF power is 50 W, and the cavity pressure is 850 mTorr. The locations of vias are defined using photolithography, and the vias are etched using ICP or RIE etching techniques. A first interconnect metal 19 is deposited above the vias to achieve electrical connection between the MOSFET drain metal 12 and the HEMT source metal 14.

[0055] S8, a second dielectric layer 18 is deposited on the upper surface obtained in step S7 using PECVD. The second dielectric layer 18 is made of SiN with a thickness ranging from 200-300 nm. NH3 and SiH4 are used as the reaction gases, the deposition reaction temperature is 270 °C, the RF power is 50 W, and the cavity pressure is 850 mTorr. The locations of vias are defined using photolithography, and the vias are etched using ICP or RIE etching techniques. A second interconnect metal 20 is deposited above the vias to achieve electrical connection between the MOSFET source metal 11 and the HEMT gate metal 16.

[0056] The monolithically integrated GaN Cascode device fabricated through the above steps achieves compact integration of GaN MOSFET devices and GaNHEMT devices on the same silicon substrate. This monolithic integration significantly reduces the area of ​​the GaN Cascode device and improves integration density. Furthermore, this device eliminates parasitic inductance and capacitance caused by external interconnections in discrete structures, improving switching speed and reducing switching losses. In addition, a high power density is maintained through an efficient heat dissipation structure, and the positive threshold characteristic of GaN MOSFET devices is utilized to achieve normally-off functionality, balancing gate reliability and driving simplicity.

[0057] In actual operation, when the GaN Cascode device receives an input signal, the MOSFET gate metal 13 serves as the gate control signal for the entire device, controlling the MOSFET's conduction state. When the MOSFET is turned on, current flows from the HEMT drain metal 15 to the HEMT source metal 14, then through the first interconnect metal 19 to the MOSFET drain metal 12, and finally through the MOSFET source metal 11 and the second interconnect metal 20 to the HEMT gate metal 16, completing the entire current path. Because GaN MOSFET devices have a positive threshold characteristic, they can achieve normally-off functionality, thereby improving device reliability. Simultaneously, the high mobility and high saturated electron velocity characteristics of GaN HEMT devices enable them to maintain excellent performance under high-frequency conditions.

[0058] In summary, this invention achieves compact integration of GaN MOSFET and GaN HEMT devices on the same silicon substrate, overcoming the technical bottlenecks of traditional cascaded cascode devices in high-frequency, high-power applications. Overall, it outperforms the traditional Si MOSFET+GaN HEMT solution in terms of area, cost, and reliability, providing a superior technical solution for high-frequency, high-power applications.

[0059] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A monolithically integrated GaN Cascode device, characterized in that, include: Substrate; GaN MOSFET devices integrated on a substrate and GaN HEMT devices located on GaN MOSFET devices; The GaN MOSFET device and GaN HEMT device are electrically connected through a metal interconnect structure; as well as Dielectric layer covering GaN MOSFET devices and GaN HEMT devices; The GaN MOSFET device includes a GaN MOSFET epitaxial structure consisting of a nucleation layer, a MOSFET buffer layer, and a p-GaN layer, from bottom to top, including a substrate, and a source doped region, a MOSFET source metal, a drain doped region, a MOSFET drain metal, a MOSFET gate oxide layer, and a MOSFET gate metal disposed on the p-GaN layer; wherein, the MOSFET gate metal serves as the gate of the GaN Cascode device; The GaN HEMT device includes, from bottom to top, a HEMT buffer layer, a channel layer, and a barrier layer disposed on a p-GaN layer; and a HEMT source metal, a HEMT drain metal, a HEMT gate oxide layer, and a HEMT gate metal disposed on the barrier layer; wherein, the HEMT drain metal serves as the drain of the GaN Cascode device structure.

2. The monolithically integrated GaN Cascode device according to claim 1, characterized in that, The metal interconnect structure includes a first interconnect metal connecting the drain metal of the MOSFET and the source metal of the HEMT, and a second interconnect metal connecting the source metal of the MOSFET and the gate metal of the HEMT.

3. The monolithically integrated GaN Cascode device according to claim 2, characterized in that, The dielectric layer includes a first dielectric layer covering the upper surface of the MOSFET gate oxide layer and a second dielectric layer covering the upper surface of the first dielectric layer and the first interconnect metal; the first dielectric layer and the second dielectric layer are made of one or more insulating materials such as AlN, Al2O3, SiO2, Si3N4, AlON, and SiON, and their thickness is 100~300nm.

4. The monolithically integrated GaN Cascode device according to claim 3, characterized in that, The nucleation layer is made of either AlN or AlGaN, and its thickness ranges from 30 to 100 nm; the MOSFET buffer layer is made of any one or more combinations of AlN, AlGaN, InGaN, and GaN, and its thickness ranges from 1000 to 4000 nm; the p-GaN layer is a p-GaN layer doped with Mg, Zn, or Ca, and its thickness ranges from 500 to 1000 nm.

5. The monolithically integrated GaN Cascode device according to claim 4, characterized in that, The HEMT buffer layer is made of any one or more combinations of AlN, AlGaN, InGaN, and GaN, with a thickness ranging from 1000 to 4000 nm; the channel layer is made of undoped GaN, with a thickness ranging from 100 to 300 nm; and the barrier layer is made of AlGaN, with a thickness ranging from 50 to 100 nm.

6. The monolithically integrated GaN Cascode device according to claim 5, characterized in that, The MOSFET gate oxide layer is made of one of the high-k dielectric materials Al2O3, SiO2, HfO2, Si3N4, and AlON, and its thickness ranges from 10 to 100 nm.

7. A monolithically integrated GaN Cascode device according to claim 6, characterized in that, Both the source and drain doped regions are heavily N-type doped, and the doping element is one of Si, O, Ge, or C.

8. The monolithically integrated GaN Cascode device according to claim 7, characterized in that, The MOSFET source metal, MOSFET drain metal, HEMT source metal, HEMT drain metal, first interconnect metal, and second interconnect metal are all made of ohmic contact metal.

9. A monolithically integrated GaN Cascode device according to claim 8, characterized in that, The MOSFET gate metal and HEMT gate metal are Schottky contact metals, made of Ni / Au multilayer metal, wherein the thickness of Ni is 20~50nm and the thickness of Au is 50~100nm.

10. A method for fabricating a monolithically integrated GaN Cascode device, characterized in that, The method for fabricating the GaN Cascode device as described in claim 8 includes the following steps: Step 1: Obtain a silicon substrate, and epitaxially grow a nucleation layer, a MOSFET buffer layer, and a p-GaN layer on the substrate in sequence as the epitaxial structure of a GaN MOSFET device. Then, continue to epitaxially grow a HEMT buffer layer, a channel layer, and a barrier layer as the epitaxial structure of a GaN HEMT device. Step 2: Etch the epitaxial structure of the GaN MOSFET device: etch away part of the barrier layer, channel layer and HEMT buffer layer to expose the bottom p-GaN layer; Step 3: Fabricate source-doped and drain-doped regions on the p-GaN layer; Step 4: Fabricate MOSFET source metal and MOSFET drain metal on the source doped region and drain doped region, and fabricate HEMT source metal and HEMT drain metal on the barrier layer; Step 5: Fabricate the MOSFET gate oxide layer and the HEMT gate oxide layer on the upper surface obtained in Step 4; Step 6: Fabricate HEMT gate metal on the HEMT gate oxide layer, and fabricate MOSFET gate metal on the MOSFET gate oxide layer; Step 7: Deposit the first dielectric layer and the second dielectric layer on the upper surface obtained in step 6; Step 8: Etch vias and deposit metal interconnect structures above the electrodes of the GaN MOSFET device and the GaN HEMT device to connect the MOSFET drain metal to the HEMT source metal and the MOSFET source metal to the HEMT gate metal; wherein, the MOSFET source metal, after being connected to the HEMT gate metal, serves as the source of the GaN Cascode device.

Images