Bandwidth allocation modules, multi-core processors, and computer systems

Abstract

A bandwidth allocation module, a multi-core processor, and a computer system are disclosed, relating to the field of data processing technology. The bandwidth allocation module is applied to a multi-core processor, which includes N cores and a corresponding near-end memory for each core, where N is greater than or equal to 2. The bandwidth allocation module includes write data channels, each containing a fully reduced channel corresponding to one of the N cores. The bandwidth allocation module is configured to: receive data from the N cores and temporarily store it in the fully reduced channel corresponding to each core; generate a write data request corresponding to the fully reduced channel when the amount of temporarily stored data reaches W; grant each fully reduced channel write data permission once per write data cycle; and, when the fully reduced channel simultaneously has both a write data request and write data permission, write the temporarily stored data in the fully reduced channel to a target memory, where the amount of data written is W, and the target memory is a near-end memory with a bit width of W corresponding to a target core, and the target core is one of the N cores.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and more particularly to a bandwidth allocation module, a multi-core processor, and a computer system. Background Technology

[0002] To address the high demands for data transfer efficiency in scenarios such as high-performance computing, distributed training, and parallel algorithms, multi-core processors typically employ an all-reduce mode for data transfer and aggregation between multiple cores. In this mode, when multiple cores in a multi-core processor write data to the near-end memory of a single core, the cores write sequentially according to the order of the write requests. During this process, each core occupies the full width of the near-end memory, and the next core writes only after all the data on one core has been written. For scenarios with high data concurrency, this data transfer mode carries the risk of data blocking, thus impacting the data processing efficiency of the multi-core processor. Summary of the Invention

[0003] This disclosure provides a bandwidth allocation module, a multi-core processor, and a computer system.

[0004] In a first aspect, embodiments of this disclosure provide a bandwidth allocation module applied to a multi-core processor, the processor including N cores and a near-end memory corresponding to each core, where N is greater than or equal to 2; the bandwidth allocation module includes a write data channel, the write data channel including N fully reduced channels corresponding one-to-one with the N cores; the bandwidth allocation module is configured to: receive data from the N cores and temporarily store it in the fully reduced channel corresponding to each core; generate a write data request corresponding to the fully reduced channel when the amount of temporarily stored data reaches W; grant each fully reduced channel write data permission once in each write data cycle; and, when the fully reduced channel has both a write data request and write data permission, write the temporarily stored data in the fully reduced channel to the target memory, where the amount of data written is W, the target memory is the near-end memory with a bit width of W corresponding to the target core, and the target core is one of the N cores.

[0005] Secondly, embodiments of this disclosure provide a multi-core processor, including N cores, each core being provided with a near-end memory, a data transport module, and a bandwidth allocation module as described in the above embodiments; N is greater than or equal to 2; the data transport module is configured to transport data from the N cores to the bandwidth allocation module; the bandwidth allocation module is configured to distribute received data to the corresponding write data channel; and, in each write data cycle, data in the full-protocol channel that simultaneously has write data permission and write data request is written to the near-end memory of the corresponding core, and the amount of data written is consistent with the bit width of the write interface of the near-end memory.

[0006] Thirdly, this disclosure provides a computer system including the multi-core processor described in the above embodiments.

[0007] The bandwidth allocation module of this embodiment sets up a corresponding fully reduced channel for each core in a multi-core processor to temporarily store data from that core, and grants each fully reduced channel one write data permission in each write data cycle, so that each fully reduced channel corresponding to each core can get one opportunity to write data in a write data cycle. When the data temporarily stored in the fully reduced channel reaches the bit width W of the target memory, a write data request is generated. The fully reduced channel with both the write data request and the write data permission can write data of amount W to the target memory. In this way, each core in the multi-core processor can get a relatively fair opportunity to write data, and it can also ensure that the core with data amount reaching the bit width of the target memory can write first, which can effectively avoid data blocking and make full use of the bit width of the target memory, thereby improving the data transmission efficiency of the multi-core processor in fully reduced mode.

[0008] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0010] Figure 1 A schematic diagram of the structure of one embodiment of the bandwidth allocation module of this disclosure; Figure 2 A schematic diagram of the structure of yet another embodiment of the bandwidth allocation module of this disclosure; Figure 3 A schematic diagram of the structure of yet another embodiment of the bandwidth allocation module of this disclosure; Figure 4 This is a schematic diagram of the structure of one embodiment of the multi-core processor disclosed herein. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0012] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0013] The ordinal numbers such as "first" and "second" in this disclosure are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0014] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0015] like Figure 1 As shown, this disclosure provides a bandwidth allocation module applied to a multi-core processor, which may include N cores and a local memory corresponding to each core; wherein N is greater than or equal to 2.

[0016] Here, near-end memory refers to memory units that are physically close to the processor core. They typically have advantages such as short transmission paths and low access latency. For example, it can be SRAM (Static Random-Access Memory) integrated on the same chip as the core.

[0017] In this embodiment, the multi-core processor has a corresponding local memory for each core. When the multi-core processor is in all-reduce mode, each core can write data to the local memory of other cores through a specific channel, and also write local data to its local local memory through the same channel. This channel is the all-reduce channel in this embodiment. Each core can also have a corresponding remote memory (e.g., DRAM (Dynamic Random-Access Memory)) and a data transfer module (e.g., DMA (Direct Memory Access)). The data transfer module can transfer data from local remote memory to local local local memory, and can also transfer data from the local local memory or remote memory of other cores to local local local memory.

[0018] In this embodiment, the bandwidth allocation module includes write data channels, which include N fully reduced channels corresponding one-to-one with the N cores. The bandwidth allocation module is configured to: receive data from the N cores and temporarily store it in the fully reduced channel corresponding to each core; generate a write data request corresponding to the fully reduced channel when the amount of temporarily stored data reaches W; grant each fully reduced channel write data permission once in each write data cycle; and, when the fully reduced channel has both a write data request and write data permission, write the temporarily stored data in the fully reduced channel to the target memory, and the amount of data written is W. The target memory is a near-end memory with a bit width of W corresponding to the target core, and the target core is one of the N cores.

[0019] In this embodiment, the bandwidth allocation module can be configured to write data to the near-end memory (i.e., the target memory of the target core) of any one of the cores in the multi-core processor. When the multi-core processor is in full reduction mode, each core of the multi-core processor can write data to the near-end memory of other cores.

[0020] Here, the target memory bit width of W indicates that the target memory write interface bit width is W bits. Correspondingly, the data volume of W indicates the data volume corresponding to W bits, such as W / 8 bytes.

[0021] The bandwidth allocation module can be set in hardware between the target memory and the data transport module corresponding to the target core. The input of the bandwidth allocation module is connected to the output of the data transport module so as to receive data from the target core and other cores. At the same time, the output of the bandwidth allocation module is connected to the write interface of the near-end memory so as to write data to the near-end memory.

[0022] As an example, assume a multi-core processor has three cores: core0, core1, and core2. Taking the bandwidth allocation module corresponding to core0 as an example, its write data channel includes three fully reduced channels. Fully reduced channel 0 corresponds to core0 itself and can be used to read data from other memories of core0 and write it to the near-end memory of core0. Fully reduced channel 1 corresponds to core1 and is used to receive data from core1 for writing to the near-end memory of core0. Fully reduced channel 2 corresponds to core2 and is used to receive data from core2 for writing to the near-end memory of core0. Here, the fully reduced channels can be buffered to temporarily store received data and generate a write data request when the temporarily stored data reaches the bit width W of the target memory. The bit width of the write data request can be W.

[0023] In this embodiment, the bandwidth allocation module can sequentially grant write data permissions to each full-protocol channel so that the write interface of the target memory can be opened to each full-protocol channel in sequence. Each round of write data permission is a write data cycle.

[0024] Continuing with the example above, the bandwidth allocation module can be set with a loop counter from 0 to 2. When the loop counter reading is 0, full-reduction channel 0 obtains write data permission; when the loop counter reading is 1, full-reduction channel 1 obtains write data permission; and when the loop counter is 2, full-reduction channel 2 obtains write data permission. When a full-reduction channel simultaneously has write data permission and a write data request, the data temporarily stored in that full-reduction channel can be written to the target memory. Here, the bit width of the write data request is W, which ensures that data writing can be completed in a single write operation, avoiding prolonged occupation of the target memory's write interface and preventing data blocking.

[0025] The bandwidth allocation module of this embodiment sets up a corresponding fully reduced channel for each core in a multi-core processor to temporarily store data from that core, and grants each fully reduced channel one write data permission in each write data cycle, so that each fully reduced channel corresponding to each core can get one opportunity to write data in a write data cycle. When the data temporarily stored in the fully reduced channel reaches the bit width W of the target memory, a write data request is generated. The fully reduced channel with both the write data request and the write data permission can write data of amount W to the target memory. In this way, each core in the multi-core processor can get a relatively fair opportunity to write data, and it can also ensure that the core with data amount reaching the bit width of the target memory can write first, which can effectively avoid data blocking and make full use of the bit width of the target memory, thereby improving the data transmission efficiency of the multi-core processor in fully reduced mode.

[0026] In some embodiments, the write data cycle includes N cycles; the bit width of the full protocol channel receiving data is W / N, and W / N of the data can be received in each cycle.

[0027] In this embodiment, "pause" can represent one or more clock cycles required for a single write operation to the target memory.

[0028] Continuing with the example above, let's illustrate this further. The cycle counter in the bandwidth allocation module can count cycles per beat. Assuming the cycle counter reads 2 in the current beat, full-protocol channel 2 gains write data permission. Simultaneously, with data input, each of the three full-protocol channels can receive and temporarily store W / 3 of the data. In the next beat, the cycle counter reads 0, and full-protocol channel 0 gains write data permission. Assuming full-protocol channels 0 and 1 have already received two data inputs previously, and receive another W / 3 of the data in this beat, then the full-protocol channel... When the data temporarily stored in both full reduction channel 0 and full reduction channel 1 reaches W, both full reduction channels 0 and 1 generate write data requests with a bit width of W. Since full reduction channel 0 has write data permission, the data temporarily stored in full reduction channel 0 can be written to the target memory. In the next cycle, the reading of the loop counter becomes 1, and full reduction channel 1 obtains write data permission. At this time, full reduction channel 1 can write data to the target memory. This data comes from the memory of core 1, which realizes the operation of core 1 writing data to core 0.

[0029] In this embodiment, the bit width of the full-protocol channel receiving data is set to W / N, so that the full-protocol channel can receive a maximum of W data in one write data cycle. Only one write operation is needed to write this part of the data to the target memory, so that the speed of receiving data in the full-protocol channel matches the speed of writing data to the target memory, avoiding data blocking and back pressure phenomena, and enabling the bandwidth allocation module to improve the data transmission efficiency of multi-core processors in full-protocol mode.

[0030] The following is for reference. Figure 2 ,exist Figure 2 In the embodiment shown, the bandwidth allocation module is further provided with a data bit width converter 210 before the full-protocol data channel. The data bit width converter 210 is configured to convert the bit width of the received local data to W / N and then send it to the full-protocol channel corresponding to the target core and other cores; wherein, the local data comes from other memory corresponding to the target core.

[0031] As an example, a multi-core processor can assign a corresponding DMA to each core as a data transfer module for that core, enabling data transfer from local memory and other cores. The input of the data bit-width converter 210 can be connected to the output of the DMA to receive data transferred from local memory, then convert the received data bit-width to W / N before sending it to the full-reduction channel corresponding to the target core and other cores. In this way, the data bit-width received by the full-reduction channel corresponding to the target core in the bandwidth allocation module of other cores is also W / N.

[0032] In this embodiment, the bandwidth allocation module can convert the received local data bit width to W / N using a data bit width converter before sending it to the full protocol channel corresponding to the target core and other cores. This can make full use of the bit width of the full protocol channel receiving data and avoid data blocking at the full protocol channel receiver.

[0033] Next, refer to Figure 2 In some embodiments, each full protocol channel is provided with a data collector 220, which is configured to temporarily store the received data and generate a write data request when the amount of stored data reaches W.

[0034] As an example, data collector 220 can be configured with a buffer for temporary data storage. The full-reduction channel can receive W / N data per clock cycle during a write data cycle. This data can be temporarily stored in data collector 220, allowing data collector 220 to temporarily store up to W data in a single write data cycle. When data collector 220 detects that the amount of data in the buffer has reached W, it can generate a write request with a bit width of W to write the data to the target memory upon obtaining write access.

[0035] In this embodiment, the bandwidth allocation module sets up a data collector in the full protocol channel to temporarily store data, and generates a write data request when the amount of stored data reaches the bit width of the target memory. This can avoid occupying the write interface of the target memory when the amount of temporarily stored data is small, which helps to alleviate data contention and bandwidth waste.

[0036] In some optional implementations of this embodiment, the data collector includes a FIFO (First In First Out) buffer with a capacity of not less than 2W for temporarily storing the received data.

[0037] As an example, the FIFO buffer capacity can be 2W, 2.5W, 3W, or others. Assume the multi-core processor has 8 cores, i.e., N=8. Correspondingly, the bandwidth allocation module includes 8 write data channels, with each write data cycle consisting of 8 clock cycles. Each fully reduced-resolution channel obtains write data permission once every 8 clock cycles, and each fully reduced-resolution channel can receive a maximum of W / 8 data per clock cycle.

[0038] When a fully standardized channel has received and temporarily stored data 8 or more times and has obtained write data permission, the bandwidth allocation module can write the data of size W that was first stored in the FIFO buffer of that fully standardized channel to the target memory. If a fully standardized channel has received less than 8 data times when it obtains write data permission, that fully standardized channel will not generate a write data request.

[0039] In some cases, a fully reduced channel may have already stored 7 data entries and is receiving the 8th data entry, and has obtained write permission. Since no write request has been generated yet, the fully reduced channel needs to wait 8 more cycles before obtaining write permission. During this period, the fully reduced channel may need to store up to 8 more data entries. The FIFO buffer capacity is no less than 20,000, which ensures that the data received by the fully reduced channel will not overflow within 2 write cycles, thus avoiding data blocking. This enables data transmission without backpressure in fully reduced mode for multi-core processors, further improving the throughput and stability of data transmission for multi-core processors.

[0040] As the performance of deep learning models continues to improve, the amount of data involved in the training and inference processes is increasing, leading to higher demands for data transmission efficiency. Consequently, multi-core processors are employing increasingly sophisticated data processing methods. For example, in the feedforward neural network computation of the Transformer model, a multi-core processor can use DMA's fully reduced mode to read data from its own core while simultaneously writing to the local memory of both the core and other cores. Conversely, in the attention computation of the Transformer model, a multi-core processor can use DMA's non-fully reduced channel mode to read data from its own core and write only to the local memory of that core.

[0041] For the aforementioned application scenarios, the write data channel of the bandwidth allocation module disclosed herein also includes a non-full-protocol channel with reverse pressure, such as... Figure 3 As shown, the input of the write data channel of the bandwidth allocation module is connected to the output of the DMA to receive data. The write data channel includes a non-fully reduced channel and N fully reduced channels. The non-fully reduced channel can be used for data transfer in the non-fully reduced mode of the DMA, that is, the DMA reads local data (i.e., data in the memory corresponding to the target core) and writes data only to the target memory. The fully reduced channel corresponding to the target core can be used in the fully reduced mode of the DMA, that is, the DMA reads local data and simultaneously writes to the target memory and the near-end memory of other cores.

[0042] Here, the non-full-recommendation channel adopts a design with backpressure, and the write data permission priority of the non-full-recommendation channel is lower than that of the full-recommendation channel to ensure the priority of writing data to the full-recommendation channel.

[0043] In this embodiment, the bandwidth allocation module is further configured to: receive local data and generate a write data request corresponding to a non-full-protocol channel, so as to write the local data to the target memory through the non-full-protocol channel. The local data originates from other memories corresponding to the target core.

[0044] In this way, write data requests in non-full-reduction mode of DMA can be merged into the write data channel with low priority and backpressure. DMA only needs one data output interface to realize data transmission in both modes through the two channels of the bandwidth allocation module, which can greatly reduce the hardware overhead of multi-core processors.

[0045] exist Figure 3 In the illustrated embodiment, the target memory may include multiple memory chips, such as Figure 3 The SRAM_0~SRAM_m in the bandwidth allocation module. The bandwidth allocation module may also include a routing module 310 (i.e., Figure 3 Router in the middle), Arbitration module 320 (i.e. Figure 3 Arbiter in the middle) and time division multiplexing module 330 (i.e. Figure 3 In the TDM (Time Division Multiplexing) configuration, the routing module 310 is configured to write data to the storage chip pointed to by the received write data request; the arbitration module 320 is configured to grant write data permissions to the write data channel according to priority and send the write data request corresponding to the write data channel with write data permission to the routing module 310; the time division multiplexing module 330 is configured to receive the write data request corresponding to the full protocol channel and send the write data request to the arbitration module 320 according to the time division multiplexing strategy.

[0046] Continue to combine Figure 3 An illustrative example is provided. Assume a multi-core processor has N cores: core0 to coreN-1, each with a corresponding DMA and near-end memory. Core0 will be used as the target core for this example. The bandwidth allocation module's write data channel includes a non-fully-reduced channel and N fully-reduced channels. The input of the write data channel is connected to the output of the DMA to receive data. When a non-fully-reduced channel receives local data transmitted by the DMA in non-fully-reduced mode, the bandwidth allocation module generates a write data request corresponding to that non-fully-reduced channel (e.g., ...). Figure 3 The self-only mode Req is sent to the arbitration module 320.

[0047] DMA can transfer data from any one or more cores from core0 to coreN-1 in full-reduction mode. Local data transferred by DMA in full-reduction mode is processed by a data bit-width converter 340 (e.g., ...). Figure 3 After being converted into data with a bit width of W / N by the Downsizer in the core, it is sent to the full reduction channel 0 corresponding to core 0 and other cores (e.g., the full reduction channel corresponding to core 0 in the bandwidth allocation module of core 1, the full reduction channel corresponding to core 0 in the bandwidth allocation module of core 2, etc.). The data is then collected by the data collector in the full reduction channel (e.g., Figure 3The DMA (Collector) temporarily stores the data. For data from other cores, which has already been converted to W / N bandwidth by the other cores' data bit-width converters, the DMA can directly distribute the data to the corresponding full-reduction channel according to its source. For example, data from core1 is distributed to full-reduction channel 1, and data from coreN-1 is distributed to full-reduction channel N-1.

[0048] When the amount of data temporarily stored in a certain full-protocol channel reaches W, the data collector of that full-protocol channel can generate a write data request with a bit width of W and send it to the time-division multiplexing module 330. The time-division multiplexing module 330 then sends multiple write data requests to the arbitration module 320 according to the time-division multiplexing module.

[0049] Arbitration module 320 can manage write data permissions for full-protocol channels and non-full-protocol channels based on the priority of the write data channels. Since full-protocol channels have higher priority than non-full-protocol channels, when arbitration module 320 receives a write data request from a full-protocol channel, it can sequentially grant write data permissions to each full-protocol channel and send the write data request corresponding to the full-protocol channel with write data permission to routing module 310. During this process, if a write data request from a non-full-protocol channel is received, it can be temporarily suspended until the write data request from the full-protocol channel is processed before granting write data permissions to the non-full-protocol channel and sending the write data request from the non-full-protocol channel to routing module 310. Routing module 310 can then write data to the specified storage chip according to the write data request.

[0050] In this embodiment, the arbitration module and the time-division multiplexing module schedule the write data requests and write data permissions of the write data channel, and then the data writing is completed through the routing module, which can reduce the hardware consumption of the bandwidth allocation module.

[0051] Figure 4 A schematic diagram of the structure of one embodiment of the multi-core processor of this disclosure is shown, as follows: Figure 4 As shown, multiple processors can include N cores (e.g., Figure 4 In the above embodiments, core0 to coreN-1 are configured, each core has a corresponding near-end memory, a data transfer module, and a bandwidth allocation module; N is greater than or equal to 2; wherein, the data transfer module is configured to transfer data from N cores to the bandwidth allocation module; the bandwidth allocation module is configured to distribute the received data to the corresponding write data channel; and, in each write data cycle, the data in the full-protocol channel that has both write data permission and write data request is written to the near-end memory of the corresponding core, and the amount of data written is consistent with the bit width of the write interface of the near-end memory.

[0052] In this embodiment, a bandwidth allocation module is used to realize data transmission in a multi-core processor, which can effectively avoid data blocking and make full use of the write data bit width of the near-end memory, thus helping to improve the data transmission efficiency of the multi-core processor.

[0053] In some optional implementations of this embodiment, each bandwidth allocation module is connected to the bandwidth allocation modules corresponding to other cores to send the received local data to the bandwidth allocation modules corresponding to other cores.

[0054] As an example, in the bandwidth allocation module corresponding to core0, full-reduction channel 0 is used to temporarily store local data transferred by DMA in full-reduction mode; in the bandwidth allocation module corresponding to core1, full-reduction channel 1 is used to receive data from core0, and in the bandwidth allocation module corresponding to core2, full-reduction channel 2 is used to receive data from core0. Therefore, the bandwidth allocation module corresponding to core0 can not only write local data to the near-end memory of core0 through full-reduction channel 0, but also send the temporarily stored local data to full-reduction channel 1 in the bandwidth allocation module corresponding to core1 and full-reduction channel 2 in the bandwidth allocation module corresponding to core2, so that this data can be written to the near-end memory of core1 and core2 respectively.

[0055] In this embodiment, connecting the bandwidth allocation modules corresponding to different cores can further improve the data transmission efficiency between different cores.

[0056] This disclosure also provides a computer system including the multi-core processor described in the above embodiments.

[0057] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A bandwidth allocation module applied to a multi-core processor, characterized in that, The processor includes N cores and a corresponding near-end memory for each core, where N is greater than or equal to 2; the processor is in full reduction mode. The bandwidth allocation module includes a write data channel, and the write data channel includes N full-protocol channels that correspond one-to-one with the N cores. The bandwidth allocation module is configured to: receive data from the N cores and temporarily store it in the full protocol channel corresponding to each core; generate a write data request corresponding to the full protocol channel when the amount of temporarily stored data reaches W; and grant each full protocol channel write data permission once in each write data cycle. Furthermore, when the full-reduction channel simultaneously has a write data request and write data permission, the data temporarily stored in the full-reduction channel is written to the target memory, and the amount of data written is W. The target memory is a near-end memory with a bit width of W corresponding to the target core, and the target core is one of the N cores.

2. The bandwidth allocation module according to claim 1, characterized in that, The data writing cycle includes N cycles; The bit width of the full protocol channel for receiving data is W / N, and W / N of the data can be received per frame.

3. The bandwidth allocation module according to claim 2, characterized in that, It also includes a data bit-width converter, configured to convert the bit width of the received local data to W / N and then send it to the full reduction channel corresponding to the target core and other cores; the local data comes from other memories corresponding to the target core.

4. The bandwidth allocation module according to claim 1, characterized in that, Each of the full protocol channels is equipped with a data collector, which is configured to temporarily store the received data and generate a write data request when the amount of stored data reaches W.

5. The bandwidth allocation module according to claim 4, characterized in that, The data collector includes a FIFO buffer with a capacity of not less than 2W for temporarily storing the received data.

6. The bandwidth allocation module according to claim 1, characterized in that, The write data channel also includes a non-full-reduction channel with backpressure, and the write data permission priority of the non-full-reduction channel is lower than that of the full-reduction channel; The bandwidth allocation module is further configured to: receive local data and generate a write data request corresponding to the non-full-protocol channel, so as to write the local data to the target memory through the non-full-protocol channel; The local data comes from other memory corresponding to the target core.

7. The bandwidth allocation module according to any one of claims 1 to 6, characterized in that, The target memory includes multiple memory chips; The bandwidth allocation module further includes a routing module, an arbitration module, and a time-division multiplexing module. The routing module is configured to write data to the storage chip pointed to by the received write data request. The arbitration module is configured to grant write data permissions to the write data channel according to priority and send the write data request corresponding to the write data channel with write data permissions to the routing module. The time-division multiplexing module is configured to receive the write data request corresponding to the full protocol channel and send the write data request to the arbitration module according to the time-division multiplexing strategy.

8. A multi-core processor, characterized in that, It includes N cores, each core being equipped with a near-end memory, a data transport module, and a bandwidth allocation module as described in any one of claims 1 to 7; N is greater than or equal to 2. The data transfer module is configured to transfer the data from the N cores to the bandwidth allocation module; The bandwidth allocation module is configured to distribute received data to the corresponding write data channel; In addition, during each write data cycle, data from the full-reduction channel that simultaneously has write data permissions and write data requests is written to the near-end memory of the corresponding core, and the amount of data written is consistent with the bit width of the write interface of the near-end memory.

9. The multi-core processor according to claim 8, characterized in that, Each of the bandwidth allocation modules is connected to the bandwidth allocation modules corresponding to other cores to send the received local data to the bandwidth allocation modules corresponding to other cores.

10. A computer system comprising the multi-core processor of claim 8.

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