A type-c interface protocol intelligent testing method, system and storage medium

Abstract

The application provides a Type-C interface protocol intelligent testing method and system and a storage medium. First, electrical information of a Type-C interface is collected, and standardized signal data is obtained through filtering and preprocessing. Then, VBUS signal threshold judgment and channel signal threshold range verification are sequentially performed to complete physical layer and electrical parameter verification. After passing the basic verification, signal sequences are extracted and input into a preset protocol state machine for protocol compliance judgment. According to the judgment result, handshake communication messages are parsed or structured test state results are generated. Finally, an indication instruction is output and can respond to a feedback signal, and the signal threshold parameter is dynamically optimized through a pre-trained adjustment model. Thus, full-automatic testing from electrical characteristics to protocol logic is realized, and the testing efficiency and accuracy are improved. Based on the adaptive learning ability, different equipment and cable characteristics are adapted, and the technical problem of effectively adapting to a complex protocol scene is solved.

Description

Technical Field

[0001] This invention relates to the field of Type-C interface protocol testing, and more specifically, to a Type-C interface protocol intelligent testing method, system, and storage medium. Background Technology

[0002] With the widespread adoption of Type-C interfaces in smartphones, laptops, tablets, and other electronic devices, their complex protocol stacks and diverse functions make protocol conformance testing a critical step in equipment development, production, and maintenance. However, existing Type-C protocol testing technologies still have many limitations, severely restricting testing efficiency and reliability. Traditional testing methods heavily rely on large, dedicated testing instruments, such as protocol analyzers and oscilloscopes. These instruments are not only expensive and complex to operate, but also lack portability, making them unsuitable for on-site debugging or rapid troubleshooting. Furthermore, existing testing methods often focus on single-point measurements of electrical parameters, lacking in-depth analysis of the timing logic of the protocol state machine and the content of handshake messages. This results in an inability to effectively diagnose latent faults caused by protocol incompatibility, timing deviations, or communication logic errors. More importantly, the threshold parameters of traditional testing equipment are usually fixed and cannot adapt to different device models, cable characteristics, or environmental changes, easily leading to false alarms or missed alarms and poor consistency of test results.

[0003] Therefore, there is an urgent need for a Type-C protocol testing technology based on intelligent threshold comparison and protocol status analysis. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide an intelligent testing method, system, and storage medium for Type-C interface protocols. Firstly, through a multi-channel synchronous sampling and signal preprocessing mechanism, the electrical signals of the Type-C interface are filtered, normalized, and baseline calibrated to effectively suppress noise interference and improve signal quality and test repeatability. Based on this, a hierarchical threshold verification strategy is adopted to sequentially complete physical connection verification and electrical parameter compliance checks, gradually eliminating underlying anomalies and accurately locating fault points. Furthermore, by incorporating a built-in Type-C protocol state machine model, timing events of the CC pin are tracked and state transitions analyzed to achieve automated judgment of protocol compliance, solving the problem that traditional methods cannot detect protocol logic defects. For abnormal situations, this invention can initiate a deep message parsing process to extract and reconstruct handshake communication messages from differential signals, while generating a structured test report providing detailed information such as fault level and suspicious node identification, greatly improving diagnostic transparency and maintenance efficiency. Particularly noteworthy is the introduction of a machine learning-based adaptive optimization mechanism, which uses feedback signals to drive a neural network model to dynamically adjust signal thresholds, enabling the system to continuously learn and adapt, significantly improving its generalization performance to different devices and environmental conditions.

[0005] The first aspect of this invention provides an intelligent testing method for Type-C interface protocols, the method comprising: Collect electrical information from the Type-C interface; Based on the preset filtering and signal preprocessing mechanism, standardized signal data is obtained according to the electrical information; Based on the standardized signal data, determine whether the VBUS signal data is greater than a preset first signal threshold; If so, determine whether the channel signal data is within the preset second signal threshold range; If so, then the signal sequence is extracted based on the standardized signal data; Based on a preset protocol state machine, the system determines whether the signal sequence conforms to the preset protocol specifications. If so, extract the handshake communication message; If not, then generate the test status result; Based on the handshake communication message or the test status result, output an indication command; In response to the feedback signal, the standardized signal data and the instruction are input into the pre-trained adjustment model to correct the range of the first signal threshold and the second signal threshold.

[0006] In this solution, the standardized signal data obtained based on the electrical information through a preset filtering and signal preprocessing mechanism specifically includes: It receives multiple analog electrical signals acquired in real time from the CC pin, VBUS pin, and D+ / D- pin of the Type-C interface; The multiple analog electrical signals are synchronously sampled and converted from analog to digital to obtain a multiple digital signal sequence; A preset moving average and digital filtering algorithm is applied to the multi-channel digital signal sequence to obtain a smooth signal sequence; The smoothed signal sequence is subjected to a preset dimension normalization process to obtain a normalized signal sequence; The normalized signal sequence is subjected to a preset baseline calibration to obtain the standardized signal data.

[0007] In this scheme, after obtaining the standardized signal data, the following steps are included: The VBUS signal data is compared with a preset first signal threshold. If the duration of the signal not exceeding the first signal threshold exceeds the preset first duration, it is determined to be a physical connection abnormality. If the duration of the signal exceeding the first signal threshold exceeds the preset first duration, it is determined that the primary verification has been passed. In response to passing the primary verification, the channel signal data is compared one by one with the preset second signal threshold range; If the duration of any channel signal deviating from the corresponding threshold range exceeds the preset second duration, an amplitude anomaly event is generated and the deviation channel identifier is recorded. If all channel signals are within the corresponding threshold range, the intermediate verification is considered passed.

[0008] In this scheme, the step of determining whether the signal sequence conforms to the preset protocol specification based on the preset protocol state machine specifically includes: The channel signal data is loaded into a preset Type-C protocol state machine model; Based on the CC pin channel signal data, the first timing feature is extracted to identify the notification event; Perform state machine transitions based on the notification events; If the notification event performs a conditional transition according to the preset state machine conditions, it is determined to conform to the protocol specifications; If a timeout occurs and the expected event is not received, or an undefined transfer is triggered, it is determined to be a protocol timing anomaly.

[0009] This plan also includes: In response to the determination of a protocol timing anomaly, the message extraction process is initiated; Bit clock recovery and decoding are performed on the differential signals of data lines D+ / D- to obtain a digital bit stream; Based on the protocol data frame structure, the frame start delimiter and packet identifier are identified from the bit stream to extract the payload data segment. Based on the payload data segment, the handshake communication message is reassembled. In response to the determination of a protocol timing anomaly, the test status generation process is initiated. Based on the error codes of the protocol state machine, structured test state results are generated.

[0010] In this scheme, responding to the feedback signal by inputting the standardized signal data and the instruction to the pre-trained adjustment model to correct the ranges of the first signal threshold and the second signal threshold specifically includes: The current standardized signal data, instructions, and feedback signals are integrated into training samples; The training samples are input into a pre-trained neural network conditioning model to obtain the target threshold. Calculate the deviation between the target threshold and the range of the first signal threshold and the second signal threshold; If the deviation value exceeds a preset deviation threshold, the ranges of the first signal threshold and the second signal threshold are adjusted according to the deviation value.

[0011] A second aspect of the present invention provides a Type-C interface protocol intelligent testing system, including a Type-C interface protocol intelligent testing method program, wherein the Type-C interface protocol intelligent testing method program, when executed by the processor, performs the following steps: Collect electrical information from the Type-C interface; Based on the preset filtering and signal preprocessing mechanism, standardized signal data is obtained according to the electrical information; Based on the standardized signal data, determine whether the VBUS signal data is greater than a preset first signal threshold; If so, determine whether the channel signal data is within the preset second signal threshold range; If so, then the signal sequence is extracted based on the standardized signal data; Based on a preset protocol state machine, the system determines whether the signal sequence conforms to the preset protocol specifications. If so, extract the handshake communication message; If not, then generate the test status result; Based on the handshake communication message or the test status result, output an indication command; In response to the feedback signal, the standardized signal data and the instruction are input into the pre-trained adjustment model to correct the range of the first signal threshold and the second signal threshold.

[0012] In this solution, the standardized signal data obtained based on the electrical information through a preset filtering and signal preprocessing mechanism specifically includes: It receives multiple analog electrical signals acquired in real time from the CC pin, VBUS pin, and D+ / D- pin of the Type-C interface; The multiple analog electrical signals are synchronously sampled and converted from analog to digital to obtain a multiple digital signal sequence; A preset moving average and digital filtering algorithm is applied to the multi-channel digital signal sequence to obtain a smooth signal sequence; The smoothed signal sequence is subjected to a preset dimension normalization process to obtain a normalized signal sequence; The normalized signal sequence is subjected to a preset baseline calibration to obtain the standardized signal data.

[0013] In this scheme, after obtaining the standardized signal data, the following steps are included: The VBUS signal data is compared with a preset first signal threshold. If the duration of the signal not exceeding the first signal threshold exceeds the preset first duration, it is determined to be a physical connection abnormality. If the duration of the signal exceeding the first signal threshold exceeds the preset first duration, it is determined that the primary verification has been passed. In response to passing the primary verification, the channel signal data is compared one by one with the preset second signal threshold range; If the duration of any channel signal deviating from the corresponding threshold range exceeds the preset second duration, an amplitude anomaly event is generated and the deviation channel identifier is recorded. If all channel signals are within the corresponding threshold range, the intermediate verification is considered passed.

[0014] A third aspect of the present invention provides a computer-readable storage medium comprising a Type-C interface protocol intelligent testing method program, wherein when the Type-C interface protocol intelligent testing method program is executed by a processor, it implements the steps of the Type-C interface protocol intelligent testing method as described in any of the preceding claims.

[0015] This invention provides an intelligent testing method, system, and storage medium for Type-C interface protocols. First, it collects electrical information from the Type-C interface and obtains standardized signal data through filtering and preprocessing. Then, it sequentially performs VBUS signal threshold judgment and channel signal threshold range verification to complete physical layer and electrical parameter verification. After passing the basic verification, it extracts the signal sequence and inputs it into a preset protocol state machine for protocol compliance judgment. Based on the judgment result, it parses handshake communication messages or generates structured test status results. Finally, it outputs indication commands and can respond to feedback signals, dynamically optimizing signal threshold parameters through a pre-trained adjustment model. This achieves fully automated testing from electrical characteristics to protocol logic, improving testing efficiency and accuracy. Based on adaptive learning capabilities, it adapts to different device and cable characteristics, effectively addressing technical problems in complex protocol scenarios. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope.

[0017] Figure 1 A flowchart of an intelligent testing method for a Type-C interface protocol according to the present invention is shown; Figure 2 This invention provides a flowchart of filtering and signal preprocessing for electrical information according to an embodiment of the present invention. Figure 3 This invention provides a flowchart of primary and intermediate verification processes for standardized signal data according to an embodiment of the present invention. Figure 4A block diagram of a Type-C interface protocol intelligent testing system according to the present invention is shown. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used in embodiments of this invention shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in a common dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as being interpreted in an idealized or highly formalized sense, unless expressly defined in this embodiment of the invention.

[0020] The terms "first," "second," and similar words used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "an," "a," or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Similarly, terms such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The steps preceding or following the steps in the method of the embodiments of this invention are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0021] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0022] A smart test circuit for a Type-C interface protocol includes two Type-C interfaces arranged in reverse, with their pins connected in reverse series. Specifically, the first pin of the first Type-C interface is connected to the last first pin of the second Type-C interface; the second pin of the first Type-C interface is connected to the last second pin of the second Type-C interface, and so on.

[0023] Figure 1 A flowchart of an intelligent testing method for a Type-C interface protocol according to the present invention is shown.

[0024] like Figure 1 As shown, the first aspect of this invention discloses an intelligent testing method for a Type-C interface protocol, the method comprising: S102, collects electrical information from the Type-C interface; S104, Based on the preset filtering and signal preprocessing mechanism, standardized signal data is obtained according to the electrical information; S106, Based on the standardized signal data, determine whether the VBUS signal data is greater than a preset first signal threshold; S108, if so, determine whether the channel signal data is within the preset second signal threshold range; S110, if so, then extract the signal sequence based on the standardized signal data; S112, based on the preset protocol state machine, determine whether the signal sequence conforms to the preset protocol specification; S114, if yes, then extract the handshake communication message; S116, if not, generate test status results; S118, output an indication command based on the handshake communication message or the test status result; S120, in response to the feedback signal, the standardized signal data and the instruction are input into the pre-trained adjustment model to correct the range of the first signal threshold and the second signal threshold.

[0025] It should be noted that the electrical information refers to the voltage or current values ​​of the Type-C interface pins. In this embodiment, the voltage or current signals of the Type-C interface pins are first collected as electrical information input, providing the raw data foundation for subsequent analysis. Secondly, based on a preset filtering and signal preprocessing mechanism, the collected electrical information is digitized, smoothed, and normalized to eliminate noise interference and obtain standardized signal data. Then, based on the standardized data, it is determined whether the VBUS signal exceeds a first signal threshold to verify the normality of the physical connection, i.e., a primary verification is performed. If the physical connection passes verification, a secondary verification is further performed by checking whether the signals of each channel are within a second signal threshold range to ensure the rationality of the electrical parameters. After passing the secondary verification, a timing signal sequence is extracted from the standardized signal and loaded into a preset Type-C protocol state machine model. Protocol compliance is determined by detecting whether the event timing on the CC pin conforms to the conditional transition rules defined by the state machine. If the protocol conforms to the preset rules, the handshake communication message is parsed and extracted; otherwise, a test state result containing fault information is generated. Finally, based on the handshake communication message or test status result, an indication command is output to control various combinations of colors or numbers of indicator lights, or communication commands, to visually display the Type-C interface protocol test status. Furthermore, in response to external feedback signals, a pre-trained adjustment model is used to dynamically optimize the first and second signal thresholds, enabling the system to have adaptive learning capabilities, thereby comprehensively improving test accuracy, automation, and compatibility with different Type-C devices.

[0026] Figure 2 A flowchart illustrating the filtering and signal preprocessing of electrical information provided by an embodiment of the present invention is shown.

[0027] According to embodiments of the present invention, such as Figure 2 As shown, the preset filtering and signal preprocessing mechanism, based on the electrical information, obtains standardized signal data, specifically including: S202 receives multiple analog electrical signals acquired in real time from the CC pin, VBUS pin, and D+ / D- pin of the Type-C interface; S204, synchronously sample and convert the multiple analog electrical signals to digital signals to obtain a multiple digital signal sequence; S206, Perform a preset moving average and digital filtering algorithm on the multi-channel digital signal sequence to obtain a smooth signal sequence; S208, Perform a preset dimension normalization process on the smoothed signal sequence to obtain a normalized signal sequence; S210, perform a preset baseline calibration on the normalized signal sequence to obtain the standardized signal data.

[0028] It should be noted that this embodiment provides a signal preprocessing flow. In this embodiment, firstly, multiple analog electrical signals from the CC, VBUS, and D+ / D- pins of the Type-C interface are simultaneously acquired to ensure data timing consistency. Simultaneously, a high-precision analog-to-digital converter converts the analog signals into digital signal sequences for subsequent processing. Secondly, these digital signal sequences are processed using moving average and digital filtering algorithms to suppress high-frequency noise and transient interference, resulting in smooth and stable signal waveforms. Then, the smoothed signals undergo dimension normalization, mapping each channel signal to a unified scale to eliminate data deviations caused by hardware gain differences. Finally, a baseline calibration operation is performed to compensate for DC component drift, outputting high-quality standardized signal data. This embodiment employs a series of preprocessing steps to improve the quality and consistency of signal data, providing a reliable data foundation for subsequent threshold comparison and protocol analysis, while also enhancing the system's anti-interference capability and test repeatability.

[0029] Figure 3 The diagram illustrates a primary and intermediate verification flowchart for standardized signal data provided by an embodiment of the present invention.

[0030] According to embodiments of the present invention, such as Figure 3 As shown, after obtaining the standardized signal data, it includes: S302, compare the VBUS signal data with a preset first signal threshold; S304, if the duration of the signal not exceeding the first signal threshold exceeds the preset first duration, it is determined to be a physical connection abnormality; S306, if the duration of the signal exceeding the first signal threshold exceeds the preset first duration, it is determined that the primary verification has been passed. S308, in response to passing the primary check, compares the channel signal data one by one with the preset second signal threshold range; S310, if the duration of any channel signal deviating from the corresponding threshold range exceeds the preset second duration, an amplitude abnormality event is generated and the deviation channel identifier is recorded. S312, if all channel signals are within the corresponding threshold range, then the intermediate verification is passed.

[0031] It should be noted that this embodiment provides a hierarchical threshold verification process. In this embodiment, after obtaining standardized signal data, the VBUS signal is first compared with a first signal threshold. If the VBUS signal remains below the first signal threshold for more than a preset duration, it is determined to be a physical connection anomaly and the process terminates. If the VBUS signal remains above the first signal threshold for more than a preset duration, it is determined to pass the primary verification. After the primary verification passes, the system enters the intermediate verification stage, comparing the signal data of each channel with a preset second signal threshold range one by one. If any channel signal deviates from its corresponding range for more than a set duration, the channel anomaly identifier is recorded and an event log is generated. The intermediate verification is only considered passed when all channels meet the requirements. The hierarchical, channel-specific verification mechanism adopted in this embodiment gradually filters out abnormal signals, which can quickly locate basic connection and electrical parameter problems, and avoid the influence of a single channel anomaly on the overall judgment, significantly improving the accuracy of fault diagnosis and system robustness.

[0032] According to an embodiment of the present invention, the step of determining whether a signal sequence conforms to a preset protocol specification based on a preset protocol state machine specifically includes: The channel signal data is loaded into a preset Type-C protocol state machine model; Based on the CC pin channel signal data, the first timing feature is extracted to identify the notification event; Perform state machine transitions based on the notification events; If the notification event performs a conditional transition according to the preset state machine conditions, it is determined to conform to the protocol specifications; If a timeout occurs and the expected event is not received, or an undefined transfer is triggered, it is determined to be a protocol timing anomaly.

[0033] It should be noted that this embodiment provides a protocol compliance judgment process. In this embodiment, channel signal data is loaded into a built-in Type-C protocol state machine model; wherein, the protocol state machine model defines multiple states and transition conditions, such as not connected, role negotiation, and normal communication. By analyzing the CC pin signal, the timing characteristics of notification events such as connection detection and current surge are extracted, and the state machine is driven to perform state transitions. If the event sequence completely meets the preset state transition conditions, the protocol specification is determined to be compliant; if a timeout or undefined state transition occurs, it is determined to be a protocol timing anomaly. This embodiment, by simulating the real protocol interaction process, can deeply diagnose faults at the timing logic level, solving the problem of traditional testing that only focuses on electrical parameters and ignores the integrity of protocol states, thus improving the depth and reliability of protocol testing.

[0034] According to an embodiment of the present invention, it further includes: In response to the determination of a protocol timing anomaly, the message extraction process is initiated; Bit clock recovery and decoding are performed on the differential signals of data lines D+ / D- to obtain a digital bit stream; Based on the protocol data frame structure, the frame start delimiter and packet identifier are identified from the bit stream to extract the payload data segment. Based on the payload data segment, the handshake communication message is reassembled. In response to the determination of a protocol timing anomaly, the test status generation process is initiated. Based on the error codes of the protocol state machine, structured test state results are generated.

[0035] It should be noted that the handshake communication message includes at least a Type-C device, a power capability message, or a power request message; the test status result includes at least a status conclusion, a fault level, a suspected fault point identifier, and a raw data timestamp. This embodiment provides a deep diagnostic and result generation process for a protocol. In this embodiment, when the system determines the protocol, it automatically initiates the message extraction process. Bit clock recovery and decoding operations are performed on the differential signals of the data lines D+ / D- to obtain the raw digital bitstream. Subsequently, according to the frame structure defined by the Type-C protocol, the frame start delimiter and packet identifier are identified from the bitstream to locate the payload data segment. The extracted data segment is reassembled into a complete handshake communication message, such as a power capability message or a power request message, for subsequent analysis. Simultaneously, the test status generation process is initiated in parallel, integrating the error codes generated by the protocol state machine, the physical connection status, and the amplitude status information of each channel to generate a structured test status result containing a status conclusion, a fault level, a suspected fault point identifier, and a timestamp. This embodiment realizes full-chain fault diagnosis capability from low-level signal decoding to high-level protocol parsing. It can identify anomalies and provide detailed diagnostic basis and location information, improving the depth of protocol layer testing and the accuracy of fault analysis.

[0036] According to an embodiment of the present invention, the step of inputting the standardized signal data and the instruction to a pre-trained adjustment model in response to the feedback signal to correct the ranges of the first signal threshold and the second signal threshold specifically includes: The current standardized signal data, instructions, and feedback signals are integrated into training samples; The training samples are input into a pre-trained neural network conditioning model to obtain the target threshold. Calculate the deviation between the target threshold and the range of the first signal threshold and the second signal threshold; If the deviation value exceeds a preset deviation threshold, the ranges of the first signal threshold and the second signal threshold are adjusted according to the deviation value.

[0037] It should be noted that the feedback signal is either a user-confirmed correct judgment or a threshold adjustment command issued by the host computer system; the neural network adjustment model is constructed based on the mapping relationship between signal features and correct thresholds in historical data. This embodiment provides an adaptive threshold optimization mechanism based on machine learning. In this embodiment, a user-confirmed correct judgment or an adjustment command issued by the host computer is received as a feedback signal. The standardized signal data of the current period, the output indication command, and the feedback signal are integrated into a training sample. This sample is input into a pre-trained neural network adjustment model; wherein, the adjustment model learns the mapping relationship between signal features and correct thresholds in historical data and outputs the optimal target threshold for the current environment. Then, the deviation between the target threshold and the existing first signal threshold and second signal threshold range is calculated. If the deviation exceeds a preset tolerance, the threshold parameters are automatically dynamically corrected. This embodiment adapts to changes in different devices, cables, and environments, gradually improving the accuracy of threshold settings and reducing false alarms and missed alarms; thereby achieving self-optimization and long-term accurate operation of the test system.

[0038] It is worth mentioning that, before extracting the handshake communication message, the process also includes: Monitor the VBUS voltage and the modulation signal of the CC pin, and extract the characteristic patterns of the modulation signal; Based on the aforementioned feature pattern, a preset protocol feature library is matched; If the match is a preset fast charging protocol, then the parameter set and protocol state machine model are dynamically loaded according to the fast charging protocol.

[0039] It should be noted that the protocol feature library includes, but is not limited to, USB Power Delivery, Quick Charge, and Programmable Power Supply protocols. This embodiment provides an automatic fast charging protocol identification and testing function. In this embodiment, before extracting the handshake message, the amplitude, frequency, and timing characteristics are extracted by actively monitoring the VBUS voltage and the modulation signal on the CC pin. Then, the characteristic patterns are matched with the built-in protocol feature library to identify whether mainstream fast charging protocols such as USB PD, QC, or PPS are supported. If the match is successful, the dedicated threshold parameter set and protocol state machine model of the corresponding fast charging protocol are dynamically loaded, and a dedicated handshake process monitoring and message parsing for that protocol are executed. The fast charging protocol identification mechanism of this embodiment enhances the compatibility and application scope of the testing system, enabling it to complete the compliance testing of the basic Type-C protocol and multiple fast charging protocols in one stop, meeting the complex testing needs of modern electronic devices' fast charging technology.

[0040] It is worth mentioning that it also includes: Standardized signal data, test status results, and threshold adjustment records are used as historical data samples. Based on a preset analysis cycle, time-series pattern mining and feature trend analysis are performed on the historical data samples to obtain health indicators. Calculate the deviation of the health index from the standard health baseline; If the deviation exceeds a preset deviation threshold, an early fault warning signal is generated; A maintenance signal is generated based on the early fault warning signal.

[0041] It should be noted that the health indicators include at least VBUS voltage fluctuation rate and CC pin resistance change slope. This embodiment provides a device health status assessment and predictive maintenance mechanism. In this embodiment, standardized signal data, test status results, and threshold adjustment records are continuously stored as historical data samples. Secondly, time-series pattern mining and feature trend analysis are periodically performed on the data samples to calculate health indicators such as VBUS voltage fluctuation rate and CC pin resistance change slope. Then, by comparing the health indicators with a standard health baseline established based on historical data, the deviation between the health indicators is calculated. If the deviation exceeds the warning threshold, an early fault warning signal is generated and a maintenance prompt is triggered. This embodiment extends the testing function from immediate diagnosis to long-term status monitoring and predictive maintenance, helping users to identify potential degradation risks in advance, optimize equipment maintenance strategies, and improve system reliability and service life.

[0042] It is worth mentioning that it also includes: When a physical connection between the current test board and the slave test board is detected, the collaborative test mode is entered. Generate a synchronous clock signal and broadcast it to each slave test board via the cascade bus; In response to receiving standardized signal data processed locally from the test board, global standardized signal data is obtained by fusing the data. Based on preset signal attenuation, timing deviation and protocol anomaly analysis, a comprehensive diagnostic report is generated, and the status of indicator lights on each test board is coordinated.

[0043] It should be noted that this embodiment provides a collaborative testing scheme for multiple cascaded devices. In this embodiment, when the main test board and the slave test boards are detected to be physically connected through the cascading interface, the collaborative testing mode is automatically entered. The main test board generates a high-precision synchronous clock signal and distributes it to each slave board through the cascading bus to ensure strict synchronization of data acquisition at all nodes. Each slave board preprocesses its local Type-C signal and uploads standardized data to the main board. The main board integrates all data to form a global signal view. Then, based on the global data, it performs signal attenuation analysis, timing deviation detection, and protocol anomaly location, generates a comprehensive diagnostic report, and coordinates the status of indicator lights on all boards to visually indicate the faulty section. This embodiment overcomes the limitations of single-point testing, realizes distributed measurement and precise global fault location for complex link systems, and is particularly suitable for testing needs in complex scenarios such as long cables and multi-interface expansion.

[0044] Figure 4 A block diagram of a Type-C interface protocol intelligent testing system according to the present invention is shown.

[0045] like Figure 4 As shown, the second aspect of the present invention discloses a Type-C interface protocol intelligent testing system 4, including a memory 41 and a processor 42. The memory includes a Type-C interface protocol intelligent testing method program, which, when executed by the processor, performs the following steps: Collect electrical information from the Type-C interface; Based on the preset filtering and signal preprocessing mechanism, standardized signal data is obtained according to the electrical information; Based on the standardized signal data, determine whether the VBUS signal data is greater than a preset first signal threshold; If so, determine whether the channel signal data is within the preset second signal threshold range; If so, then the signal sequence is extracted based on the standardized signal data; Based on a preset protocol state machine, the system determines whether the signal sequence conforms to the preset protocol specifications. If so, extract the handshake communication message; If not, then generate the test status result; Based on the handshake communication message or the test status result, output an indication command; In response to the feedback signal, the standardized signal data and the instruction are input into the pre-trained adjustment model to correct the range of the first signal threshold and the second signal threshold.

[0046] It should be noted that the electrical information refers to the voltage or current values ​​of the Type-C interface pins. In this embodiment, the voltage or current signals of the Type-C interface pins are first collected as electrical information input, providing the raw data foundation for subsequent analysis. Secondly, based on a preset filtering and signal preprocessing mechanism, the collected electrical information is digitized, smoothed, and normalized to eliminate noise interference and obtain standardized signal data. Then, based on the standardized data, it is determined whether the VBUS signal exceeds a first signal threshold to verify the normality of the physical connection, i.e., a primary verification is performed. If the physical connection passes verification, a secondary verification is further performed by checking whether the signals of each channel are within a second signal threshold range to ensure the rationality of the electrical parameters. After passing the secondary verification, a timing signal sequence is extracted from the standardized signal and loaded into a preset Type-C protocol state machine model. Protocol compliance is determined by detecting whether the event timing on the CC pin conforms to the conditional transition rules defined by the state machine. If the protocol conforms to the preset rules, the handshake communication message is parsed and extracted; otherwise, a test state result containing fault information is generated. Finally, based on the handshake communication message or test status result, an indication command is output to control various combinations of colors or numbers of indicator lights, or communication commands, to visually display the Type-C interface protocol test status. Furthermore, in response to external feedback signals, a pre-trained adjustment model is used to dynamically optimize the first and second signal thresholds, enabling the system to have adaptive learning capabilities, thereby comprehensively improving test accuracy, automation, and compatibility with different Type-C devices.

[0047] According to an embodiment of the present invention, the step of obtaining standardized signal data based on the electrical information using a preset filtering and signal preprocessing mechanism specifically includes: It receives multiple analog electrical signals acquired in real time from the CC pin, VBUS pin, and D+ / D- pin of the Type-C interface; The multiple analog electrical signals are synchronously sampled and converted from analog to digital to obtain a multiple digital signal sequence; A preset moving average and digital filtering algorithm is applied to the multi-channel digital signal sequence to obtain a smooth signal sequence; The smoothed signal sequence is subjected to a preset dimension normalization process to obtain a normalized signal sequence; The normalized signal sequence is subjected to a preset baseline calibration to obtain the standardized signal data.

[0048] It should be noted that this embodiment provides a signal preprocessing flow. In this embodiment, firstly, multiple analog electrical signals from the CC, VBUS, and D+ / D- pins of the Type-C interface are simultaneously acquired to ensure data timing consistency. Simultaneously, a high-precision analog-to-digital converter converts the analog signals into digital signal sequences for subsequent processing. Secondly, these digital signal sequences are processed using moving average and digital filtering algorithms to suppress high-frequency noise and transient interference, resulting in smooth and stable signal waveforms. Then, the smoothed signals undergo dimension normalization, mapping each channel signal to a unified scale to eliminate data deviations caused by hardware gain differences. Finally, a baseline calibration operation is performed to compensate for DC component drift, outputting high-quality standardized signal data. This embodiment employs a series of preprocessing steps to improve the quality and consistency of signal data, providing a reliable data foundation for subsequent threshold comparison and protocol analysis, while also enhancing the system's anti-interference capability and test repeatability.

[0049] According to an embodiment of the present invention, after obtaining standardized signal data, the process includes: The VBUS signal data is compared with a preset first signal threshold. If the duration of the signal not exceeding the first signal threshold exceeds the preset first duration, it is determined to be a physical connection abnormality. If the duration of the signal exceeding the first signal threshold exceeds the preset first duration, it is determined that the primary verification has been passed. In response to passing the primary verification, the channel signal data is compared one by one with the preset second signal threshold range; If the duration of any channel signal deviating from the corresponding threshold range exceeds the preset second duration, an amplitude anomaly event is generated and the deviation channel identifier is recorded. If all channel signals are within the corresponding threshold range, the intermediate verification is considered passed.

[0050] It should be noted that this embodiment provides a hierarchical threshold verification process. In this embodiment, after obtaining standardized signal data, the VBUS signal is first compared with a first signal threshold. If the VBUS signal remains below the first signal threshold for more than a preset duration, it is determined to be a physical connection anomaly and the process terminates. If the VBUS signal remains above the first signal threshold for more than a preset duration, it is determined to pass the primary verification. After the primary verification passes, the system enters the intermediate verification stage, comparing the signal data of each channel with a preset second signal threshold range one by one. If any channel signal deviates from its corresponding range for more than a set duration, the channel anomaly identifier is recorded and an event log is generated. The intermediate verification is only considered passed when all channels meet the requirements. The hierarchical, channel-specific verification mechanism adopted in this embodiment gradually filters out abnormal signals, which can quickly locate basic connection and electrical parameter problems, and avoid the influence of a single channel anomaly on the overall judgment, significantly improving the accuracy of fault diagnosis and system robustness.

[0051] According to an embodiment of the present invention, the step of determining whether a signal sequence conforms to a preset protocol specification based on a preset protocol state machine specifically includes: The channel signal data is loaded into a preset Type-C protocol state machine model; Based on the CC pin channel signal data, the first timing feature is extracted to identify the notification event; Perform state machine transitions based on the notification events; If the notification event performs a conditional transition according to the preset state machine conditions, it is determined to conform to the protocol specifications; If a timeout occurs and the expected event is not received, or an undefined transfer is triggered, it is determined to be a protocol timing anomaly.

[0052] It should be noted that this embodiment provides a protocol compliance judgment process. In this embodiment, channel signal data is loaded into a built-in Type-C protocol state machine model; wherein, the protocol state machine model defines multiple states and transition conditions, such as not connected, role negotiation, and normal communication. By analyzing the CC pin signal, the timing characteristics of notification events such as connection detection and current surge are extracted, and the state machine is driven to perform state transitions. If the event sequence completely meets the preset state transition conditions, the protocol specification is determined to be compliant; if a timeout or undefined state transition occurs, it is determined to be a protocol timing anomaly. This embodiment, by simulating the real protocol interaction process, can deeply diagnose faults at the timing logic level, solving the problem of traditional testing that only focuses on electrical parameters and ignores the integrity of protocol states, thus improving the depth and reliability of protocol testing.

[0053] According to an embodiment of the present invention, it further includes: In response to the determination of a protocol timing anomaly, the message extraction process is initiated; Bit clock recovery and decoding are performed on the differential signals of data lines D+ / D- to obtain a digital bit stream; Based on the protocol data frame structure, the frame start delimiter and packet identifier are identified from the bit stream to extract the payload data segment. Based on the payload data segment, the handshake communication message is reassembled. In response to the determination of a protocol timing anomaly, the test status generation process is initiated. Based on the error codes of the protocol state machine, structured test state results are generated.

[0054] It should be noted that the handshake communication message includes at least a Type-C device, a power capability message, or a power request message; the test status result includes at least a status conclusion, a fault level, a suspected fault point identifier, and a raw data timestamp. This embodiment provides a deep diagnostic and result generation process for a protocol. In this embodiment, when the system determines the protocol, it automatically initiates the message extraction process. Bit clock recovery and decoding operations are performed on the differential signals of the data lines D+ / D- to obtain the raw digital bitstream. Subsequently, according to the frame structure defined by the Type-C protocol, the frame start delimiter and packet identifier are identified from the bitstream to locate the payload data segment. The extracted data segment is reassembled into a complete handshake communication message, such as a power capability message or a power request message, for subsequent analysis. Simultaneously, the test status generation process is initiated in parallel, integrating the error codes generated by the protocol state machine, the physical connection status, and the amplitude status information of each channel to generate a structured test status result containing a status conclusion, a fault level, a suspected fault point identifier, and a timestamp. This embodiment realizes full-chain fault diagnosis capability from low-level signal decoding to high-level protocol parsing. It can identify anomalies and provide detailed diagnostic basis and location information, improving the depth of protocol layer testing and the accuracy of fault analysis.

[0055] According to an embodiment of the present invention, the step of inputting the standardized signal data and the instruction to a pre-trained adjustment model in response to the feedback signal to correct the ranges of the first signal threshold and the second signal threshold specifically includes: The current standardized signal data, instructions, and feedback signals are integrated into training samples; The training samples are input into a pre-trained neural network conditioning model to obtain the target threshold. Calculate the deviation between the target threshold and the range of the first signal threshold and the second signal threshold; If the deviation value exceeds a preset deviation threshold, the ranges of the first signal threshold and the second signal threshold are adjusted according to the deviation value.

[0056] It should be noted that the feedback signal is either a user-confirmed correct judgment or a threshold adjustment command issued by the host computer system; the neural network adjustment model is constructed based on the mapping relationship between signal features and correct thresholds in historical data. This embodiment provides an adaptive threshold optimization mechanism based on machine learning. In this embodiment, a user-confirmed correct judgment or an adjustment command issued by the host computer is received as a feedback signal. The standardized signal data of the current period, the output indication command, and the feedback signal are integrated into a training sample. This sample is input into a pre-trained neural network adjustment model; wherein, the adjustment model learns the mapping relationship between signal features and correct thresholds in historical data and outputs the optimal target threshold for the current environment. Then, the deviation between the target threshold and the existing first signal threshold and second signal threshold range is calculated. If the deviation exceeds a preset tolerance, the threshold parameters are automatically dynamically corrected. This embodiment adapts to changes in different devices, cables, and environments, gradually improving the accuracy of threshold settings and reducing false alarms and missed alarms; thereby achieving self-optimization and long-term accurate operation of the test system.

[0057] It is worth mentioning that, before extracting the handshake communication message, the process also includes: Monitor the VBUS voltage and the modulation signal of the CC pin, and extract the characteristic patterns of the modulation signal; Based on the aforementioned feature pattern, a preset protocol feature library is matched; If the match is a preset fast charging protocol, then the parameter set and protocol state machine model are dynamically loaded according to the fast charging protocol.

[0058] It should be noted that the protocol feature library includes, but is not limited to, USB Power Delivery, Quick Charge, and Programmable Power Supply protocols. This embodiment provides an automatic fast charging protocol identification and testing function. In this embodiment, before extracting the handshake message, the amplitude, frequency, and timing characteristics are extracted by actively monitoring the VBUS voltage and the modulation signal on the CC pin. Then, the characteristic patterns are matched with the built-in protocol feature library to identify whether mainstream fast charging protocols such as USB PD, QC, or PPS are supported. If the match is successful, the dedicated threshold parameter set and protocol state machine model of the corresponding fast charging protocol are dynamically loaded, and a dedicated handshake process monitoring and message parsing for that protocol are executed. The fast charging protocol identification mechanism of this embodiment enhances the compatibility and application scope of the testing system, enabling it to complete the compliance testing of the basic Type-C protocol and multiple fast charging protocols in one stop, meeting the complex testing needs of modern electronic devices' fast charging technology.

[0059] It is worth mentioning that it also includes: Standardized signal data, test status results, and threshold adjustment records are used as historical data samples. Based on a preset analysis cycle, time-series pattern mining and feature trend analysis are performed on the historical data samples to obtain health indicators. Calculate the deviation of the health index from the standard health baseline; If the deviation exceeds a preset deviation threshold, an early fault warning signal is generated; A maintenance signal is generated based on the early fault warning signal.

[0060] It should be noted that the health indicators include at least VBUS voltage fluctuation rate and CC pin resistance change slope. This embodiment provides a device health status assessment and predictive maintenance mechanism. In this embodiment, standardized signal data, test status results, and threshold adjustment records are continuously stored as historical data samples. Secondly, time-series pattern mining and feature trend analysis are periodically performed on the data samples to calculate health indicators such as VBUS voltage fluctuation rate and CC pin resistance change slope. Then, by comparing the health indicators with a standard health baseline established based on historical data, the deviation between the health indicators is calculated. If the deviation exceeds the warning threshold, an early fault warning signal is generated and a maintenance prompt is triggered. This embodiment extends the testing function from immediate diagnosis to long-term status monitoring and predictive maintenance, helping users to identify potential degradation risks in advance, optimize equipment maintenance strategies, and improve system reliability and service life.

[0061] It is worth mentioning that it also includes: When a physical connection between the current test board and the slave test board is detected, the collaborative test mode is entered. Generate a synchronous clock signal and broadcast it to each slave test board via the cascade bus; In response to receiving standardized signal data processed locally from the test board, global standardized signal data is obtained by fusing the data. Based on preset signal attenuation, timing deviation and protocol anomaly analysis, a comprehensive diagnostic report is generated, and the status of indicator lights on each test board is coordinated.

[0062] It should be noted that this embodiment provides a collaborative testing scheme for multiple cascaded devices. In this embodiment, when the main test board and the slave test boards are detected to be physically connected through the cascading interface, the collaborative testing mode is automatically entered. The main test board generates a high-precision synchronous clock signal and distributes it to each slave board through the cascading bus to ensure strict synchronization of data acquisition at all nodes. Each slave board preprocesses its local Type-C signal and uploads standardized data to the main board. The main board integrates all data to form a global signal view. Then, based on the global data, it performs signal attenuation analysis, timing deviation detection, and protocol anomaly location, generates a comprehensive diagnostic report, and coordinates the status of indicator lights on all boards to visually indicate the faulty section. This embodiment overcomes the limitations of single-point testing, realizes distributed measurement and precise global fault location for complex link systems, and is particularly suitable for testing needs in complex scenarios such as long cables and multi-interface expansion.

[0063] A third aspect of the present invention provides a computer-readable storage medium comprising a Type-C interface protocol intelligent testing method program, wherein when the Type-C interface protocol intelligent testing method program is executed by a processor, it implements the steps of the Type-C interface protocol intelligent testing method as described in any of the preceding claims.

[0064] In summary, this invention provides an intelligent testing method, system, and storage medium for Type-C interface protocols. First, it collects electrical information from the Type-C interface and obtains standardized signal data through filtering and preprocessing. Then, it sequentially performs VBUS signal threshold judgment and channel signal threshold range verification to complete physical layer and electrical parameter verification. After passing the basic verification, it extracts the signal sequence and inputs it into a preset protocol state machine for protocol compliance judgment. Based on the judgment result, it parses handshake communication messages or generates structured test status results. Finally, it outputs indication commands and can respond to feedback signals, dynamically optimizing signal threshold parameters through a pre-trained adjustment model. This achieves fully automated testing from electrical characteristics to protocol logic, improving testing efficiency and accuracy. Based on adaptive learning capabilities, it adapts to different device and cable characteristics, effectively addressing technical problems in complex protocol scenarios.

[0065] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0066] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A smart testing method for Type-C interface protocol, characterized in that, The method includes: Collect electrical information from the Type-C interface; Based on the preset filtering and signal preprocessing mechanism, standardized signal data is obtained according to the electrical information; Based on the standardized signal data, determine whether the VBUS signal data is greater than a preset first signal threshold; If so, determine whether the channel signal data is within the preset second signal threshold range; If so, then the signal sequence is extracted based on the standardized signal data; Based on a preset protocol state machine, the system determines whether the signal sequence conforms to the preset protocol specifications. If so, extract the handshake communication message; If not, then generate the test status result; Based on the handshake communication message or the test status result, output an indication command; In response to the feedback signal, the standardized signal data and the instruction are input into the pre-trained adjustment model to correct the range of the first signal threshold and the second signal threshold. Specifically, the step of determining whether a signal sequence conforms to a preset protocol specification based on a preset protocol state machine includes: The channel signal data is loaded into a preset Type-C protocol state machine model; Based on the CC pin channel signal data, the first timing feature is extracted to identify the notification event; Perform state machine transitions based on the notification events; If the notification event performs a conditional transition according to the preset state machine conditions, it is determined to conform to the protocol specifications; If a timeout occurs and the expected event is not received, or an undefined transfer is triggered, it is determined to be a protocol timing anomaly.

2. The intelligent testing method for a Type-C interface protocol according to claim 1, characterized in that, The preset filtering and signal preprocessing mechanism, based on the electrical information, obtains standardized signal data, specifically including: It receives multiple analog electrical signals acquired in real time from the CC pin, VBUS pin, and D+ / D- pin of the Type-C interface; The multiple analog electrical signals are synchronously sampled and converted from analog to digital to obtain a multiple digital signal sequence; A preset moving average and digital filtering algorithm is applied to the multi-channel digital signal sequence to obtain a smooth signal sequence; The smoothed signal sequence is subjected to a preset dimension normalization process to obtain a normalized signal sequence; The normalized signal sequence is subjected to a preset baseline calibration to obtain the standardized signal data.

3. The intelligent testing method for a Type-C interface protocol according to claim 2, characterized in that, After obtaining the standardized signal data, the following is included: The VBUS signal data is compared with a preset first signal threshold. If the duration of the signal not exceeding the first signal threshold exceeds the preset first duration, it is determined to be a physical connection abnormality. If the duration of the signal exceeding the first signal threshold exceeds the preset first duration, it is determined that the primary verification has been passed. In response to passing the primary verification, the channel signal data is compared one by one with the preset second signal threshold range; If the duration of any channel signal deviating from the corresponding threshold range exceeds the preset second duration, an amplitude anomaly event is generated and the deviation channel identifier is recorded. If all channel signals are within the corresponding threshold range, the intermediate verification is considered passed.

4. The intelligent testing method for a Type-C interface protocol according to claim 1, characterized in that, Also includes: In response to the determination of a protocol timing anomaly, the message extraction process is initiated; Bit clock recovery and decoding are performed on the differential signals of data lines D+ / D- to obtain a digital bit stream; Based on the protocol data frame structure, the frame start delimiter and packet identifier are identified from the bit stream to extract the payload data segment. Based on the payload data segment, the handshake communication message is reassembled. In response to the determination of a protocol timing anomaly, the test status generation process is initiated. Based on the error codes of the protocol state machine, structured test state results are generated.

5. The intelligent testing method for a Type-C interface protocol according to claim 1, characterized in that, In response to the feedback signal, the standardized signal data and the instruction are input into a pre-trained adjustment model to correct the ranges of the first and second signal thresholds, specifically including: The current standardized signal data, instructions, and feedback signals are integrated into training samples; The training samples are input into a pre-trained neural network conditioning model to obtain the target threshold. Calculate the deviation between the target threshold and the range of the first signal threshold and the second signal threshold; If the deviation value exceeds a preset deviation threshold, the ranges of the first signal threshold and the second signal threshold are adjusted according to the deviation value.

6. A Type-C interface protocol intelligent testing system, characterized in that, The system includes a memory and a processor. The memory includes a Type-C interface protocol intelligent testing method program. When the Type-C interface protocol intelligent testing method program is executed by the processor, it performs the following steps: Collect electrical information from the Type-C interface; Based on the preset filtering and signal preprocessing mechanism, standardized signal data is obtained according to the electrical information; Based on the standardized signal data, determine whether the VBUS signal data is greater than a preset first signal threshold; If so, determine whether the channel signal data is within the preset second signal threshold range; If so, then the signal sequence is extracted based on the standardized signal data; Based on a preset protocol state machine, the system determines whether the signal sequence conforms to the preset protocol specifications. If so, extract the handshake communication message; If not, then generate the test status result; Based on the handshake communication message or the test status result, output an indication command; In response to the feedback signal, the standardized signal data and the instruction are input into the pre-trained adjustment model to correct the range of the first signal threshold and the second signal threshold. Specifically, the step of determining whether a signal sequence conforms to a preset protocol specification based on a preset protocol state machine includes: The channel signal data is loaded into a preset Type-C protocol state machine model; Based on the CC pin channel signal data, the first timing feature is extracted to identify the notification event; Perform state machine transitions based on the notification events; If the notification event performs a conditional transition according to the preset state machine conditions, it is determined to conform to the protocol specifications; If a timeout occurs and the expected event is not received, or an undefined transfer is triggered, it is determined to be a protocol timing anomaly.

7. The intelligent testing system for Type-C interface protocol according to claim 6, characterized in that, The preset filtering and signal preprocessing mechanism, based on the electrical information, obtains standardized signal data, specifically including: It receives multiple analog electrical signals acquired in real time from the CC pin, VBUS pin, and D+ / D- pin of the Type-C interface; The multiple analog electrical signals are synchronously sampled and converted from analog to digital to obtain a multiple digital signal sequence; A preset moving average and digital filtering algorithm is applied to the multi-channel digital signal sequence to obtain a smooth signal sequence; The smoothed signal sequence is subjected to a preset dimension normalization process to obtain a normalized signal sequence; The normalized signal sequence is subjected to a preset baseline calibration to obtain the standardized signal data.

8. The intelligent testing system for the Type-C interface protocol according to claim 7, characterized in that, After obtaining the standardized signal data, the following is included: The VBUS signal data is compared with a preset first signal threshold. If the duration of the signal not exceeding the first signal threshold exceeds the preset first duration, it is determined to be a physical connection abnormality. If the duration of the signal exceeding the first signal threshold exceeds the preset first duration, it is determined that the primary verification has been passed. In response to passing the primary verification, the channel signal data is compared one by one with the preset second signal threshold range; If the duration of any channel signal deviating from the corresponding threshold range exceeds the preset second duration, an amplitude anomaly event is generated and the deviation channel identifier is recorded. If all channel signals are within the corresponding threshold range, the intermediate verification is considered passed.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer-readable storage medium includes a Type-C interface protocol intelligent testing method program, which, when executed by a processor, implements the steps of the Type-C interface protocol intelligent testing method as described in any one of claims 1 to 5.

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