Data processing apparatus, method and electronic device

Abstract

The present disclosure provides a data processing apparatus, method and electronic device, the apparatus comprising: a bus interconnection module and at least one multiplexing module, each multiplexing module comprising a first multiplexer, a cache module, a second multiplexer and a memory module, for any multiplexing module: the bus interconnection module is connected to the first multiplexer of the multiplexing module through N bus channels, N being an integer greater than 1; the first multiplexer is configured to map the N bus channels to N cache channels and one backup cache channel of the cache module; the second multiplexer is configured to map the N cache channels and the one backup cache channel of the cache module to N memory channels of the memory module, to form N data paths. According to embodiments of the present disclosure, the reliability of the memory can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data processing apparatus, method, and electronic device. Background Technology

[0002] In modern computer system design, a flexible bus architecture and an efficient memory architecture are typically required to match the parallel processing capabilities of the processing device. In memory architecture design, memory with multiple channels can be configured, such as High Bandwidth Memory (HBM), to enable parallel data read and write operations. Furthermore, caches can be designed in conjunction with memory, with each memory channel corresponding to a cache channel, thereby matching data bandwidth and achieving high-bandwidth, low-latency data read and write operations, thus improving system performance.

[0003] However, during chip manufacturing and use, channel damage may occur. If a channel is damaged at a certain location, the channel cannot be used, which means the entire chip can only be downgraded or discarded, resulting in significant losses. Summary of the Invention

[0004] This disclosure provides a data processing apparatus, method, and electronic device.

[0005] In a first aspect, this disclosure provides a data processing apparatus, comprising: a bus interconnect module and at least one multiplexing module. Each multiplexing module includes a first multiplexer, a cache module, a second multiplexer, and a memory module. For any multiplexing module: the bus interconnect module is connected to the first multiplexer of the multiplexing module through N bus channels, where N is an integer greater than 1; the first multiplexer is used to map the N bus channels to N cache channels and 1 backup cache channel of the cache module; the second multiplexer is used to map the N cache channels and 1 backup cache channel of the cache module to N memory channels of the memory module, thereby forming N data paths.

[0006] Secondly, this disclosure provides a data processing method applied to a data processing apparatus, the apparatus including a bus interconnect module and at least one multiplexing module. Each multiplexing module includes a first multiplexer, a cache module, a second multiplexer, and a memory module. For any multiplexing module: the bus interconnect module is connected to the first multiplexer of the multiplexing module through N bus channels, where N is an integer greater than 1; the first multiplexer is used to map the N bus channels to N cache channels and 1 backup cache channel of the cache module; the second multiplexer is used to map the N cache channels and 1 backup cache channel of the cache module to N memory channels of the memory module, so as to form N data paths.

[0007] The method includes: when there are no damaged paths in the N data paths, controlling the first multiplexer and the second multiplexer to select N buffer channels to form N data paths; when there are damaged paths in the N data paths, controlling the first multiplexer and the second multiplexer to select the buffer channels of the undamaged paths and the backup buffer channels of the N data paths to form N data paths.

[0008] Thirdly, this disclosure provides an electronic device that includes the aforementioned data processing apparatus.

[0009] The embodiments provided in this disclosure can add a backup cache channel to the cache module of a data processing device, set a multiplexer to map N bus channels to N cache channels and backup cache channels, and map the N cache channels and backup cache channels to N memory channels to form N data paths. This allows the cache channels and backup cache channels of undamaged paths to be selected when a data path is damaged, thereby ensuring that the number of data paths remains unchanged, ensuring the normal functioning of the memory system, and thus improving memory utilization and reliability.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed exemplary embodiments described with reference to the accompanying drawings.

[0012] Figure 1 This is a schematic diagram of the memory architecture of a data processing device in the context of related technologies.

[0013] Figure 2 This is a schematic diagram of a data processing apparatus provided in an embodiment of the present disclosure.

[0014] Figure 3 This is a schematic diagram of the structure of a multiplexer for a data processing apparatus provided in an embodiment of the present disclosure.

[0015] Figure 4 This is a schematic diagram of the structure of a multiplexer for a data processing apparatus provided in an embodiment of the present disclosure. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0017] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0018] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0020] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0021] As mentioned earlier, in the memory architecture design of data processing devices, such as graphics processing units (GPUs) and central processing units (CPUs), in order to improve the parallel processing efficiency of the data processing device, memory with multiple channels can be set up, such as high-bandwidth memory (HBM), to enable parallel data reading and writing; and cache can be designed in conjunction with memory, with each memory channel corresponding to a cache channel, thereby matching the data bandwidth, realizing high-bandwidth, low-latency data reading and writing, and improving system performance.

[0022] Figure 1 This is a schematic diagram of the memory architecture of a data processing device in related technologies. For example... Figure 1 As shown, the data processing device may include multiple processing modules, a bus interconnect module, a cache module, and M memory modules 1 to M (M is an integer greater than or equal to 1). The storage space of each memory module may be 16G, 32G, 48G, 64G, etc. The processing modules may include the processing core of a GPU, such as an MPC (MUSA Processor Cluster), and may also include other modules (otherhosts), such as a data management module and a logic scheduling module, etc., which are not limited in this disclosure.

[0023] like Figure 1 As shown, each memory module has N memory channels (N is an integer greater than 1), and each memory channel corresponds to a cache channel of the cache module; each memory channel corresponds to a storage unit with an independent channel, such as DRAM (Dynamic Random Access Memory). In this way, the bus interconnect module forms multiple data paths through cache channels and memory channels to achieve parallel data read and write.

[0024] However, implementing memory design using HBM in GPUs is extremely costly. During chip manufacturing and use, channel damage can occur. If a data path fails at a point, the corresponding memory channel becomes unusable, forcing the entire chip to be downgraded or scrapped, resulting in significant losses. Bus channels in the bus interconnect module typically do not fail; however, damage in the data path is more likely to occur in the cache channel. Specific damage could include an open circuit between the bus interconnect module's bus channel and the cache channel, damage to the cache channel itself, or an open circuit between the cache channel and the corresponding memory channel.

[0025] According to embodiments of this disclosure, a data processing apparatus is provided that can add a backup cache channel to the cache module of the apparatus. A multiplexer is configured to map N bus channels to N cache channels and the backup cache channel, and to map the N cache channels and the backup cache channel to N memory channels to form N data paths. This allows the cache channel and backup cache channel of the undamaged path to be selected when a data path is damaged, thereby ensuring that the number of data paths remains unchanged, ensuring the normal functioning of the memory system, thereby improving memory utilization and reliability, and reducing the proportion of chips used downgraded or discarded.

[0026] The data processing apparatus according to the embodiments of this disclosure can be located in an electronic device such as a terminal device or a server. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc.

[0027] In some possible implementations, the data processing apparatus according to embodiments of this disclosure can be a graphics processing unit (GPU) or a central processing unit (CPU). The GPU can be a general-purpose graphics processing unit (GPGPU), a full-featured GPU, etc. This disclosure does not limit the specific type of data processing apparatus.

[0028] In some possible implementations, the data processing apparatus according to embodiments of this disclosure includes: a bus interconnect module and at least one multiplexing module. Each multiplexing module includes a first multiplexer, a cache module, a second multiplexer, and a memory module. For any multiplexing module: the bus interconnect module is connected to the first multiplexer of the multiplexing module through N bus channels, where N is an integer greater than 1; the first multiplexer is used to map the N bus channels to N cache channels and 1 backup cache channel of the cache module; the second multiplexer is used to map the N cache channels and 1 backup cache channel of the cache module to N memory channels of the memory module, so as to form N data paths.

[0029] Figure 2 This is a schematic diagram of a data processing apparatus provided in an embodiment of this disclosure. Figure 2 As shown, the data processing device includes a bus interconnect module 21 and at least one multiplexer module 22. Each multiplexer module includes a cache module 221, a memory module 222, a first multiplexer 223, a second multiplexer 224, and a control module (not shown). There can be M multiplexer modules 22, where M is an integer greater than or equal to 1.

[0030] In some possible implementations, the memory module includes high-bandwidth memory (HBM), and each memory channel of the memory module corresponds to a storage unit of the memory module. That is, each memory module 23 corresponds to one HBM particle or HBM chip, which has N memory channels, and each memory channel corresponds to a storage unit with an independent channel, such as DRAM, to achieve parallel read and write of N channels. The value of N can be, for example, 8 / 16 / 32. This disclosure does not limit the specific type of memory module or the specific value of N.

[0031] In some possible implementations, for each memory module, the bus interconnect module has N bus channels, and the cache module has N cache channels and one backup cache channel (cache_bak). A first multiplexer is added between the bus interconnect module and the cache module, and a second multiplexer is added between the cache module and the memory module. Thus, the bus interconnect module is connected to the cache module via the first multiplexer, and the cache module is connected to the memory module via the second multiplexer.

[0032] The bus interconnect module is connected to the first multiplexer through N bus channels. The first multiplexer maps the N bus channels to the N cache channels and 1 backup cache channel of the cache module, with one of the channels used by the backup cache channel to replace a potentially damaged cache channel. The second multiplexer maps the N cache channels and 1 backup cache channel of the cache module to the N memory channels of the memory module, and selects N functional channels from the N+1 channels for the memory module, thereby forming N data paths.

[0033] In some possible implementations, the device further includes a control module. Under normal circumstances, the control module can control the first and second multiplexers to select N buffer channels respectively via control signals. Each data path includes a corresponding bus channel, buffer channel, and memory channel for data transmission. The control module can be implemented in hardware or software, for example, by configurable logic unit registers, NAND gates, inverters, etc., in the data processing device. It should be understood that those skilled in the art can configure the specific implementation of the control module according to actual conditions, and this disclosure does not impose any limitations on this.

[0034] In some possible implementations, the value (1 or 0) of the corresponding control signal can be set by the application program or driver corresponding to the data processing device, such as the 8-bit value 00000111, and loaded into the memory, cache or register of the data processing device; the control module can read the corresponding value, generate the control signal, for example, the control signal generated when the value is 0 is low level, and the control signal generated when the value is 1 is high level, and input the control signal to the first multiplexer and the second multiplexer, thereby realizing the selection control of the first multiplexer and the second multiplexer.

[0035] In some possible implementations, such as Figure 2 As shown, the bus interconnect module is also connected to multiple processing modules of the data processing device. The processing modules send data access requests to the memory module through N data paths and receive response data from the memory module.

[0036] In other words, during the execution of a processing task by the processing module, if data for that task is needed, a data access request is generated and sent to the cache channel through the corresponding bus channel in the bus interconnect module. If the cache is hit, the response data is returned directly. If the cache is not hit, the data is sent to the memory channel. The response data returned by the memory channel is sent to the bus channel of the bus interconnect module via the cache channel and then returned to the processing module. The response data is also cached in the cache space of the cache channel for future access, thus improving the response speed.

[0037] In this way, parallel reading and writing of N data paths can be achieved, improving processing efficiency.

[0038] In some possible implementations, the control module is used to: control the first multiplexer and the second multiplexer to select the cache channel and backup cache channel of the undamaged path among the N data paths when there is a damaged path among the N data paths.

[0039] In other words, if there is a damaged path among the N data paths, the application or driver can set a new value for the corresponding control signal according to the location of the damaged path and load it into the data processing device. The control module reads the new value, generates a control signal to control the selection state of the first multiplexer and the second multiplexer, selects the cache channel and backup cache channel of the undamaged path among the N data paths, thereby switching the cache channel through which the data path passes, keeping the number of data paths unchanged, thereby improving memory utilization and reliability.

[0040] The data processing apparatus according to embodiments of the present disclosure will now be described in detail.

[0041] According to the data processing apparatus of this disclosure, the implementation of cache channel backup focuses on the physical and functional implementation of the multiplexer. For a single cache channel, the bus width is relatively large. For example, taking a 256-bit data width AXI bus (Advanced eXtensible Interface, the highest-performance bus in the AMBA protocol, designed for high-bandwidth, low-latency data transmission) and a 32-bit data width APB bus (Advanced Peripheral Bus, a low-power, low-complexity control bus in the AMBA protocol, designed for low-frequency, small-data-volume interactions such as configuration / status queries) as examples, the bus width of each cache channel may be 900-1000 bits, or even higher, occupying a large chip area. Therefore, when designing the multiplexer, the physical routing of the chip implementation needs to be considered to avoid timing, area, and congestion problems caused by excessive wiring.

[0042] like Figure 2As shown, on the N memory channels of a memory module, the multiplexers that implement N data paths include a first multiplexer at the cache module entry point, called cache_in_mux; and a second multiplexer at the cache module exit point, called cache_out_mux.

[0043] As mentioned earlier, the interaction between the processing module and the memory module includes data access requests and returned response data. The data bus from the processing module to the memory module can be called the request data bus, and the corresponding data path can be called the request data path. The data bus from the memory module to the processing module can be called the response data bus, and the corresponding data path can be called the response data path.

[0044] In some possible implementations, the first multiplexer includes a request input selector and a response output selector, and the second multiplexer includes a request output selector and a response input selector.

[0045] The request input selector is used to send data access requests from N bus channels to N cache channels and backup cache channels; the request output selector is used to send data access requests from N cache channels and backup cache channels to N memory channels.

[0046] The response input selector is used to send response data from N memory channels to N cache channels and backup cache channels; the response output selector is used to send response data from N cache channels and backup cache channels to N bus channels.

[0047] Figure 3 This is a schematic diagram of the structure of a multiplexer in a data processing apparatus provided in an embodiment of this disclosure. Figure 3 As shown, the multiplexer can be further divided into four types according to the direction of the data path. Among them, in the request data path ( Figure 3 On the downward arrow (in the middle), the first multiplexer includes a request input selector (req_cache_in_mux), and the second multiplexer includes a request output selector (req_cache_out_mux); in the response data path ( Figure 3 The second multiplexer (as indicated by the upward arrow) includes a response input selector (rsp_cache_in_mux), and the first multiplexer includes a response output selector (rsp_cache_out_mux).

[0048] Wherein, both the request input selector (req_cache_in_mux) and the response input selector (rsp_cache_in_mux) are configured to implement mapping from N channels to N+1 channels, and have similar circuit structures; both the request output selector (req_cache_out_mux) and the response output selector (rsp_cache_out_mux) are configured to implement mapping from N+1 channels to N channels, and also have similar circuit structures.

[0049] It should be noted that in actual design of the multiplexer, it is necessary to consider the physical routing for corresponding chip implementation, so as to avoid problems such as timing, area and congestion caused by a large amount of wiring. Those skilled in the art can arrange each multiplexer according to actual conditions, which is not limited in the present disclosure.

[0050] The structures of the request input selector and the request output selector are described below.

[0051] In some possible implementation manners, the request input selector comprises N+1 first sub-selectors, the request output selector comprises N second sub-selectors, and both the first sub-selectors and the second sub-selectors are 2-to-1 selectors.

[0052] Wherein, a first input terminal of an n-th first sub-selector is connected to an (n-1)-th bus channel, a second input terminal thereof is connected to an n-th bus channel, and an output terminal thereof is connected to an n-th cache channel, where 1<n≤N and n is an integer; a second input terminal of a 1st first sub-selector is connected to a 1st bus channel, and an output terminal thereof is connected to a 1st cache channel; a first input terminal of an (N+1)-th first sub-selector is connected to an N-th bus channel, and an output terminal thereof is connected to a backup cache channel.

[0053] Wherein, a first input terminal of an n-th second sub-selector is connected to an n-th cache channel, a second input terminal thereof is connected to an (n+1)-th cache channel, and an output terminal thereof is connected to an n-th memory channel; a first input terminal of an N-th second sub-selector is connected to an N-th cache channel, a second input terminal thereof is connected to the backup cache channel, and an output terminal thereof is connected to an N-th memory channel.

[0054] Figure 4 is a structural schematic diagram of a multiplexer of a data processing apparatus provided by an embodiment of the present disclosure. As shown in Figure 4 , the request input selector comprises N+1 first sub-selectors 41-1, 41-2, …, 41-(N-1), 41-N, 41-(N+1), and the request output selector comprises N second sub-selectors 42-1, …, 42-(N-2), 41-(N-1), 42-N.

[0055] Wherein, both the first sub-selector and the second sub-selector are 2-to-1 multiplexers, each first sub-selector or second sub-selector comprises a first input terminal (0), a second input terminal (1), an output terminal and a control terminal. When the control signal (Sel) input to the control terminal is 0, the sub-selector gates the data at the first input terminal (0) to the output terminal for output; when the control signal input to the control terminal is 1, the sub-selector gates the data at the second input terminal (1) to the output terminal for output.

[0056] In some possible implementation manners, there are N bus channels ch_1, …, ch_N-2, ch_N-1, ch_N at the inlet of the request input selector; the data on the request data path is packed by N bus_pack sub-modules, which facilitates the implementation and maintenance of RTL (Register Transfer Level).

[0057] In some possible implementation manners, for the n-th first sub-selector among N+1 first sub-selectors, the first input terminal thereof is connected to the (n-1)-th bus channel, the second input terminal thereof is connected to the n-th bus channel, and the output terminal thereof is connected to the n-th buffer channel, where 1<n≤N and n is an integer.

[0058] Wherein, for the first first sub-selector, the first input terminal thereof is connected to an all-zero signal 'h0, the second input terminal thereof is connected to the first bus channel, and the output terminal thereof is connected to the first buffer channel; for the (N+1)-th first sub-selector, the first input terminal thereof is connected to the N-th bus channel, the second input terminal thereof is connected to an all-zero signal 'h0, and the output terminal thereof is connected to a backup buffer channel;

[0059] In some possible implementation manners, the output data of the first sub-selector is unpacked by a bus_unpack sub-module and then input to a corresponding buffer channel, which comprises N buffer channels and one backup buffer channel.

[0060] In some possible implementation manners, there are N buffer channels 1~N at the inlet of the request output selector, which are represented as ch_1, …, ch_N-2, ch_N-1, ch_N, and a backup buffer channel ch_bak. Data output from the buffer channels is packed by an axi_pack sub-module and then input to the second sub-selector of the request output selector.

[0061] Among the N second sub-selectors, the nth second sub-selector has its first input (0) connected to the nth buffer channel, its second input (1) connected to the (n+1)th buffer channel, and its output connected to the nth memory channel; and the first input of the Nth second sub-selector is connected to the Nth buffer channel, its second input is connected to the backup buffer channel, and its output is connected to the Nth memory channel. The output data of the second sub-selector is unpacked by the data bus unpacking (axi_unpack) submodule and then input to the corresponding memory channels, including N memory channels ch_1, ..., ch_N-2, ch_N-1, and ch_N.

[0062] Implementing a multiplexer using multiple 2-to-1 selectors requires fewer additional logic resources, better meets the timing and area requirements of physical implementation, and improves the flexibility of physical implementation.

[0063] In some possible implementations, the control module is also used to: control N+1 first sub-selectors to select the second input terminal and control N second sub-selectors to select the first input terminal when there is no damaged path among the N data paths, so that the N data paths pass through N buffer channels respectively.

[0064] For example, for N+1 first sub-selectors, each first sub-selector has a 1-bit control signal. If no corrupted path exists in the N data paths, the second input terminal (1) is selected by default. The control signal output from the control module to the first sub-selector is represented as ~sel=1'b1, where ~ indicates inversion. That is, Figure 4 The left input terminal (1) of each first sub-selector is selected, and the backup buffer channel is not used. Among them, the N+1 first sub-selectors correspond to N-bit control signals ~sel[1], ..., ~sel[N-1], ~sel[N], and the control signal of the first and second first sub-selectors is ~sel[1].

[0065] In some possible implementations, for N second sub-selectors, each second sub-selector has a 1-bit control signal. If no corrupted path exists in the N data paths, the first input terminal (0) is selected by default. The control signal output by the control module to the second sub-selector is represented as sel = 1'b0. That is, Figure 4 The right input terminal (0) of each second sub-selector is selected, and the backup buffer channel is not used. Among them, the N second sub-selectors correspond to N bits of control signals sel[1], ..., sel[N-1], sel[N].

[0066] This approach enables data interaction across multiple data pathways under normal conditions, enhancing the flexibility of data interaction.

[0067] In some possible implementations, the corrupted path is the nth data path, and the control module is used for:

[0068] Control the first n-1 first sub-selectors to select the second input terminal, and control the first n-1 second sub-selectors to select the first input terminal, so that the first n-1 data paths pass through the first n-1 buffer channels respectively;

[0069] Control the (n+1)th first sub-selector to the (N+1)th first sub-selector to select the first input terminal, and control the (n)th second sub-selector to the (N)th second sub-selector to select the second input terminal, so that the (n)th data path to the (N)th data path passes through the (n+1)th cache channel to the (N)th cache channel and the backup cache channel, respectively.

[0070] For example, suppose the damaged path is the nth data path out of N data paths. When the test reveals that the nth data path is damaged, the control module can keep the control signals of the sub-selectors of the preceding n-1 data paths unchanged. That is, it controls the first n-1 first sub-selectors to select the second input terminal and controls the first n-1 second sub-selectors to select the first input terminal, so that the first n-1 data paths pass through the first n-1 buffer channels respectively.

[0071] In some possible implementations, for data paths after the nth data path, the control module can change the control signals of the (n+1)th first sub-selector to the (N+1)th first sub-selector to control the (n+1)th first sub-selector to select the first input terminal (0); and change the control signals of the (n)th second sub-selector to the (N)th second sub-selector to control the (n)th second sub-selector to select the second input terminal (1), so that the nth data path to the Nth data path respectively pass through the (n+1)th buffer channel to the Nth buffer channel and the backup buffer channel, thereby realizing the switching of data paths, maintaining the connection of N data paths, and ensuring the normal function of the data flow.

[0072] In the example, if N=32, then when all N data paths are normal, the control signal output by the control module is sel[32 :1]==32'h00000000 by default; if data path 29 is damaged (cache channel 29 is open-circuited), then sel[32 :1]==32'hf0000000 is configured, indicating that cache channels 32~29 are switched to the backup cache channel and cache channels 32~30 in sequence; cache channels 28~1 remain unchanged to ensure the normal function of the data flow.

[0073] In this manner, switching of backup cache channels can be implemented, and by selecting an adjacent normal cache channel for switching, wiring of the data path after switching can be reduced, enabling the timing requirements of data transmission to still be satisfied after switching and improving the processing efficiency of the entire system.

[0074] In some possible implementations, the control module is further configured to: in response to damage to the n-th data path, output a control signal to control the N+1 first sub-selectors and the N second sub-selectors to switch their gating states simultaneously.

[0075] For example, the control module can control the gating states of the N+1 first sub-selectors and the N second sub-selectors through the same set of control signals. The N second sub-selectors are controlled by control signals sel[1], ..., sel[N-1], sel[N]; the N+1 first sub-selectors are controlled by the inverted control signals ~sel[1], ..., ~sel[N-1], ~sel[N], wherein the first and the second first sub-selectors share the control signal ~sel[1].

[0076] In some possible implementations, when it is detected that the n-th data path is damaged, the control module can output a new set of control signals to control the N+1 first sub-selectors and the N second sub-selectors to switch their gating states simultaneously, so as to implement synchronous switching of data paths.

[0077] In this way, the probability of data error in the data path can be reduced, and the reliability and stability of system data transmission can be improved.

[0078] In some possible implementations, for the response data path, the second multiplexer comprises a response input selector (rsp_cache_in_mux), and the first multiplexer comprises a response output selector (rsp_cache_out_mux). The structures of the response input selector and the response output selector are described below.

[0079] In some possible implementations, the response input selector comprises N+1 third sub-selectors, the response output selector comprises N fourth sub-selectors, and both the third sub-selectors and the fourth sub-selectors are 2-out-of-1 selectors,

[0080] wherein a first input end of the n-th third sub-selector is connected to the (n-1)-th memory channel, a second input end of the n-th third sub-selector is connected to the n-th memory channel, and an output end of the n-th third sub-selector is connected to the n-th cache channel, with 1 < n ≤ N and n being an integer; a second input end of the first third sub-selector is connected to the first memory channel, and an output end of the first third sub-selector is connected to the first cache channel; a first input end of the (N+1)-th third sub-selector is connected to the N-th memory channel, and an output end of the (N+1)-th third sub-selector is connected to the backup cache channel;

[0081] wherein, a first input end of an n-th fourth sub-selector is connected to an n-th cache channel, a second input end of the n-th fourth sub-selector is connected to an n+1-th cache channel, and an output end of the n-th fourth sub-selector is connected to an n-th bus channel; a first input end of an N-th second sub-selector is connected to an N-th cache channel, a second input end of the N-th second sub-selector is connected to a backup cache channel, and an output end of the N-th second sub-selector is connected to an N-th bus channel.

[0082] For example, the circuit structure of a response input selector is similar to that of a request input selector, and the circuit structure of a response output selector is similar to that of a request output selector.

[0083] In some possible implementation manners, for an n-th third sub-selector among N+1 third sub-selectors of the response input selector, a first input end of the n-th third sub-selector is connected to an n-1-th memory channel, a second input end of the n-th third sub-selector is connected to an n-th memory channel, and an output end of the n-th third sub-selector is connected to an n-th cache channel, where 1<n≤N and n is an integer.

[0084] wherein, for a first third sub-selector, a first input end (0) of the first third sub-selector is connected to an all-zero signal 'h0, a second input end (1) of the first third sub-selector is connected to a first memory channel, and an output end of the first third sub-selector is connected to a first cache channel; for an N+1-th third sub-selector, a first input end of the N+1-th third sub-selector is connected to an N-th memory channel, a second input end of the N+1-th third sub-selector is connected to an all-zero signal 'h0, and an output end of the N+1-th third sub-selector is connected to a backup cache channel.

[0085] In some possible implementation manners, for an n-th fourth sub-selector among N fourth sub-selectors, a first input end (0) of the n-th fourth sub-selector is connected to an n-th cache channel, a second input end (1) of the n-th fourth sub-selector is connected to an n+1-th bus channel, and an output end of the n-th fourth sub-selector is connected to an n-th memory channel; furthermore, a first input end of an N-th fourth sub-selector is connected to an N-th cache channel, a second input end of the N-th fourth sub-selector is connected to a backup cache channel, and an output end of the N-th fourth sub-selector is connected to an N-th bus channel.

[0086] The manner of implementing a multiplexer through a plurality of 2-to-1 selectors can better meet the timing and area requirements of physical implementation and improve the flexibility of physical implementation.

[0087] In some possible implementation manners, the control module is further configured to: control N+1 third sub-selectors to gate the second input ends and control N fourth sub-selectors to gate the first input ends when there is no damaged channel among N data channels, so that the N data channels respectively pass through N cache channels. The control manner when there is no damaged channel among the N data channels is similar to that described above, and details are not described herein again.

[0088] In some possible implementation manners, the damaged channel is an n-th data channel, and the control module is configured to:

[0089] Control the first n-1 third sub-selectors to select the second input terminal, and control the first n-1 fourth sub-selectors to select the first input terminal, so that the first n-1 data paths pass through the first n-1 buffer channels respectively;

[0090] Control the (n+1)th third sub-selector to the (N+1)th third sub-selector to select the first input terminal, and control the (n)th fourth sub-selector to the (N)th fourth sub-selector to select the second input terminal, so that the (n)th data path to the (N)th data path passes through the (n+1)th cache channel to the (N)th cache channel and the backup cache channel, respectively.

[0091] The control method for the nth data path failure is similar to that described above, and will not be repeated here.

[0092] In some possible implementations, the control module is also used to: in response to damage to the nth data path, output a control signal to control the N+1 third sub-selectors and N fourth sub-selectors to switch their selection states simultaneously.

[0093] For example, the control module can control the selection states of N+1 first sub-selectors, N second sub-selectors, N+1 third sub-selectors, and N fourth sub-selectors using the same set of control signals. The N second sub-selectors and N fourth sub-selectors are controlled by control signals sel[1], ..., sel[N-1], sel[N]; the N+1 first sub-selectors and N+1 third sub-selectors are controlled by the inverted control signals ~sel[1], ..., ~sel[N-1], ~sel[N]. The first and second first sub-selectors and the first and second third sub-selectors share the control signal ~sel[1].

[0094] In some possible implementations, if the nth data path is found to be damaged, the control module can output a new set of control signals to control the N+1 first sub-selectors, N second sub-selectors, N+1 third sub-selectors and N fourth sub-selectors to switch their selection states simultaneously, so as to achieve synchronous switching of the data path in both the request and response directions.

[0095] In this way, the probability of data errors in the data path can be reduced, further improving the reliability and stability of system data transmission.

[0096] According to the data processing apparatus of the present disclosure, a backup cache channel can be added to the memory module, and a multiplexer can be set to map N bus channels to N cache channels and backup cache channels, and to map N cache channels and backup cache channels to N memory channels to form N data paths. In this way, when a data path is damaged, the multiplexer can be configured to select the cache channel and backup cache channel of the undamaged path, thereby ensuring that the number of data paths remains unchanged and ensuring the normal function of the memory system.

[0097] According to the data processing apparatus of this disclosure, by switching the damaged channel to the backup channel, the corresponding memory can be prevented from becoming unusable due to the damage of a certain channel, thus avoiding waste of chip resources. Furthermore, by selecting an adjacent normal cache channel for switching, the physical implementation of the chip can be satisfied without introducing timing risks. The backup cache channel is located on the channel between the bus interconnect module and the memory module, which does not result in a significant increase in area. The multiplexer is implemented using multiple 2-to-1 selectors, which requires less additional logic resources but has a significant benefit in improving memory utilization and the overall yield of the chip.

[0098] The data processing apparatus according to the embodiments of this disclosure can significantly improve the yield of the cache module in the system, thereby improving the overall yield of the chip, thus greatly reducing costs and improving the overall performance and quality of the chip.

[0099] It is understood that the various device embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further.

[0100] According to embodiments of this disclosure, a data processing method is also provided. This method is applied to a data processing apparatus, which includes a bus interconnect module and at least one multiplexing module. Each multiplexing module includes a first multiplexer, a cache module, a second multiplexer, and a memory module. For any multiplexing module: the bus interconnect module is connected to the first multiplexer of the multiplexing module via N bus channels, where N is an integer greater than 1; the first multiplexer maps the N bus channels to N cache channels and one backup cache channel of the cache module; the second multiplexer maps the N cache channels and one backup cache channel of the cache module to N memory channels of the memory module, thereby forming N data paths.

[0101] The method includes: when there are no damaged channels in the N data paths, controlling both the first multiplexer and the second multiplexer to select N buffer channels to form N data paths.

[0102] When there is a damaged data path among the N data paths, controlling the first multiplexer and the second multiplexer to gate the cache channels of undamaged paths and the backup cache channel among the N data paths, so as to form N data paths.

[0103] In some possible implementations, the first multiplexer includes a request input selector and a response output selector, and the second multiplexer includes a request output selector and a response input selector; the request input selector is configured to send data access requests from N bus channels to N cache channels and the backup cache channel; the request output selector is configured to send data access requests from N cache channels and the backup cache channel to N memory channels; the response input selector is configured to send response data from N memory channels to N cache channels and the backup cache channel; the response output selector is configured to send response data from N cache channels and the backup cache channel to N bus channels.

[0104] In some possible implementations, the request input selector includes N+1 first sub-selectors, the request output selector includes N second sub-selectors, both the first sub-selectors and the second sub-selectors are one-out-of-two selectors, wherein a first input end of the n-th first sub-selector is connected to the (n-1)-th bus channel, a second input end thereof is connected to the n-th bus channel, and an output end thereof is connected to the n-th cache channel, where 1 < n ≤ N and n is an integer; a second input end of the 1st first sub-selector is connected to the 1st bus channel, and an output end thereof is connected to the 1st cache channel; a first input end of the (N+1)-th first sub-selector is connected to the N-th bus channel, and an output end thereof is connected to the backup cache channel; wherein a first input end of the n-th second sub-selector is connected to the n-th cache channel, a second input end thereof is connected to the (n+1)-th cache channel, and an output end thereof is connected to the n-th memory channel; a first input end of the N-th second sub-selector is connected to the N-th cache channel, a second input end thereof is connected to the backup cache channel, and an output end thereof is connected to the N-th memory channel.

[0105] In some possible implementations, the damaged path is the n-th data path, and when there is a damaged path among the N data paths, controlling the first multiplexer and the second multiplexer to gate the cache channels of undamaged paths and the backup cache channel among the N data paths includes: controlling the first n-1 first sub-selectors to gate the second input ends, and controlling the first n-1 second sub-selectors to gate the first input ends, so that the first n-1 data paths respectively pass through the first n-1 cache channels; controlling the (n+1)-th first sub-selector to the (N+1)-th first sub-selector to gate the first input ends, and controlling the n-th second sub-selector to the N-th second sub-selector to gate the second input ends, so that the n-th data path to the N-th data path respectively pass through the (n+1)-th cache channel to the N-th cache channel and the backup cache channel.

[0106] In some possible implementations, when there is no damaged data path among the N data paths, controlling the first multiplexer and the second multiplexer to both select the N buffer channels comprises: when there is no damaged data path among the N data paths, controlling the N+1 first sub-selectors to select the second input terminals, and controlling the N second sub-selectors to select the first input terminals, such that the N data paths respectively pass through the N buffer channels.

[0107] In some possible implementations, when there is a damaged data path among the N data paths, controlling the first multiplexer and the second multiplexer to select the buffer channels for undamaged data paths and the backup buffer channel among the N data paths comprises: in response to damage occurring on the n-th data path, outputting a control signal to control the N+1 first sub-selectors and the N second sub-selectors to switch their gating states simultaneously.

[0108] In some possible implementations, the response input selector comprises N+1 third sub-selectors, the response output selector comprises N fourth sub-selectors, and both the third sub-selectors and the fourth sub-selectors are one-out-of-two selectors, wherein, a first input terminal of the n-th third sub-selector is connected to the (n-1)-th memory channel, a second input terminal thereof is connected to the n-th memory channel, and an output terminal thereof is connected to the n-th buffer channel, where 1<n≤N and n is an integer; a second input terminal of the first third sub-selector is connected to the first memory channel, and an output terminal thereof is connected to the first buffer channel; a first input terminal of the (N+1)-th third sub-selector is connected to the N-th memory channel, and an output terminal thereof is connected to the backup buffer channel; wherein, a first input terminal of the n-th fourth sub-selector is connected to the n-th buffer channel, a second input terminal thereof is connected to the (n+1)-th buffer channel, and an output terminal thereof is connected to the n-th bus channel; a first input terminal of the N-th second sub-selector is connected to the N-th buffer channel, a second input terminal thereof is connected to the backup buffer channel, and an output terminal thereof is connected to the N-th bus channel.

[0109] In some possible implementations, the damaged path is the n-th data path, and when there is a damaged data path among the N data paths, controlling the first multiplexer and the second multiplexer to select the buffer channels for undamaged data paths and the backup buffer channel among the N data paths comprises: controlling the first n-1 third sub-selectors to select the second input terminals, and controlling the first n-1 fourth sub-selectors to select the first input terminals, such that the first n-1 data paths respectively pass through the first n-1 buffer channels; controlling the (n+1)-th third sub-selector to the (N+1)-th third sub-selector to select the first input terminals, and controlling the n-th fourth sub-selector to the N-th fourth sub-selector to select the second input terminals, such that the n-th data path to the N-th data path respectively pass through the (n+1)-th buffer channel to the N-th buffer channel and the backup buffer channel.

[0110] The data processing method according to the embodiments of this disclosure, the corresponding technical solutions and descriptions and references to the apparatus section are not repeated here.

[0111] According to embodiments of this disclosure, an electronic device is also provided, which includes the data processing apparatus described above. This electronic device can be any type of electronic device, such as a terminal device or a server; this disclosure does not limit the specific type of electronic device.

[0112] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A data processing apparatus, characterized in that, The data processing apparatus comprises a graphics processing unit (GPU), and includes a bus interconnection module, a control module and at least one multi-channel selection module. Each multi-channel selection module comprises a first multiplexer, a cache module, a second multiplexer and a memory module, and the memory module comprises a high bandwidth memory (HBM) in the GPU. For any multi-channel selection module: The bus interconnection module is connected to the first multiplexer of the multi-channel selection module via N bus channels, wherein N is an integer greater than 1; The first multiplexer is configured to map the N bus channels to N cache channels and one backup cache channel of the cache module; The second multiplexer is configured to map the N cache channels and one backup cache channel of the cache module to N memory channels of the memory module, so as to form N data paths; The control module is configured to: control the first multiplexer and the second multiplexer to gate the undamaged cache channels in the N data paths and the backup cache channel when there is a damaged path among the N data paths.

2. The apparatus according to claim 1, characterized in that, The first multiplexer comprises a request input selector and a response output selector, and the second multiplexer comprises a request output selector and a response input selector; The request input selector is configured to send data access requests of the N bus channels to the N cache channels and the backup cache channel; The request output selector is configured to send data access requests of the N cache channels and the backup cache channel to the N memory channels; The response input selector is configured to send response data of the N memory channels to the N cache channels and the backup cache channel; The response output selector is configured to send response data of the N cache channels and the backup cache channel to the N bus channels.

3. The apparatus according to claim 2, characterized in that, The request input selector comprises N+1 first sub-selectors, the request output selector comprises N second sub-selectors, both the first sub-selectors and the second sub-selectors are 2-out-of-1 multiplexers, wherein, a first input end of the n-th first sub-selector is connected to the (n-1)-th bus channel, a second input end of the n-th first sub-selector is connected to the n-th bus channel, and an output end of the n-th first sub-selector is connected to the n-th cache channel, wherein 1 < n ≤ N and n is an integer; a second input end of the first first sub-selector is connected to the first bus channel, and an output end of the first first sub-selector is connected to the first cache channel; a first input end of the (N+1)-th first sub-selector is connected to the N-th bus channel, and an output end of the (N+1)-th first sub-selector is connected to the backup cache channel; wherein, a first input end of the n-th second sub-selector is connected to the n-th cache channel, a second input end of the n-th second sub-selector is connected to the (n+1)-th cache channel, and an output end of the n-th second sub-selector is connected to the n-th memory channel; a first input end of the N-th second sub-selector is connected to the N-th cache channel, a second input end of the N-th second sub-selector is connected to the backup cache channel, and an output end of the N-th second sub-selector is connected to the N-th memory channel.

4. The apparatus according to claim 3, characterized in that, The damaged path is the n-th data path, and the control module is configured to: controlling the first n-1 first sub-selectors to gate the second input terminals, and controlling the first n-1 second sub-selectors to gate the first input terminals, so that the first n-1 data paths respectively pass through the first n-1 cache channels; controlling the (n+1)-th first sub-selector to the (N+1)-th first sub-selector to gate the first input terminals, and controlling the n-th second sub-selector to the N-th second sub-selector to gate the second input terminals, so that the n-th data path to the N-th data path respectively pass through the (n+1)-th cache channel to the N-th cache channel and said backup cache channel.

5. The apparatus according to claim 3, characterized in that, The control module is further configured to: when there is no damaged path among the N data paths, controlling the N+1 first sub-selectors to gate the second input terminals, and controlling the N second sub-selectors to gate the first input terminals, so that the N data paths respectively pass through the N cache channels.

6. The apparatus according to claim 4, characterized in that, The control module is further configured to: in response to damage occurring on the n-th data path, outputting a control signal to control the N+1 first sub-selectors and the N second sub-selectors to switch their gating states simultaneously.

7. The apparatus according to claim 2, characterized in that, The response input selector comprises N+1 third sub-selectors, the response output selector comprises N fourth sub-selectors, and both the third sub-selectors and the fourth sub-selectors are one-out-of-two selectors, wherein the first input terminal of the n-th third sub-selector is connected to the (n-1)-th memory channel, the second input terminal of the n-th third sub-selector is connected to the n-th memory channel, the output terminal of the n-th third sub-selector is connected to the n-th cache channel, 1 < n ≤ N and n is an integer; the second input terminal of the first third sub-selector is connected to the first memory channel, the output terminal of the first third sub-selector is connected to the first cache channel; the first input terminal of the (N+1)-th third sub-selector is connected to the N-th memory channel, and the output terminal of the (N+1)-th third sub-selector is connected to said backup cache channel; wherein the first input terminal of the n-th fourth sub-selector is connected to the n-th cache channel, the second input terminal of the n-th fourth sub-selector is connected to the (n+1)-th cache channel, the output terminal of the n-th fourth sub-selector is connected to the n-th bus path; the first input terminal of the N-th second sub-selector is connected to the N-th cache channel, the second input terminal of the N-th second sub-selector is connected to said backup cache channel, and the output terminal of the N-th second sub-selector is connected to the N-th bus path.

8. The apparatus according to claim 7, characterized in that, The damaged path is the n-th data path, and the control module is configured to: controlling the first n-1 third sub-selectors to gate the second input terminals, and controlling the first n-1 fourth sub-selectors to gate the first input terminals, so that the first n-1 data paths respectively pass through the first n-1 cache channels; controlling the (n+1)-th third sub-selector to the (N+1)-th third sub-selector to gate the first input terminals, and controlling the n-th fourth sub-selector to the N-th fourth sub-selector to gate the second input terminals, so that the n-th data path to the N-th data path respectively pass through the (n+1)-th cache channel to the N-th cache channel and said backup cache channel.

9. The apparatus according to claim 1, characterized in that, The bus interconnection module is further connected to a plurality of processing modules of the data processing apparatus, and the processing modules respectively send data access requests to the memory module through the N data paths and receive response data from the memory module.

10. The apparatus according to claim 1, characterized in that, Each memory channel of the memory module corresponds to one storage unit of the memory module.

11. A data processing method, characterized in that, This is applied to a data processing device, which includes a graphics processing unit (GPU). The device includes a bus interconnect module and at least one multiplexing module. Each multiplexing module includes a first multiplexer, a cache module, a second multiplexer, and a memory module. The memory module includes high-bandwidth memory (HBM) within the GPU. For any multiplexing module: The bus interconnect module is connected to the first multiplexer of the multiplexing module through N bus channels, where N is an integer greater than 1; the first multiplexer is used to map the N bus channels to the N cache channels and 1 backup cache channel of the cache module. The second multiplexer is used to map the N cache channels and 1 backup cache channel of the cache module to the N memory channels of the memory module to form N data paths; The method includes: If there are no damaged paths in the N data paths, control both the first multiplexer and the second multiplexer to select the N buffer channels to form N data paths; If a damaged path exists among the N data paths, the first multiplexer and the second multiplexer are controlled to select the cached channel of the undamaged path and the backup cached channel among the N data paths to form N data paths.

12. An electronic device, characterized in that, The data processing apparatus includes any one of claims 1-10.

Images