Storage device backplane, device control method, apparatus, and device

Abstract

The application discloses a storage device backboard, a device control method, a device control device and a device, and relates to the technical field of servers. The storage device backboard is integrated with a mainboard connector, a path selector, a protocol converter, a storage interface and a type indicator. The type indicator indicates the protocol type of a storage device inserted on the storage interface, the mainboard connector obtains the protocol type from the type indicator, and according to the protocol type, outputs a selection signal and a first signal to the path selector, so that the path selector distributes the first signal output by the mainboard connector to the protocol converter or the storage interface according to the selection signal. The protocol converter also converts the first signal into a second signal matched with the protocol type, and outputs the second signal to the storage interface. The storage device backboard supports flexible switching of storage devices of multiple protocols, and solves the technical problems of poor hardware compatibility and high operation and maintenance cost when hard disks of different protocols are replaced in electronic devices.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a storage device backplane, device control method, apparatus and device. Background Technology

[0002] Electronic devices (such as servers) are equipped with storage device backplanes (such as hard drive backplanes) for inserting storage devices (such as M.2 hard drives).

[0003] Currently, electronic device manufacturers (such as server manufacturers) can flexibly configure the storage devices installed on the storage backplane according to the user's business needs. For example, in large-scale data storage scenarios, M.2 hard drives based on the Serial Advanced Technology Attachment (SATA) protocol are installed on the hard drive backplane to reduce the bill of materials (BOM) cost. In real-time data processing scenarios, solid-state drives based on the Peripheral Component Interconnect Express (PCIe) protocol are installed on the hard drive backplane to improve throughput.

[0004] However, when electronic devices are replaced with storage devices using different protocols, a corresponding storage device backplane needs to be configured for the replacement storage device (such as configuring a SATA protocol hard drive backplane for a SATA M.2 hard drive), resulting in poor hardware compatibility and high maintenance costs. Summary of the Invention

[0005] This application provides a storage device backplane, a device control method, an apparatus, and a device to at least solve the technical problems of poor hardware compatibility and high maintenance costs when replacing hard drives with different protocols in electronic devices.

[0006] This application provides a storage device backplane, including a motherboard connector, a protocol converter, a path selector, a storage interface, and a type indicator, wherein...

[0007] The protocol converter connects to the motherboard connector, the channel selector, and the storage interface. The channel selector also connects to the motherboard connector and the storage interface. The type indicator connects to the motherboard connector.

[0008] The motherboard connector is used to obtain the protocol type of the storage device plugged into the storage interface from the type indicator, and output a selection signal to the path selector according to the protocol type, and output a first signal to the path selector.

[0009] The path selector is used to allocate the first signal to the storage interface or protocol converter according to the selection signal;

[0010] The protocol converter is used to convert the first signal into a second signal that matches the protocol type, and output the second signal to the storage interface.

[0011] This application also provides a device control method, the method comprising:

[0012] Send a type indication signal to the controller on the motherboard; the type indication signal is used to indicate the protocol type of the storage device, which is inserted into the storage device backplane and connected to the motherboard;

[0013] Acquire the selection signal sent by the controller and the first signal output by the motherboard; the selection signal is determined according to the protocol type;

[0014] Based on the selection signal, a first signal is output to the storage device, or the first signal is converted into a second signal that matches the protocol type and then output to the storage device.

[0015] This application also provides a device control method, the method comprising:

[0016] Receives a type indication signal sent by the storage device backplane; the type indication signal is used to indicate the protocol type of the storage device, which is inserted into the storage device backplane and connected to the motherboard.

[0017] Send a selection signal to the storage device backplane; the selection signal is determined according to the protocol type; the selection signal is used to instruct the storage device backplane to output the first signal output by the motherboard to the storage device, or to instruct the storage device backplane to convert the first signal into a second signal that matches the protocol type and output the second signal to the storage device.

[0018] This application also provides a device control apparatus, the apparatus comprising:

[0019] The transceiver module is used to receive type indication signals sent by the storage device backplane; the type indication signal is used to indicate the protocol type of the storage device, which is inserted into the storage device backplane and connected to the motherboard;

[0020] The transceiver module is also used to send a selection signal to the storage device backplane; the selection signal is determined according to the protocol type; the selection signal is used to instruct the storage device backplane to output the first signal output by the motherboard to the storage device, or to instruct the storage device backplane to convert the first signal into a second signal that matches the protocol type and output the second signal to the storage device.

[0021] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described device control method.

[0022] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described device control method.

[0023] This application provides a storage device backplane, a device control method, an apparatus, and a device. The storage device backplane can support dynamic switching between storage devices using multiple protocols. When different types of storage devices need to be supported, users do not need to obtain and replace the storage device backplane with an adapted protocol, thus solving the technical problems of poor hardware compatibility and high maintenance costs when replacing hard drives with different protocols in electronic devices. Attached Figure Description

[0024] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is one of the schematic diagrams of the design scheme of the M.2 backplate provided in the embodiments of this application;

[0026] Figure 2 This is one of the structural schematic diagrams of the storage device backplane provided in the embodiments of this application;

[0027] Figure 3 This is a partially enlarged schematic diagram of the relevant signals of the path selector provided in the embodiments of this application;

[0028] Figure 4 This is a schematic diagram of the structure of a type of indicator provided in an embodiment of this application;

[0029] Figure 5 This is a second schematic diagram of the structure of the backplane of the storage device provided in the embodiments of this application;

[0030] Figure 6 This is the third schematic diagram of the structure of the storage device backplane provided in the embodiments of this application;

[0031] Figure 7 Fourth schematic diagram of the structure of the storage device backplane provided in the embodiments of this application;

[0032] Figure 8 This is the second schematic diagram of the design scheme of the M.2 backplate provided in the embodiments of this application;

[0033] Figure 9 One of the schematic flowcharts of the device control method provided in the embodiments of this application;

[0034] Figure 10A second schematic flowchart illustrating the device control method provided in this application embodiment;

[0035] Figure 11 The third schematic flowchart of the device control method provided in the embodiments of this application;

[0036] Figure 12 This is a schematic diagram of the structure of the device control apparatus provided in the embodiments of this application;

[0037] Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0039] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0040] It should be noted that in the embodiments of this application, certain software, components, devices, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, it does not mean that the applicant has used or necessarily used the solution.

[0041] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use, processing, transmission, provision, disclosure, and application of the relevant data all comply with relevant laws, regulations, and standards, necessary confidentiality measures have been taken, they do not violate public order and good morals, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0042] It should be noted that the "connection" between the electronic components in the embodiments of this application can be understood as an electrical connection. The connection between two electronic components can be a direct or indirect connection between the two electronic components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electronic components. For example, the connection between A and B can also be a direct connection between A and C, a direct connection between C and B, with A and B connected through C.

[0043] First, the terminology used in the embodiments of this application will be introduced.

[0044] 1. SATA: A computer hardware interface standard for serial data transmission, mainly used to connect storage devices such as mechanical hard drives and solid-state drives.

[0045] 2. PCIe: A high-speed serial computer expansion bus standard used to connect the motherboard to various high-speed peripheral devices.

[0046] 3. M.2 Interface: A type of board interface with a width of 22mm and lengths of 2230, 2242, 2280, etc. It can support SATA (SATA mode) devices and PCIe (Non-Volatile Memory Express, NVMe) devices through pin multiplexing, requiring hardware or firmware configuration protocols.

[0047] 4. Jumper Configuration: By physically shorting specific pins (such as pin 1 to pin 2 or pin 2 to pin 3), the circuit state (e.g., high or low level) can be changed. This eliminates the need for soldering or removing components; function switching is achieved through hardware configuration, simplifying BOM management.

[0048] 5. Printed Circuit Board Assembly (PCBA): This is the finished board formed by soldering electronic components onto a printed circuit board (PCB).

[0049] The scenarios involved in the embodiments of this application will be described below.

[0050] Electronic devices (such as servers) serve as data storage, processing, and transmission carriers. They possess high-speed central processing unit (CPU) computing power, long-term reliable operation characteristics, powerful input / output (I / O) external data throughput capabilities, and excellent scalability, making them suitable for data processing in scenarios such as data centers, cloud computing platforms, artificial intelligence training clusters, and high-performance computing (HPC).

[0051] Electronic devices are provided with a storage device backplane, which can be used to insert storage devices. The storage device backplane may include, but is not limited to, a hard drive backplane and / or a memory card backplane; the storage device may include, but is not limited to, a hard drive and / or a memory card.

[0052] Taking servers as an example, server systems (or "server assembly systems") typically require support for M.2 hard drives, which are storage devices that conform to the M.2 interface specification. M.2 hard drives and traditional solid-state drives (SSDs) differ significantly in interface type, speed, performance, physical size, form factor, installation, and compatibility. Compared to SSDs, M.2 hard drives offer a smaller size, faster read / write speeds, and more advanced interface technology.

[0053] M.2 SSDs utilize the M.2 interface specification, giving them greater flexibility and scalability. M.2 SSDs support multiple transmission protocols, such as SATA and NVMe (based on PCIe), allowing for flexible configuration to suit different application scenarios and performance requirements.

[0054] In server systems, M.2 hard drives typically connect to the motherboard via an M.2 backplane. Depending on the specific business requirements, engineers can develop different types of M.2 backplanes to support different types of M.2 hard drives. For example, a SATA protocol M.2 backplane might be developed to support SATA M.2 hard drives, or a PCIe protocol M.2 backplane might be developed to support PCIe M.2 hard drives. These two protocol M.2 backplanes are usually based on completely different PCBs and cannot be shared.

[0055] In some examples, the M.2 backplane may also be referred to as the "M.2 adapter backplane".

[0056] When electronic devices are replaced with storage devices using different protocols, a corresponding storage device backplane needs to be configured for the replacement storage device (such as configuring a SATA protocol hard drive backplane for a SATA M.2 hard drive), resulting in poor hardware compatibility and high maintenance costs.

[0057] Therefore, how to make M.2 backplanes compatible with M.2 storage devices using multiple protocols has become an urgent problem to be solved.

[0058] In the embodiments of this application, the technicians have discovered through research that an M.2 backplane that simultaneously supports the SATA protocol and the PCIe protocol can be designed. The PCB of the M.2 backplane can adopt a unified hardware design, and according to the protocol type of the M.2 storage device supported by the M.2 backplane, different specifications of electronic components (such as protocol adapter modules, interface matching circuits, etc.) can be configured for the PCB.

[0059] Figure 1 This is one of the schematic diagrams of the M.2 backplate design provided in an embodiment of this application. Please refer to... Figure 1 The motherboard (MB) has cable connector 1, and the backplane (BP) has cable connector 2 and M.2 interface (M.2 CONN).

[0060] Cable connector 1 and cable connector 2 can support multiple protocols, including but not limited to PCIe protocol and / or Serial Attached SCSI (SAS) protocol.

[0061] The cable connector 2 in this M.2 backplane is connected to the cable connector 1 on the motherboard via a cable. For example, cable connector 1 and cable connector 2 can be SlimSAS connectors (CONN), and the two cable connectors are connected to each other via a SlimSAS cable.

[0062] In some embodiments, the M.2 interface may also be referred to as an "M.2 connector". The M.2 interface refers to the physical interface of an M.2 hard drive, which supports the SATA or E protocol.

[0063] exist Figure 1 The M.2 backplane design shown supports two types of M.2 backplanes using the same PCB: an M.2 backplane supporting SATA protocol M.2 hard drives and an M.2 backplane supporting PCIe protocol M.2 hard drives.

[0064] exist Figure 1In the diagram, the CNS mark on the right side of some electronic components indicates that this electronic component (i.e., this part of the electronic components) will not be installed when the PCB supports SATA M.2 hard drives. The CNP mark on the right side of other electronic components indicates that this electronic component (i.e., this part of the electronic components) will not be installed when the PCB supports PCIe M.2 hard drives.

[0065] In an M.2 backplane supporting SATA M.2 storage devices, a protocol converter can be present between the cable connector 2 and the storage interface. This protocol converter can be used for protocol conversion. For example, this protocol converter can be used to implement PCIe-to-SATA protocol conversion, converting PCIe signals to SATA signals for compatibility with SATA protocol devices.

[0066] For example, the protocol converter can be a PCIe to SATA controller, such as an ASM1064 controller.

[0067] Below, taking the ASM1064 controller as an example for protocol converter, we will... Figure 1 The connection relationships between the components in the M.2 backplane design shown are explained.

[0068] like Figure 1 As shown, there are multiple signal lines between cable connector 1 and cable connector 2. These signal lines are arranged from top to bottom as follows:

[0069] (1) PCIe_M2 <1> : This is the differential signal pair of the first PCIe lane on the M.2 interface, used for transmitting high-speed data.

[0070] (2) CLK_100M: is the 100MHz reference clock signal of the M.2 interface (Clock 100MHz), which provides a timing synchronization reference for signal transmission of PCIe channel, SATA protocol and other protocols.

[0071] (3) PERST: is the PCIe interface reset signal (PCI Express Reset), used for reset control of PCIe devices with M.2 interface during power-on initialization or abnormality, to ensure that the device returns to its initial working state.

[0072] (4) M2_PRSNT_N: This is the presence detection signal (M.2 Present Negative) of the M.2 storage device (such as M.2 hard disk) inserted into the M.2 interface. It is used to detect whether an M.2 storage device is inserted into the M.2 interface and to provide the system with device access status feedback.

[0073] (5) PCIe_M2 <0> : This is the differential signal pair of the 0th PCIe lane on the M.2 interface, and PCIe_M2 <1> It works collaboratively to transmit high-speed data and supports x1 / x2 / x4 multi-channel configuration.

[0074] (6) CLK_100M_ASM1064: is a 100MHz reference clock signal provided for the ASM1064 controller (100MHz Clock for ASM1064), used to synchronize the signal processing timing of PCIe to SATA.

[0075] (7) SATA_CTRL_PERST: This is the reset signal for the ASM1064 controller (SATA Controller Reset), used to reset the ASM1064 controller.

[0076] (8) M2_TYPE_ID: This is the M.2 Type Identification signal for M.2 storage devices, used to identify the protocol type (SATA / NVMe) of the inserted M.2 storage device and achieve protocol adaptation. The protocol type can be SATA protocol or Non-Volatile Memory Express (NVMe) protocol (based on PCIe).

[0077] (9) BMC_I2C: is the I2C (Inter-Integrated Circuit) bus signal pair between the Baseboard Management Controller (BMC) and the M.2 storage device, used for out-of-band management operations such as device status monitoring and configuration information reading.

[0078] (10) RST_M2_9546_N: This is a reset signal for the 9546 controller (such as the PCIe switch controller) related to the M.2 interface. It is used to reset the 9546 controller related to the M.2 interface to ensure that the signal routing function is normal.

[0079] (11) P3V3_VR_EN: is the 3.3V Voltage Regulator Enable signal, which is used to control the 3.3V power output of the M.2 backplane. After being enabled, it provides working power to the M.2 backplane.

[0080] (12) P12V_STBY: is the 12V standby power signal of the M.2 backplane, which provides low power supply for the M.2 backplane in standby mode and supports functions such as device presence detection and wake-up.

[0081] (13) P3V3_STBY: is the 3.3V standby power signal of the M.2 backplane, which provides stable power supply for the standby state of the M.2 backplane and ensures the status monitoring and rapid wake-up of the device during standby.

[0082] like Figure 1 As shown, the following signal line exists between cable connector 2 and the M.2 interface: PCIe_M2 <1> CLK_100M, PERST, and M2_PRSNT_N.

[0083] In the M.2 backplane, some electronic components between the cable connector 2 and the M.2 interface differ depending on whether the CNP or CNS markings are used.

[0084] (1) CNP mark

[0085] According to the CNP marking, in an M.2 backplane supporting SATA M.2 storage devices, the ASM1064 controller and related electronic components are located on the backplane, while the CNS-marked cable connector 2 connects to the PCIe_M2 interface. <0> No additional components are required for the signal cable.

[0086] like Figure 1 As shown, cable connector 2 is connected to the ASM1064 controller, and the following signal line exists between cable connector 2 and the ASM1064 controller: PCIe_M2 <0> CLK_100M_ASM1064, SATA_CTRL_PERST. The ASM1064 controller and the M.2 interface have a SATA_M2 interface. <0> The signal line, the SATA_M2 <0> The signal is from the ASM1064 controller to PCIe_M2 <0> The signal is obtained by protocol conversion (PCIe→SATA).

[0087] The ASM1064 controller also connects to flash memory via a Serial Peripheral Interface (SPI) signal line. This flash memory can be used to store the firmware of the ASM1064 controller, which can be used for the initialization and functional configuration of the ASM1064 controller.

[0088] The ASM1064 controller also needs to be connected to the P3V3_ASM signal line and the P1V05_ASM signal line. The P3V3_ASM signal line can provide 3.3V operating power to the ASM1064 controller, and the P1V05_ASM signal line can provide 1.05V operating power to the ASM1064 controller.

[0089] exist Figure 1In the M.2 backplane design shown, cable connector 2 is also connected to the M2_TYPE_ID signal line. This M2_TYPE_ID signal is used to inform the BMC on the motherboard about the type of the M.2 backplane (such as PCIe or SATA). When the M2_TYPE_ID signal is high, it indicates that the M.2 backplane is a PCIe M.2 backplane; when the M2_TYPE_ID signal is low, it indicates that the M.2 backplane is a SATA M.2 backplane.

[0090] (2) CNS mark

[0091] According to the CNS markings, in an M.2 backplane supporting PCIe M.2 storage devices, the PCIe_M2 cable connector 2 is located between the M.2 interface and the PCIe M.2 port. <0> The signal line component is not required, while the CNP-marked ASM1064 controller and related electronic components will not require the component.

[0092] According to the CNS designation, the M.2 interface is also connected to an I2C bus level conversion module (CA9617MMR), which can be used for I2C signal conversion between different voltage domains. The CA9617MMR and the M.2 interface are also connected to the P1V8 signal line.

[0093] The CA9617MMR also connects to a software-simulated I2C (I2C SW) via the SW_I2C_M2 signal line. This I2C SW can simulate I2C timings through General Purpose Input / Output (GPIO). The I2C SW can also connect to cable connector 2 via the RST_M2_9546_N and BMC_I2C signal lines. Furthermore, the I2C SW connects to the Field Replaceable Unit (FRU) and the sensor via the SMB_SW_I2C signal line, respectively.

[0094] exist Figure 1 In this configuration, cable connector 2 is also connected to voltage regulator (VR) 1 via P3V3_VR_EN and P12V_STBY signal lines to output P3V3_VR_EN and P12V_STBY signals to VR1. Cable connector 2 also provides a P3V3_STBY signal to the M.2 backplane via the P3V3_STBY signal line.

[0095] VR1 can output the PWRGD_P3V3 signal to VR2, the P3V3_ASM signal to the ASM1064 controller, and the P3V3 signal to the M.2 interface.

[0096] VR2 can output the PWRGD_P1V8 signal to VR3 and provide the P1V8 signal to the M.2 backplane.

[0097] VR3 can output the P1V05_ASM signal to the ASM1064 controller.

[0098] based on Figure 1 The M.2 backplane design shown allows developers to flexibly select the corresponding BOM (Bill of Materials) for the M.2 hard drive protocol type to fabricate the PCB, resulting in a PCBA (Printed Circuit Board Assembly). By marking the design with CNS and CNP symbols, both M.2 protocol types can share the same PCB design. Compared to designing two different PCB designs for different M.2 backplanes to support different protocol types, this approach reduces the number of new PCBs, increases PCB reuse, and lowers the development costs for layout engineers.

[0099] However, during the development of servers, depending on different business scenarios or the requirements of motherboard connector interface limitations, the interface on the motherboard connecting to the M.2 backplane may need to support both SATA M.2 hard drives and PCIe M.2 hard drives. Figure 1 The M.2 backplane design shown can integrate M.2 backplanes that support SATA protocol M.2 hard drives and M.2 backplanes that support PCIe protocol M.2 hard drives onto the same PCB. By simply selecting different BOMs, two types of M.2 backplanes can be obtained. However, the actual assembled PCBA needs to be configured with different specifications of electronic components (such as protocol adapter modules, interface matching circuits, etc.) according to the type of M.2 hard drive supported by the M.2 backplane.

[0100] In other words, these two types of M.2 backplanes are different PCBA boards with different electronic components on their PCBs. This results in the BOMs (Bill of Materials) for the corresponding PCBs of these two types of M.2 backplanes being incompatible. Separate management of the two PCBA part numbers for these two types of M.2 backplanes is required, which is not streamlined. When the type of hard drive is changed, the BOM must also be changed accordingly. Furthermore, the above problems prevent users from flexibly switching between M.2 hard drives with different protocols on the same PCBA. When support for different types of M.2 hard drives is required, users still need to replace the M.2 backplane with one that adapts to the correct protocol, leading to poor hardware compatibility and high maintenance costs. For example, when server 1 needs to be changed from a PCIe M.2 storage device (such as a PCIe M.2 hard drive) to a SATA M.2 storage device, the user needs to reconfigure the M.2 backplane corresponding to the SATA M.2 storage device, which is inflexible.

[0101] To address the aforementioned issues, this application also provides a storage device backplane that is compatible with multiple protocols simultaneously. This storage device backplane integrates a motherboard connector, a path selector, a protocol converter, a storage interface, and a type indicator. The type indicator indicates the protocol type of the storage device plugged into the storage interface. The motherboard connector can obtain the protocol type from the type indicator and indicate this protocol type to the motherboard connected to the motherboard. Through the cooperation of the motherboard connector and the type indicator, the controller on the motherboard can promptly know the protocol type corresponding to the storage device plugged into the storage interface, allowing the controller to send a selection signal corresponding to that protocol type to the motherboard connector in a timely manner. This storage device backplane is suitable for scenarios with limited motherboard interface resources. By maximizing the utilization of hardware resources through a single-board design, it can support future protocol expansion needs of storage devices.

[0102] The motherboard connector can also acquire the selection signal and the first signal output by the motherboard, and output the selection signal and the first signal to the path selector, so that the path selector allocates the first signal output by the motherboard connector to the protocol converter or storage interface according to the selection signal. The protocol converter can also convert the first signal into a second signal that matches the protocol type and output the second signal to the storage interface.

[0103] The first and second signals can be used for data (such as high-speed data) transmission, and the first and second signals are signals of different protocol types.

[0104] For example, the first signal can be PCIe_M2 <0> The second signal can be SATA_M2. <0> Signal.

[0105] In some embodiments, this selection signal may also be referred to as a "strobe signal". For example, the selection signal may be represented as "PCIe_SATA_S", which can be used to indicate the protocol type corresponding to the storage device.

[0106] This storage backplane integrates the motherboard connector, protocol converter, path selector, storage interface, and type indicator into the storage device backplane. Through the coordinated control of these components, it enables flexible switching between signal transmission channels corresponding to different protocol types between the motherboard connector and the storage interface, based on the storage device's protocol type. This integrated design allows the motherboard to provide a unified first signal to the storage device backplane, eliminating the need for the motherboard to send different protocol type signals based on the storage device's protocol. This simplifies the interaction between the motherboard and the storage device backplane and helps eliminate redundant hardware. Furthermore, this storage device backplane supports flexible switching between storage devices with multiple protocols. When supporting different types of storage devices is required, users do not need to acquire and replace a storage device backplane with an adapted protocol, nor do they need to change the BOM due to changes in the storage device's protocol type. This solves the problems of poor compatibility, high cost, and complex operation and maintenance caused by hardware replacement.

[0107] The storage device backplane indicates the protocol type to the motherboard via the motherboard connector. Based on the selection signal output by the motherboard, it directly sends a first signal to the storage device on the storage interface via the motherboard connector and a path selector; alternatively, it performs protocol conversion on the first signal to obtain a second signal, which is then sent to the storage device on the storage interface. In this process, the type indicator, motherboard connector, path selector, protocol converter, and storage interface form a feedback loop. This allows the storage device backplane to promptly switch the signal transmission channel of the first signal according to changes in the protocol type of the storage device plugged into the storage interface, making it compatible with storage devices using multiple protocols (such as SATA and PCIe), thus exhibiting good hardware compatibility.

[0108] The storage device backplane provided in this application embodiment can support dynamic switching of storage devices with multiple protocols based on a single PCB and PCBA, achieving dynamic compatibility of a single board. Based on this storage device backplane, users can flexibly switch between storage devices with different protocols directly on the same PCBA. When supporting different types of storage devices is required, users do not need to obtain and replace the storage device backplane with the appropriate protocol, which helps reduce operational complexity and costs, improves operational flexibility, and meets the needs of rapid server configuration adjustments. Furthermore, this storage device backplane does not require configuring different BOMs for storage devices with different protocol types, thus eliminating the need to maintain two different PCBA part numbers, further reducing operational complexity and costs.

[0109] The technical solutions of the embodiments of this application will be described in detail below with specific examples. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0110] Figure 2 This is one of the structural schematic diagrams of the backplane of the storage device provided in an embodiment of this application. Please refer to... Figure 1 The storage device backplane 10 includes a motherboard connector 101, a path selector 102, a protocol converter 103, a storage interface 104, and a type indicator 105.

[0111] Protocol converter 103 is connected to motherboard connector 101, channel selector 102 and storage interface 104. Channel selector 102 is also connected to motherboard connector 101 and storage interface 104. Type indicator 105 is connected to motherboard connector 101.

[0112] In some embodiments, the storage interface 104 can be used to insert the storage device 20.

[0113] For example, the storage device backplane may be, but is not limited to, a hard drive backplane, and the storage device may be, but is not limited to, a hard drive. For instance, the storage device backplane may be an M.2 backplane, the storage interface may be an M.2 interface, and the storage device may be an M.2 hard drive.

[0114] This application embodiment is based on a unified BOM for manufacturing storage device backplanes, which can simultaneously support flexible switching between storage devices of multiple protocol types (SATA storage devices and PCIe storage devices). Based on this application embodiment, technicians do not need to configure different BOMs for storage devices of different protocol types when manufacturing storage device backplanes, or change the BOM when the protocol type of the storage device is updated, which helps to reduce research and development and maintenance costs.

[0115] The following is a detailed description of the electronic components on the back panel of the storage device.

[0116] (1) Motherboard connector 101

[0117] The motherboard connector 101 can support multiple protocols, including but not limited to PCIe and / or SAS protocols. For example, the motherboard connector 101 can be... Figure 1 The cable connector 2 shown can be a SlimSAS connector.

[0118] In some embodiments, the motherboard connector 101 can be used to connect to the motherboard 30. Optionally, the motherboard 30 may include... Figure 1The cable connector 1 shown can be connected to the motherboard connector 101.

[0119] The motherboard connector 101 is used to obtain the protocol type of the storage device 20 inserted on the storage interface 104 from the type indicator 105, and output a selection signal to the path selector 102 according to the protocol type, and output a first signal to the path selector 102.

[0120] The protocol type may include, but is not limited to, PCIe and / or SATA protocols.

[0121] For example, when the storage interface is an M.2 interface and the storage device is an M.2 storage device, the type indication signal can be represented as "M2_TYPE_ID signal".

[0122] Optionally, the selection signal can be a high-level signal or a low-level signal.

[0123] The selection signal is determined based on the protocol type. If the protocol type is the first protocol type corresponding to the first signal, the selection signal is a high-level signal, meaning the controller outputs a high-level signal to the motherboard connector; if the protocol type is the second protocol type corresponding to the second signal, the selection signal is a low-level signal, meaning the controller outputs a low-level signal to the motherboard connector.

[0124] The first signal can be used for data transmission, such as high-speed data transmission. For example, the first signal could be PCIe_M2. <0> Signal.

[0125] In some embodiments, a controller may be provided on the motherboard 30. Specifically, the motherboard connector 101 can be used to: acquire a type indication signal output by a type indicator and send the type indication signal to the controller; wherein the type indication signal is used to indicate a protocol type; the type indication signal is a high-level signal or a low-level signal, the voltage value of the high-level signal being higher than the voltage value of the low-level signal; the high-level signal is used to indicate that the protocol type is a first protocol type corresponding to a first signal, and the low-level signal is used to indicate that the protocol type is a second protocol type corresponding to a second signal. The second signal is obtained by protocol conversion of the first signal through a protocol converter.

[0126] The type indicator signal is used to indicate the protocol type. Alternatively, it can be stated that the type indicator signal indicates the type of storage device plugged into the storage interface, and this type of storage device is associated with its protocol type. For example, if the protocol type is PCIe, the storage device type is PCIe storage device; if the protocol type is SATA, the storage device type is SATA storage device.

[0127] Similarly, the second signal can be used for data (such as high-speed data) transmission, and the second signal and the first signal are signals of different protocol types.

[0128] For example, if the first signal is PCIe_M2 <0> The first signal is a PCIe protocol; if the second signal is SATA_M2 <0> The signal type is SATA.

[0129] After replacing storage devices with different protocol types on the storage device backplane, the type indicator can flexibly output the corresponding type indication signal according to the protocol type switch of the storage device. The motherboard connector can output the type indication signal output by the type indicator to the motherboard, so that the controller on the motherboard can know in time that the protocol type of the storage type has been switched and the protocol type of the storage device currently plugged into the storage interface. Based on the protocol type, it outputs the correct selection signal to the motherboard connector, so as to instruct the path selector to allocate the first signal to the correct signal transmission channel. When the protocol type of the storage device is updated, the storage device backplane can convert the first signal output by the motherboard into a second signal that matches the protocol type of the storage device, and output the second signal to the storage device. This allows the storage device backplane to still be compatible with the storage device plugged into the storage interface, thereby achieving compatibility of a single storage device backplane with storage devices of different protocol types and reducing the maintenance complexity of storage device replacement.

[0130] In some embodiments, the motherboard connector 101 is further configured to: acquire a selection signal sent by the controller and a first signal output by the motherboard, and output the selection signal and the first signal to the channel selector.

[0131] In the backplane of the storage device, the motherboard connector 101 can be used to connect to the motherboard and correctly transmit the selection signal and the first signal output by the motherboard to the path selector, so as to realize the correct switching of the signal transmission channel of the first signal through the path selector, thereby ensuring that the backplane of the storage device can be adapted to the storage device inserted in the storage interface.

[0132] Alternatively, the motherboard connector can also be connected to the storage interface via the following signal lines: PCIe_M2 <1> Signal lines, CLK_100M signal line, PERST signal line, M2_PRSNT_N signal line. There can be signal lines for transmitting selection signals and signal lines for transmitting the first signal between the motherboard connector and the channel selector.

[0133] Optionally, the motherboard connector can also be connected to the I2C SW via the RST_M2_9546_N signal line and the BMC_I2C signal line. The I2C SW can also be connected to the FRU and the sensor via the SMB_SW_I2C signal line, and to the CA9617MMR via the SW_I2C_M2 signal line.

[0134] (2) Path selector 102

[0135] A path selector is a hardware module that selectively connects different circuit paths by controlling signals.

[0136] In some embodiments, the path selector may also be used interchangeably with terms such as “line switching switch” and “gating switch”.

[0137] A path selector can be used to assign a first signal to a storage interface or protocol converter based on a selection signal.

[0138] In some embodiments, the path selector may include a signal input pin and a signal output pin, wherein:

[0139] The signal input pins include: a first signal input pin for receiving a selection signal, a second signal input pin for receiving an output signal from the motherboard connector, a third signal input pin for receiving an output signal from the protocol converter, and a fourth signal input pin for receiving an output signal from the storage interface.

[0140] The signal output pins include: a first signal output pin for outputting signals to the motherboard connector, a second signal output pin for outputting signals to the protocol converter, and a third signal pin for outputting signals to the storage interface.

[0141] Optionally, the first signal, the output signal of the protocol converter, the output signal of the storage interface, and the signal output by the path selector to the motherboard connector can be differential signal pairs.

[0142] Figure 3 This is a partially enlarged schematic diagram of the relevant signals of the path selector provided in an embodiment of this application. Please refer to... Figure 3 The path selector (SW) has 13 pins. These 13 pins include:

[0143] Pin S: Used to receive the PCIe_SATA_S signal, which can be understood as the selection signal mentioned above.

[0144] Pin A: Used to receive the positive data signal (PCIe_TX_DP) from the motherboard connector's output signals. The motherboard connector's output signals include the first signal.

[0145] Pin B: Used to receive the negative data signal (PCIe_TX_DN) from the output signal of the motherboard connector. The PCIe_TX_DP and PCIe_TX_DN can form a differential signal pair, which is used by the motherboard connector to transmit data to the path selector (SW).

[0146] Pin C: Used to output a positive data signal (PCIe_RX_DP) to the motherboard connector.

[0147] Pin D: Used to output a negative data signal (PCIe_RX_DN) to the motherboard connector. PCIe_RX_DP and PCIe_RX_DP can form a differential signal pair, which is used by the path selector (SW) to transmit data to the motherboard connector.

[0148] Pin A1: Used to output a positive data signal (SATA_TX_DP) to the protocol converter.

[0149] Pin A2: Used to output a positive data signal (PCIe_SW_TX_DP) to the storage interface.

[0150] Pin B1: Used to output a negative data signal (SATA_TX_DN) to the protocol converter. SATA_TX_DP and SATA_TX_DN can form a differential signal pair, which is used by the path selector (SW) to transmit data to the protocol converter.

[0151] Pin B2: Used to output a negative data signal (PCIe_SW_TX_DN) to the storage interface. PCIe_SW_TX_DP and PCIe_SW_TX_DN can form a differential signal pair, which is used by the path selector (SW) to transmit data to the storage device inserted on the storage interface.

[0152] Pin C1: Used to receive the positive data signal (SATA_RX_DP) from the output signal of the protocol converter.

[0153] Pin C2: Used to receive the positive data signal (PCIe_SW_RX_DP) from the output signal of the storage interface.

[0154] Pin D1: Used to receive the negative data signal (SATA_RX_DN) from the output signal of the protocol converter. SATA_RX_DP and SATA_RX_DN can form a differential signal pair, which is used by the protocol converter to transmit data to the path selector (SW).

[0155] Pin D2: Used to receive the negative data signal (PCIe_SW_RX_DN) from the output signal of the storage interface. PCIe_SW_RX_DP and PCIe_SW_RX_DN can form a differential signal pair, which is used by the storage device inserted on the storage interface to transmit data to the path selector (SW).

[0156] For example, in Figure 3 In this configuration, the protocol converter can be an ASM1064 controller, and the storage interface can be an M.2 interface.

[0157] In some embodiments, if the selection signal is a low-level signal, the path selector (SW) outputs a first signal to the protocol converter based on the low-level signal. The protocol converter converts the first signal into a second signal and outputs the second signal to the storage interface, so that the controllers on the motherboard can communicate with the storage device of the second protocol type inserted on the storage interface based on the second signal.

[0158] If the selection signal is a high-level signal, the path selector (SW) outputs a first signal to the storage interface based on the high-level signal, so that each controller on the motherboard can communicate with the storage device of the first protocol type inserted on the storage interface based on the first signal.

[0159] (3) Protocol converter 103

[0160] The protocol converter is used to convert the first signal into a second signal that matches the protocol type, and output the second signal to the storage interface.

[0161] In some embodiments, the following signal line may be connected between the motherboard connector and the protocol converter: PCIe_M2 <0> CLK_100M_ASM1064 and SATA_CTRL_PERST.

[0162] The protocol converter is also connected to flash memory via an SPI signal line. This flash memory can be used to store the firmware of the protocol converter, which can be used for the initialization and functional configuration of the protocol converter.

[0163] The protocol converter can also be connected to power supply signal lines. For example, if the protocol converter requires both a 3.3V and a 1.05V operating power supply, it can be connected to the P3V3_protocol converter power supply signal line and the P1V05_protocol converter power supply signal line. The P3V3_protocol converter power supply signal line can provide the protocol converter with a 3.3V operating power supply, and the P1V05_protocol converter power supply signal line can provide the protocol converter with a 1.05V operating power supply.

[0164] (4) Storage interface 104

[0165] The storage interface can be used to insert storage devices. For example, the storage interface is an M.2 interface, which can be used to insert M.2 storage devices.

[0166] There may be a signal line between the storage interface and the path selector for transmitting the first signal, and there may be a signal line between the storage interface and the protocol converter for transmitting the second signal.

[0167] Optionally, the storage interface can also be connected to an I2C bus level conversion module (CA9617MMR), and the storage interface and the I2C bus level conversion module are also connected to the P1V8 signal line respectively.

[0168] (5) Type indicator 105

[0169] In some embodiments, the type indicator 105 further includes a first pin, a second pin, and a third pin, wherein the first pin is used to connect to a pull-high power supply, which provides a high-level signal to the type indicator; the second pin is connected to the motherboard connector; and the third pin is used to ground.

[0170] Alternatively, the power supply can be a 3.3V standby power supply on the backplane of the storage device.

[0171] Optionally, the second pin can be connected to the motherboard connector via a type indicator signal line, and the motherboard connector can be connected to a controller (such as a BMC) on the motherboard via the type indicator signal line, thereby realizing the connection between the type indicator and the controller.

[0172] The type indicator signal line is used to transmit a type indicator signal. For example, the type indicator signal line is the M2_TYPE_ID signal line.

[0173] In some embodiments, the type indicator also includes a jumper cap configured to selectively connect two pins of the type indicator to switch the circuit on state.

[0174] A jumper cap is a hardware component that enables signal configuration by physically connecting different pins.

[0175] In some embodiments, the type indicator is specifically used to: output a high-level signal to the motherboard connector if the jumper is connected to the first and second pins; or, output a low-level signal to the motherboard connector if the jumper is connected to the second and third pins.

[0176] By introducing jumper cap configuration into the type indicator, the type indicator signal can dynamically switch as the protocol type of the storage device plugged into the storage interface changes, thus improving the hardware compatibility of the storage device. Users can switch between storage devices with different protocol types without replacing the storage device backplane; protocol adaptation is achieved simply by adjusting the jumper cap position and selection signal, reducing hardware costs and operational complexity.

[0177] It should be noted that in some examples, this pin can also be used interchangeably with terms such as "Pin".

[0178] Figure 4 This is a schematic diagram of the structure of a type indicator provided in an embodiment of this application. Please refer to... Figure 4 The type indicator has three pins. Pin 1 is used to connect to the P3V3_STBY signal line; pin 2 is used to connect to one end of the M2_TYPE_ID signal line, and the other end of the M2_TYPE_ID signal line is connected to the motherboard connector; pin 3 is used for grounding.

[0179] This type of indicator can be configured with a jumper cap, which, through different connection methods, causes the M2_TYPE_ID signal to output corresponding levels. When the jumper cap is connected to pins 1 and 2 (i.e., pins 1 and 2 are connected), the M2_TYPE_ID signal line outputs a high-level signal, which indicates that the protocol type is the first protocol type corresponding to the first signal; when the jumper cap is connected to pins 2 and 3 (i.e., pins 2 and 3 are connected), the M2_TYPE_ID signal line outputs a low-level signal, which indicates that the protocol type is the second protocol type corresponding to the second signal.

[0180] For example, when a SATA hard drive is inserted into the storage interface, the jumper cap of the type indicator is connected to pins 2 and 3, and the M2_TYPE_ID signal line outputs a low-level signal; when a PCIe hard drive is inserted, the jumper cap is connected to pins 1 and 2, and the M2_TYPE_ID signal line outputs a high-level signal.

[0181] In some embodiments, the storage device backplane 10 also includes a first power supply device.

[0182] In some embodiments, the type indicator is also connected to the storage interface; the type indicator is also used to: determine the protocol type of the storage device after the storage device is plugged into the storage interface, and switch the connection state of the first pin and the third pin according to the protocol type.

[0183] With the second pin normally connected to the motherboard connector, if the protocol type is the first protocol type, the type indicator can control the first pin to be normally connected to the pull-high power supply, and control the third pin to be in the off state. If the protocol type is the second protocol type, the type indicator can control the first pin to be in the off state, and control the third pin to be normally grounded.

[0184] After a storage device is plugged into the storage interface, the type indicator can detect the protocol type of the storage device by outputting different level signals from the protocol detection signal line between the storage device and the storage interface. Based on the protocol type, it can automatically switch the connection status of the first and third pins to ensure that the type indicator can output a type indication signal that matches the protocol type of the storage device, thus achieving adaptive compatibility between the storage device backplane and the storage device.

[0185] In some embodiments, the backplane of the storage device may also include a first power supply device.

[0186] Figure 5 For a second structural schematic diagram of the storage device backplane provided in the embodiments of this application, please refer to [link / reference]. Figure 5 ,exist Figure 2 Based on the structure of the storage device backplane shown, the storage device backplane 10 may further include a first power supply device 106. The first power supply device 106 is connected to the motherboard connector 101 and the protocol converter 103 respectively, and the motherboard connector 101 is used to connect to the motherboard 30.

[0187] The motherboard connector is also used to acquire a first enable signal output by the motherboard and to output a first enable signal to the first power supply device. The first enable signal can be used to indicate the enable of the protocol converter.

[0188] The first power supply device is used to supply power to the protocol converter according to the first enable signal.

[0189] Optionally, the first power supply device 106 can be connected to the motherboard connector 101 via an enable signal line, and the motherboard connector 101 can be connected to the controller on the motherboard via an enable signal line, thereby connecting the controller to the first power supply device 106.

[0190] The enable signal line is used to transmit a first enable signal. For example, this enable signal line can be the SATA_P3V3_ASM_EN signal line.

[0191] In some examples, when the storage device plugged into the storage interface is a SATA storage device, the controller pulls the first enable signal high (such as the SATA_P3V3_ASM_EN signal), and the first power supply device 106 provides operating power to the protocol converter; when the storage device plugged into the storage interface is a PCIe storage device, the controller pulls the first enable signal low (such as the SATA_P3V3_ASM_EN signal), and the first power supply device 106 cannot generate the relevant power supply required by the protocol converter.

[0192] Optionally, a controller may be provided in the motherboard, which can direct power to cable connector 1 on the motherboard (e.g., Figure 1 The cable connector 1 outputs a first enable signal, which can output the first enable signal to the motherboard connector.

[0193] The controller may include, but is not limited to, at least one of the following: BMC, Complex Programmable Logic Device (CPLD), Field-Programmable Gate Array (FPGA), or Microcontroller Unit (MCU).

[0194] In this storage device backplane, a separate first power supply device can be configured to power the protocol converter, thus differentiating the power supply of the protocol converter from that of other devices on the storage device backplane. This allows the storage device backplane to flexibly select the power supply mode according to different protocol types of storage devices, making its power supply method more flexible. Furthermore, when a storage device of the first protocol type is plugged into the storage interface of the storage device backplane, the storage device backplane does not need to power the protocol converter, which helps eliminate redundant power supply paths in the first protocol type storage device mode, reducing the energy consumption and circuit complexity of the storage device backplane in this mode.

[0195] In some embodiments, the structure of the storage device backplane can also be as follows: Figure 6 As shown. Figure 6 For the third schematic diagram of the structure of the storage device backplane provided in the embodiments of this application, please refer to [the following text is missing]. Figure 6 ,exist Figure 5 Based on the structure of the storage device backplane shown, the storage device backplane 10 may further include a second power supply device 107. The second power supply device 107 is connected to the motherboard connector 101 and the first power supply device 106, respectively.

[0196] The motherboard connector is also used to acquire the second enable signal and the first power supply signal output by the motherboard, and to output the second enable signal and the first power supply signal to the second power supply device. The second enable signal is used to indicate the output of the second power supply signal.

[0197] The second power supply device is used to convert the first power supply signal into a second power supply signal according to the second enable signal, and output the second power supply signal to the first power supply device; the voltage value of the second power supply signal is less than the voltage value of the first power supply signal.

[0198] For example, the second enable signal can be the P3V3_VR_EN signal, the first power supply signal can be the P12V_STBY signal, and the second power supply signal can be the P3V3 signal.

[0199] In some embodiments, the first power supply device may also be referred to as the "first power management device", and the second power supply device may also be referred to as the "second power management device".

[0200] In some embodiments, the storage device backplane and protocol converter may require operating power supplies with multiple voltage values. In such cases, the first power supply device and the second power supply device may include a power conversion device that can be used for voltage conversion processing.

[0201] Optionally, the first power supply device 106 may include a first power converter and a second power converter. The second power supply device 107 may further include a third power converter and a fourth power converter.

[0202] In this storage device backplane, the first power supply device can be connected to the second power supply device that powers the storage device backplane, eliminating the need for multiple power supply lines between the motherboard connector and the storage device backplane, thus reducing redundant power supply lines. Furthermore, the second and first enable signals can flexibly drive different power supply devices to distinguish different power supply modes of the storage device backplane (such as PCIe storage device power supply mode and SATA storage device power supply mode), making the power supply method of the storage device backplane more flexible.

[0203] Figure 7 For the fourth schematic diagram of the structure of the storage device backplane provided in the embodiments of this application, please refer to [the following text is missing]. Figure 7 ,exist Figure 6 Based on the structure of the storage device backplane shown, the first power supply device 106 may include a first power converter 1061 and a second power converter 1062, and the second power supply device 107 may also include a third power converter 1071 and a fourth power converter 1072.

[0204] like Figure 7 As shown, the first power converter 1061 is connected to the motherboard connector 101, the second power supply device 107, the second power converter 1062 and the protocol converter 103 respectively, and the second power converter 1062 is also connected to the protocol converter 103.

[0205] The third power converter 1071 is connected to the motherboard connector 101, the first power converter 1061 and the fourth power converter 1072 respectively.

[0206] Optionally, the first power converter 1061 can be connected to the motherboard connector 101 via an enable signal line, and the motherboard connector 101 can be connected to the controller on the motherboard via an enable signal line, thereby connecting the controller to the first power converter.

[0207] The first power converter is used to acquire a first enable signal and a second power supply signal, and convert the second power supply signal into a third power supply signal according to the first enable signal, and output the third power supply signal to the protocol converter and output the third enable signal to the second power converter; the voltage value of the third power supply signal is the same as the voltage value of the second power supply signal; the third enable signal is used to indicate the output of a fourth power supply signal, the voltage value of the fourth power supply signal is less than the voltage value of the second power supply signal.

[0208] The second power converter is used to output a fourth power supply signal to the protocol converter according to the third enable signal.

[0209] For example, the first enable signal can be the SATA_P3V3_protocol converter_EN signal, the second power supply signal can be the P3V3 signal, the third power supply signal can be the P3V3_protocol converter signal, the third enable signal can be the P1V05_protocol converter_EN signal, and the fourth power supply signal can be the P1V05_protocol converter signal.

[0210] By processing the second power supply signal through the first power converter, a third power supply signal with the same voltage value but a more stable signal can be obtained, thereby ensuring the stability of power supply to the protocol converter.

[0211] This application also provides an M.2 backplane design that is compatible with both SATA and PCIe protocols. This M.2 backplane design can be as follows: Figure 8 As shown.

[0212] Figure 8 This is a second schematic diagram of the M.2 backplate design provided in this application embodiment. Please refer to... Figure 8 ,and Figure 1 The design schemes for the M.2 backplate shown are different. Figure 8 The design of the M.2 backplane shown includes the addition of a path selector (SW), a type indicator, and VR4.

[0213] like Figure 8As shown, this M.2 backplane can support SATA M.2 storage devices, and it can transmit PCIe signals (such as PCIe_M2) output from cable connector 1. <0> The signal is converted into a SATA signal (such as SATA_M2) by the ASM1064 controller. <0> The signal is output to the SATA M.2 storage device through the M.2 interface.

[0214] This M.2 backplane supports PCIe M.2 storage devices and can output PCIe signals (such as PCIe_M2) from cable connector 1. <0> The signal is directly connected to the M.2 interface to output the PCIe signal to the PCIe M.2 storage device through the M.2 interface.

[0215] exist Figure 8 In the M.2 backplane design shown, a path selector (SW) is added between the PCIe signals directly connected to the M.2 interface and the PCIe signals connected to the ASM1064 controller to eliminate... Figure 1 The design scheme shown avoids the limitation of needing to replace the backplane due to protocol differences, achieving single-board compatibility with two protocols while avoiding redundant circuit design. This is achieved by changing the processing method of the M2_TYPE_ID signal to a jumper cap, enabling dynamic switching and identification of the M2_TYPE_ID signal. By adding VR4, the M.2 backplane can distinguish the power supply mode of different M.2 storage device modes; for example, it can differentiate between the power supply modes under SATA (SATA mode) and PCIe (NVMe mode). This design integrates SATA M.2 and PCIe M.2 backplanes, reducing R&D investment and improving the usability and compatibility of M.2 backplanes. When switching from one type of M.2 storage device (such as a SATA M.2 hard drive) to another type (such as a PCIe M.2 hard drive), there is no need to replace the M.2 backplane; flexible switching of signal transmission channels between the two types of M.2 storage devices can be achieved using the same M.2 backplane.

[0216] exist Figure 8 In the design scheme of the M.2 backplane shown, the M.2 backplane no longer supports different types of storage devices (such as hard drives) by whether certain electronic components are installed. Instead, it uses an M.2 backplane with the same BOM to support both SATA M.2 storage devices and PCIe M.2 storage devices.

[0217] exist Figure 8In the M.2 backplane design shown, the PCIe_M2 slot is interconnected with the processor (such as the CPU) on the motherboard. <0> The signal line is split into two paths after passing through the path selector (SW) and connected to the M.2 interface. One path connects to the ASM1064 controller and then to the M.2 interface via the ASM1064 controller; the other path connects directly to the M.2 interface. The function of the ASM1064 controller is to convert the PCIe signal (PCIe_M2) into two paths. <0> The signal is converted to a SATA signal (SATA_M2). <0> After receiving the signal, it communicates with the SATA M.2 storage device plugged into the M.2 interface via the SATA signal.

[0218] When the controller on the motherboard (such as the BMC) detects that the storage device inserted into the M.2 interface is a SATA M.2 storage device via the type indication signal (M2_TYPE_ID signal), the controller sets the selection signal to a low level, outputting a low-level selection signal from cable connector 1 to cable connector 2. Cable connector 2 then outputs this low-level selection signal to the path selector (SW). Based on this low-level selection signal, the path selector (SW) outputs PCIe_M2 to the ASM1064 controller. <0> The ASM1064 controller will send PCIe_M2 signals. <0> Signal converted to SATA_M2 <0> The signal is then output to the M.2 interface as SATA_M2. <0> This signal enables the controllers on the motherboard to respond based on the SATA_M2 signal. <0> The signal communicates with the SATA M.2 storage device.

[0219] When the controller on the motherboard (such as the BMC) detects that the storage device inserted into the M.2 interface is a PCIe M.2 storage device via the type indication signal (M2_TYPE_ID signal), the controller sets the selection signal to a high level, outputting a high-level selection signal from cable connector 1 to cable connector 2. Cable connector 2 then outputs this high-level selection signal to the path selector (SW). Based on this high-level selection signal, the path selector (SW) outputs PCIe_M2 to the M.2 interface. <0> This signal enables the controllers on the motherboard to respond based on the PCIe_M2 signal. <0> Communicate with the PCIe M.2 storage device.

[0220] exist Figure 8 In the M.2 backplane design shown, the type indicator signal can be handled via a jumper connection instead of using a pull-down resistor to indicate the type of M.2 storage device supported by the backplane. For example... Figure 8As shown, the type indicator includes three pins. The top pin 1 is used to connect to the P3V3_STBY signal line; the middle pin 2 is used to connect to the controller (such as BMC) on the motherboard via the M2_TYPE_ID signal line. The M2_TYPE_ID signal line is used to transmit a type indication signal to the controller, which tells the controller whether the currently supported M.2 storage device is a SATA M.2 storage device or a PCIe M.2 storage device; the bottom pin 3 is used for grounding.

[0221] When the selected M.2 storage device is a SATA M.2 storage device, connect the jumper to pins 2 and 3. The M2_TYPE_ID signal will then be low, notifying the controller (e.g., BMC) that this storage device is a SATA M.2 storage device. When the selected M.2 storage device is a PCIe M.2 storage device, connect the jumper to pins 1 and 2. The M2_TYPE_ID signal will then be high, notifying the controller (e.g., BMC) that this storage device is a PCIe M.2 storage device. Therefore, in this solution, when replacing an M.2 storage device, there is no need to change the BOM; simply adjusting the jumper position ensures that the M.2 backplane is compatible with the replaced M.2 storage device.

[0222] exist Figure 8 In the M.2 backplane design shown, the power supply scheme differs depending on the type of M.2 storage device it supports. When the M.2 storage device is a PCIe M.2 storage device, the ASM1064 controller does not need to operate and does not need to provide power support for SATA-related signals. Therefore, when the M.2 backplane needs to support PCIe M.2 storage devices, there is no need to power the P3V3_ASM and P1V05_ASM signal lines on the board.

[0223] exist Figure 8 The M.2 backplane design shown includes a voltage regulator (or "power manager") VR4 and an enable signal line (SATA_P3V3_ASM_EN signal line). The VR4 enable signal line (SATA_P3V3_ASM_EN) is connected to the motherboard controller (such as the BMC). When the selected M.2 storage device is a SATA M.2 storage device, the controller pulls the SATA_P3V3_ASM_EN signal high, and VR4 generates P3V3_ASM power and P1V05_ASM power to supply power to the ASM1064 controller. When the selected M.2 storage device is a PCIe M.2 storage device, the controller on the motherboard pulls the SATA_P3V3_ASM_EN signal low, and VR4 on the board cannot generate the necessary power for the ASM1064 controller.

[0224] In summary, the M.2 backplane design provided in this application embodiment is feasible. This M.2 backplane can achieve bidirectional compatibility with M.2 storage devices using both SATA and PCIe protocols. It has good hardware compatibility and helps reduce operational complexity and thus lower operational costs.

[0225] This application also provides a device control method, which can be interactively executed by a controller on the backplane of a storage device and the motherboard. The following, in conjunction with... Figures 9-11 The control method for this equipment will be explained.

[0226] Figure 9 This is one of the flowcharts illustrating the device control method provided in this application. Please refer to... Figure 9 This method can be interactively executed by the controller on the storage device backplane and the motherboard in the above embodiments, and the method specifically includes the following steps:

[0227] S901, The storage device backplane sends a type indication signal to the controller.

[0228] Correspondingly, the storage device backplane can receive a type indication signal sent by the controller. The storage device backplane can send this type indication signal to the controller via the motherboard connector and cable connector 1 in the motherboard.

[0229] The type indicator signal is used to indicate the protocol type of the storage device, which is inserted into the storage device backplane and connected to the motherboard.

[0230] In some embodiments, the storage device backplane may send a high-level signal to the controller; or, the storage device backplane may send a low-level signal to the controller.

[0231] Correspondingly, the controller can receive a high-level signal sent by the storage device backplane; or, the controller can receive a low-level signal sent by the storage device backplane.

[0232] A high-level signal is used to indicate the first protocol type corresponding to the first signal, and a low-level signal is used to indicate the second protocol type corresponding to the second signal; wherein, the voltage value of the high-level signal is higher than the voltage value of the low-level signal.

[0233] It should be noted that the content of the type indicator signal in this step can be referred to the content of the type indicator signal in the above embodiment, and will not be repeated here.

[0234] S902, The controller sends a selection signal to the backplane of the storage device.

[0235] Correspondingly, the storage device backplane can obtain the selection signal sent by the controller and the first signal output by the motherboard.

[0236] The selection signal can be determined based on the protocol type.

[0237] It should be noted that the content of the selected signal in this step can refer to the content of the selected signal in the above embodiment, and will not be repeated here.

[0238] The selection signal can be used to instruct the storage device backplane to output the first signal output by the motherboard to the storage device; or, the selection signal can be used to instruct the storage device backplane to convert the first signal into a second signal that matches the protocol type and output the second signal to the storage device.

[0239] S903. The storage device backplane outputs a first signal to the storage device according to the selection signal, or converts the first signal into a second signal that matches the protocol type and outputs the second signal to the storage device.

[0240] The storage device backplane can receive the selection signal sent by the controller and the first signal output by the motherboard through the motherboard connector, and output the selection signal and the first signal to the path selector through the motherboard connector. The storage device backplane can then use the path selector to allocate the first signal to the storage interface or the protocol converter based on the selection signal. If the first signal is allocated to the protocol converter, the storage device backplane can also convert the first signal into a second signal matching the protocol type through the protocol converter, and transmit the second signal output by the protocol converter to the storage device through the storage interface.

[0241] The device control method provided in this application embodiment allows the storage device backplane to send a type indication signal to the controller after the storage device is plugged into the storage interface of the storage device backplane. This type indication signal informs the controller of the protocol type of the storage device currently plugged into the storage interface. The controller can also send a selection signal to the storage device backplane, causing the backplane to either directly send a first signal output from the motherboard to the storage device, or send a second signal obtained by protocol conversion of the first signal to the storage device. Through the interaction between the storage device backplane and the controller, adaptive adaptation between the backplane and the storage device can be achieved, effectively improving the protocol compatibility and flexibility of the storage device backplane, and reducing hardware deployment and maintenance costs in multi-protocol storage scenarios.

[0242] In some embodiments, if the protocol type of the storage device is the first protocol type corresponding to the first signal, the device control method may be as follows: Figure 10 As shown.

[0243] Figure 10 This is a second schematic flowchart illustrating the device control method provided in this application. Please refer to [link / reference]. Figure 10This method can be interactively executed by the controller on the storage device backplane and the motherboard in the above embodiments, and the method specifically includes the following steps:

[0244] S1001, The storage device backplane sends a type indication signal to the controller.

[0245] In this step, the type indication signal is used to indicate that the protocol type of the storage device is the first protocol type corresponding to the first signal (such as the PCIe protocol). This type indication signal can be a high-level signal.

[0246] S1002, The controller sends a selection signal to the backplane of the storage device.

[0247] Correspondingly, the storage device backplane can acquire the selection signal sent by the controller and the first signal output by the motherboard.

[0248] In this step, the selection signal can be determined according to the first protocol type, and the selection signal can be used to instruct the storage device backplane to output the first signal from the storage device motherboard.

[0249] S1003. The storage device backplane outputs a first signal to the storage device according to the selection signal.

[0250] In this step, the storage device backplane does not need to perform protocol conversion processing on the first signal.

[0251] The storage device backplane provided in this application embodiment, when the protocol type is the first protocol type, does not require enabling the protocol converter used for protocol conversion processing and the power supply device related to the second signal, which helps to save the power consumption and power supply complexity of the storage device.

[0252] In some embodiments, if the protocol type of the storage device is the second protocol type corresponding to the second signal, the device control method may be as follows: Figure 11 As shown.

[0253] Figure 11 This is the third schematic flowchart illustrating the device control method provided in this application. Please refer to... Figure 11 This method can be interactively executed by the controller on the storage device backplane and the motherboard in the above embodiments, and the method specifically includes the following steps:

[0254] S1101, The storage device backplane sends a type indication signal to the controller.

[0255] In this step, the type indicator signal is used to indicate that the protocol type of the storage device is the second protocol type corresponding to the second signal (such as the SATA protocol). This type indicator signal can be a low-level signal.

[0256] S1102. When the protocol type is the second protocol type, the controller sends a first enable signal to the storage device backplane.

[0257] Correspondingly, the storage device backplane can receive a first enable signal sent by the controller, which is used to instruct the protocol converter to be enabled.

[0258] The storage device backplane includes the protocol converter, which can be used to convert the first signal into a second signal.

[0259] It should be noted that the content of the first enable signal in this step can be referred to the content of the first enable signal in the above embodiment, and will not be repeated here.

[0260] S1103, The storage device backplane supplies power to the protocol converter according to the first enable signal.

[0261] The backplane of the storage device may include a first power supply device, which can provide operating power to the protocol converter according to a first enable signal, so as to enable the protocol converter.

[0262] S1104, The controller sends a selection signal to the backplane of the storage device.

[0263] Correspondingly, the storage device backplane can acquire the selection signal sent by the controller and the first signal output by the motherboard.

[0264] S1105. The storage device backplane converts the first signal into a second signal that matches the protocol type and outputs the second signal to the storage device.

[0265] In this step, the storage device backplane needs to transmit the first signal to the protocol converter through the path selector, and the protocol converter performs protocol conversion processing on the first signal in order to output a second signal with protocol type adaptation to the storage device through the storage interface.

[0266] The storage device backplane provided in this application embodiment, when the protocol type is the second protocol type, can enable the protocol converter used for protocol conversion processing and the power supply device related to the second signal, so that the protocol converter can work normally and perform protocol conversion processing on the first signal. Thus, the storage device backplane can output a second signal that is compatible with the protocol type to the storage device, ensuring that each device in the motherboard can communicate normally with the storage device based on the second signal.

[0267] This application also provides a device control apparatus that can be applied to a controller.

[0268] Figure 12 This is a schematic diagram of the structure of the device control apparatus provided in an embodiment of this application. Please refer to... Figure 12 The equipment control device 1200 may include:

[0269] Transceiver module 1201 is used to receive type indication signal sent by storage device backplane; the type indication signal is used to indicate the protocol type of storage device, storage device is inserted in storage device backplane, storage device backplane is connected to motherboard;

[0270] The transceiver module 1201 is also used to send a selection signal to the storage device backplane; the selection signal is determined according to the protocol type; the selection signal is used to instruct the storage device backplane to output the first signal output by the motherboard to the storage device, or to instruct the storage device backplane to convert the first signal into a second signal that matches the protocol type and output the second signal to the storage device.

[0271] In one possible implementation, the transceiver module 1201 is specifically used for:

[0272] Receive a high-level signal sent from the backplane of the storage device, the high-level signal indicating that the protocol type is the first protocol type corresponding to the first signal; or...

[0273] Receive a low-level signal sent by the backplane of the storage device. The low-level signal is used to indicate that the protocol type is the second protocol type corresponding to the second signal.

[0274] The voltage value of the high-level signal is higher than that of the low-level signal.

[0275] In one possible implementation, the storage device backplane includes a protocol converter for converting a first signal into a second signal; the transceiver module 1201 is further configured to:

[0276] When the protocol type is the second protocol type, a first enable signal is sent to the storage device backplane; the first enable signal is used to indicate that the protocol converter is enabled.

[0277] For a description of the features in the embodiment corresponding to the device control apparatus, please refer to the relevant description in the embodiment corresponding to the device control method, which will not be repeated here.

[0278] Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Please refer to... Figure 13 The electronic device 1300 includes a storage device backplane 10 and a motherboard 30. The storage device backplane 10 is connected to the motherboard 30, and a controller 301 is provided on the motherboard 30.

[0279] The storage device backplane 10 is used to implement the method implemented by the storage device backplane in the above embodiments; the controller 301 is used to implement the method implemented by the controller in the above embodiments.

[0280] It should be noted that the structure of the storage device backplane can refer to the structure of the storage device backplane in the above embodiments, and will not be described again here.

[0281] Optionally, the motherboard 30 may include Figure 1 The cable connector 1 shown can be connected to the motherboard connector 101 and the controller 301 respectively.

[0282] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when it is run.

[0283] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0284] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0285] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0286] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0287] The foregoing has provided a detailed description of the storage device backplane, device control method, apparatus, and device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the methods and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A storage device backplane, characterized in that, The system includes a motherboard connector, a protocol converter, a path selector, a storage interface, and a type indicator. The motherboard connector connects to the storage interface via various types of signal lines, one of which is the PCIe signal line. The protocol converter is connected to the motherboard connector, the path selector, and the storage interface. The path selector is also connected to the motherboard connector and the storage interface. The type indicator is connected to the motherboard connector. The motherboard connector is connected to the protocol converter via a signal line corresponding to a first signal, a signal line providing a reference clock signal to the protocol converter, and a reset signal line. The motherboard connector is used to obtain the protocol type of the storage device inserted on the storage interface from the type indicator, indicate the protocol type to the motherboard, obtain the selection signal and the first signal output by the motherboard, and output the first signal and the selection signal to the path selector; the path selector is a single-chip gating device, and the path selector selectively conducts hardware modules of different circuit paths through the selection signal. The path selector is used to allocate the first signal to the storage interface or the protocol converter according to the selection signal; wherein, when the protocol type is a first protocol type, the first signal is allocated to the storage interface, and when the protocol type is a second protocol type, the first signal is allocated to the protocol converter. The protocol converter is used to convert the first signal into a second signal that matches the protocol type, and output the second signal to the storage interface; The storage device backplane also includes a first power supply device, which is connected to the motherboard connector and the protocol converter respectively. The motherboard connector is used to connect to the motherboard. The motherboard connector is also used to acquire a first enable signal output by the motherboard and output the first enable signal to the first power supply device. The first enable signal is used to indicate that the protocol converter is enabled. The first enable signal is generated when the protocol type is determined to be a second protocol type. The storage device backplane also includes a second power supply device, which is connected to the motherboard connector and the first power supply device respectively. The motherboard connector is further configured to acquire a second enable signal and a first power supply signal output by the motherboard, and output the second enable signal and the first power supply signal to the second power supply device. The second enable signal is used to indicate the output of the second power supply signal. The second power supply device is configured to convert the first power supply signal into the second power supply signal according to the second enable signal, and output the second power supply signal to the first power supply device. The voltage value of the second power supply signal is less than the voltage value of the first power supply signal. The first power supply device includes a first power converter and a second power converter. The first power converter is connected to the motherboard connector, the second power supply device, the second power converter, and the protocol converter, respectively. The second power converter is also connected to the protocol converter. The first power converter is used to acquire a first enable signal and a second power supply signal, and convert the second power supply signal into a third power supply signal according to the first enable signal, and output the third power supply signal to the protocol converter and output a third enable signal to the second power converter. The voltage value of the third power supply signal is the same as the voltage value of the second power supply signal. The third enable signal is used to indicate the output of a fourth power supply signal, the voltage value of which is less than the voltage value of the second power supply signal. The second power converter is used to output the fourth power supply signal to the protocol converter according to the third enable signal. The backplane also includes: software-simulated I2C, an I2C bus level conversion module, a field-replaceable unit (FRU), and a sensor; the motherboard connector is connected to the software-simulated I2C via the RST_M2_9546_N signal line and the BMC_I2C signal line, the software-simulated I2C is connected to the field-replaceable unit (FRU) and the sensor via the SMB_SW_I2C signal line, and is connected to the I2C bus level conversion module via the SW_I2C_M2 signal line.

2. The storage device backplane according to claim 1, characterized in that, The type indicator includes a first pin, a second pin, and a third pin, wherein, The first pin is used to connect to a pull-high power supply, which provides a high-level signal to the type indicator; The second pin is connected to the motherboard connector; The third pin is used for grounding.

3. The storage device backplane according to claim 2, characterized in that, The type indicator is specifically used for: Based on the connection status of the first pin, the second pin, and the third pin, a type indication signal is output to the motherboard connector; Wherein, the type indication signal is used to indicate the protocol type; the type indication signal is a high-level signal or a low-level signal, the voltage value of the high-level signal is higher than the voltage value of the low-level signal; the high-level signal is used to indicate that the protocol type is the first protocol type corresponding to the first signal, and the low-level signal is used to indicate that the protocol type is the second protocol type corresponding to the second signal.

4. The storage device backplane according to claim 3, characterized in that, The type indicator also includes a jumper cap configured to selectively connect two pins of the type indicator to switch the circuit on / off state; the type indicator is further specifically used for: If the jumper cap is connected to both the first and second pins, a high-level signal is output to the motherboard connector; or... If the jumper cap is connected to the second pin and the third pin, the low-level signal is output to the motherboard connector.

5. The storage device backplane according to any one of claims 2-4, characterized in that, The type indicator is also connected to the storage interface; the type indicator is also used for: After the storage device is plugged into the storage interface, the protocol type of the storage device is determined, and the connection status of the first pin and the third pin is switched according to the protocol type.

6. The storage device backplane according to any one of claims 1-4, characterized in that, The motherboard connector is used to connect to the motherboard, which has a controller mounted on it; the motherboard connector is specifically used for: Obtain the type indication signal output by the type indicator and send the type indication signal to the controller; Wherein, the type indication signal is used to indicate the protocol type; the type indication signal is a high-level signal or a low-level signal, the voltage value of the high-level signal is higher than the voltage value of the low-level signal; the high-level signal is used to indicate that the protocol type is the first protocol type corresponding to the first signal, and the low-level signal is used to indicate that the protocol type is the second protocol type corresponding to the second signal.

7. The storage device backplane according to any one of claims 1-4, characterized in that, The path selector includes a signal input pin and a signal output pin, wherein, The signal input pins include: a first signal input pin for receiving the selection signal, a second signal input pin for receiving the output signal of the motherboard connector, a third signal input pin for receiving the output signal of the protocol converter, and a fourth signal input pin for receiving the output signal of the storage interface; The signal output pins include: a first signal output pin for outputting signals to the motherboard connector, a second signal output pin for outputting signals to the protocol converter, and a third signal pin for outputting signals to the storage interface.

8. A device control method, characterized in that, The method includes: A type indication signal is sent to the controller on the motherboard via the motherboard connector. This type indication signal indicates the protocol type of the storage device, which is inserted into a storage device backplane connected to the motherboard. The storage device backplane includes a motherboard connector, a protocol converter, a path selector, a storage interface, and a type indicator. The motherboard connector is connected to the storage interface via multiple types of signal lines, one of which is a PCIe signal line. The motherboard connector is connected to the protocol converter via a signal line corresponding to a first signal, a signal line providing a reference clock signal to the protocol converter, and a reset signal line. The backplane also includes: a software-simulated I2C, an I2C bus level conversion module, a field-replaceable unit (FRU), and a sensor. The motherboard connector is connected to the software-simulated I2C via the RST_M2_9546_N and BMC_I2C signal lines. The software-simulated I2C is connected to the field-replaceable unit (FRU) and the sensor via the SMB_SW_I2C signal line, and to the I2C bus level conversion module via the SW_I2C_M2 signal line. The system acquires a selection signal sent by the controller and a first signal output by the motherboard; the selection signal is determined according to the protocol type. According to the selection signal, when the protocol type is a first protocol type, the first signal is output to the storage device; or when the protocol type is a second protocol type, the first signal is allocated to the protocol converter through the path selector. The protocol converter converts the first signal into a second signal matching the protocol type and outputs the second signal to the storage device. The path selector is a single-chip gating device, and the path selector is a hardware module that selectively conducts different circuit paths through the selection signal. The method further includes: The first enable signal sent by the controller is obtained through the motherboard connector, and the first enable signal is output to the first power supply device on the backplane of the storage device; the first enable signal is used to indicate that the protocol converter is enabled, and the first enable signal is generated when the protocol type is determined to be the second protocol type; power is supplied to the protocol converter according to the first enable signal; The second enable signal and the first power supply signal output by the motherboard are obtained through the motherboard connector, and the second enable signal and the first power supply signal are output to the second power supply device of the storage device backplane. The second enable signal is used to indicate the output of the second power supply signal. The second power supply device is used to convert the first power supply signal into the second power supply signal according to the second enable signal, and output the second power supply signal to the first power supply device. The voltage value of the second power supply signal is less than the voltage value of the first power supply signal. The first power supply device includes a first power converter and a second power converter. The first power converter is connected to the motherboard connector, the second power supply device, the second power converter, and the protocol converter, respectively. The second power converter is also connected to the protocol converter. The first power converter is used to acquire a first enable signal and a second power supply signal, and convert the second power supply signal into a third power supply signal according to the first enable signal, and output the third power supply signal to the protocol converter and output a third enable signal to the second power converter. The voltage value of the third power supply signal is the same as the voltage value of the second power supply signal. The third enable signal is used to indicate the output of a fourth power supply signal, the voltage value of which is less than the voltage value of the second power supply signal. The second power converter is used to output the fourth power supply signal to the protocol converter according to the third enable signal.

9. A device control method, characterized in that, The method includes: The system receives a type indication signal sent by the storage device backplane through the motherboard connector. The type indication signal indicates the protocol type of the storage device, which is inserted into the storage device backplane and connected to the motherboard. The storage device backplane includes a motherboard connector, a protocol converter, a path selector, a storage interface, and a type indicator. The motherboard connector is connected to the storage interface via multiple types of signal lines, one of which is a PCIe signal line. The motherboard connector is connected to the protocol converter via a signal line corresponding to a first signal, a signal line providing a reference clock signal to the protocol converter, and a reset signal line. The backplane also includes: a software-simulated I2C, an I2C bus level conversion module, a field-replaceable unit (FRU), and a sensor. The motherboard connector is connected to the software-simulated I2C via the RST_M2_9546_N and BMC_I2C signal lines. The software-simulated I2C is connected to the field-replaceable unit (FRU) and the sensor via the SMB_SW_I2C signal line, and to the I2C bus level conversion module via the SW_I2C_M2 signal line. A selection signal is sent to the backplane of the storage device; the selection signal is determined according to the protocol type; the selection signal is used to instruct the backplane of the storage device to output a first signal output by the motherboard to the storage device when the protocol type is a first protocol type, or to instruct the backplane of the storage device to allocate the first signal to the protocol converter through the path selector when the protocol type is a second protocol type, the protocol converter converts the first signal into a second signal matching the protocol type, and outputs the second signal to the storage device; the path selector is a single-chip gating device, and the path selector is a hardware module that selectively conducts different circuit paths through the selection signal; The storage device backplane includes a protocol converter, which is used to convert the first signal into the second signal; the method further includes: When the protocol type is the second protocol type, a first enable signal is sent to the motherboard connector of the storage device backplane, so that the motherboard connector outputs the first enable signal to the first power supply device of the storage device backplane; the first enable signal is used to indicate that the protocol converter is enabled. The method further includes: A second enable signal and a first power supply signal are sent to the motherboard connector, causing the motherboard connector to output the second enable signal and the first power supply signal to a second power supply device on the backplane of the storage device. The second enable signal is used to indicate the output of the second power supply signal. The second power supply device is used to convert the first power supply signal into the second power supply signal according to the second enable signal and output the second power supply signal to the first power supply device. The voltage value of the second power supply signal is less than the voltage value of the first power supply signal. The first power supply device includes a first power converter and a second power converter. The first power converter is connected to the motherboard connector, the second power supply device, the second power converter, and the protocol converter, respectively. The second power converter is also connected to the protocol converter. The first power converter is used to acquire a first enable signal and a second power supply signal, and convert the second power supply signal into a third power supply signal according to the first enable signal, and output the third power supply signal to the protocol converter and output a third enable signal to the second power converter. The voltage value of the third power supply signal is the same as the voltage value of the second power supply signal. The third enable signal is used to indicate the output of a fourth power supply signal, the voltage value of which is less than the voltage value of the second power supply signal. The second power converter is used to output the fourth power supply signal to the protocol converter according to the third enable signal.

10. The method according to claim 9, characterized in that, Receive type indication signals sent by the storage device backplane, including: Receive a high-level signal sent by the backplane of the storage device, the high-level signal being used to indicate that the protocol type is the first protocol type corresponding to the first signal; or... Receive a low-level signal sent by the backplane of the storage device, the low-level signal being used to indicate that the protocol type is the second protocol type corresponding to the second signal; The voltage value of the high-level signal is higher than the voltage value of the low-level signal.

11. A device control apparatus, characterized in that, include: The transceiver module is used to receive type indication signals sent by the storage device backplane through the motherboard connector; The type indicator signal is used to indicate the protocol type of the storage device, which is inserted into a storage device backplane connected to the motherboard. The storage device backplane includes a motherboard connector, a protocol converter, a path selector, a storage interface, and a type indicator. The motherboard connector is connected to the storage interface via multiple types of signal lines, one of which is a PCIe signal line. The motherboard connector is connected to the protocol converter via a signal line corresponding to a first signal, a signal line providing a reference clock signal to the protocol converter, and a reset signal line. The backplane also includes: a software-simulated I2C, an I2C bus level conversion module, a field-replaceable unit (FRU), and a sensor. The motherboard connector is connected to the software-simulated I2C via the RST_M2_9546_N and BMC_I2C signal lines. The software-simulated I2C is connected to the field-replaceable unit (FRU) and the sensor via the SMB_SW_I2C signal line, and to the I2C bus level conversion module via the SW_I2C_M2 signal line. The transceiver module is further configured to send a selection signal to the storage device backplane; the selection signal is determined according to the protocol type; the selection signal is used to instruct the storage device backplane to output the first signal output by the motherboard to the storage device when the protocol type is a first protocol type, or to instruct the storage device backplane to allocate the first signal to the protocol converter through the path selector when the protocol type is a second protocol type, the protocol converter converts the first signal into a second signal matching the protocol type, and outputs the second signal to the storage device; the path selector is a single-chip gating device, and the path selector is a hardware module that selectively conducts different circuit paths through the selection signal; The storage device backplane includes a protocol converter, which is used to convert the first signal into the second signal; the transceiver module is further used for: When the protocol type is the second protocol type, a first enable signal is sent to the motherboard connector of the storage device backplane, so that the motherboard connector outputs the first enable signal to the first power supply device of the storage device backplane; the first enable signal is used to indicate that the protocol converter is enabled. The device is also used for: A second enable signal and a first power supply signal are sent to the motherboard connector, causing the motherboard connector to output the second enable signal and the first power supply signal to a second power supply device on the backplane of the storage device. The second enable signal is used to indicate the output of the second power supply signal. The second power supply device is used to convert the first power supply signal into the second power supply signal according to the second enable signal and output the second power supply signal to the first power supply device. The voltage value of the second power supply signal is less than the voltage value of the first power supply signal. The first power supply device includes a first power converter and a second power converter. The first power converter is connected to the motherboard connector, the second power supply device, the second power converter, and the protocol converter, respectively. The second power converter is also connected to the protocol converter. The first power converter is used to acquire a first enable signal and a second power supply signal, and convert the second power supply signal into a third power supply signal according to the first enable signal, and output the third power supply signal to the protocol converter and output a third enable signal to the second power converter. The voltage value of the third power supply signal is the same as the voltage value of the second power supply signal. The third enable signal is used to indicate the output of a fourth power supply signal, the voltage value of which is less than the voltage value of the second power supply signal. The second power converter is used to output the fourth power supply signal to the protocol converter according to the third enable signal.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the method as described in claim 9 or 10.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 9 or 10.

14. An electronic device, characterized in that, Includes a storage device backplane and a motherboard as described in any one of claims 1-7, wherein the storage device backplane is connected to the motherboard, and a controller is disposed on the motherboard, wherein... The storage device backplane is used to implement the method as described in claim 8; The controller is used to implement the method as described in claim 9 or 10.

Images