Multi-link synchronization control circuit, method, timing controller and display device

Abstract

The application belongs to the technical field of display, and particularly relates to a multi-link synchronous control circuit, a method, a timing controller and a display device. The multi-link synchronous control circuit comprises a signal receiving module configured to receive control signals from at least two independent links; a synchronization judgment module connected with the signal receiving module and configured to detect synchronization states of the at least two control signals; and a channel control module connected with the synchronization judgment module. The synchronization judgment module is further configured to send an enable signal to the channel control module when it is detected that all the control signals reach a preset threshold. The channel control module is configured to establish transmission channels of all the control signals to their respective control targets in response to the enable signal. The application can ensure synchronization of link signals.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a multi-link synchronous control circuit, method, timing controller, and display device. Background Technology

[0002] As display technology upgrades towards higher resolution and refresh rates, traditional display interfaces are gradually being replaced by mainstream high-speed interfaces due to their limited transmission capabilities. To adapt to higher transmission demands, a multi-link architecture is often adopted, using multiple links working in parallel to improve overall transmission capacity, with each link corresponding to an independent signal processing unit. However, multi-link architectures suffer from asynchronous signals between links, leading to system logic anomalies and causing signal transmission failures or display malfunctions. Summary of the Invention

[0003] The purpose of this application is to solve the problem of asynchronous signals between links in multi-link architectures in related technologies, which leads to abnormal system logic, signal transmission failures, or display anomalies.

[0004] A first aspect of this application provides a multi-link synchronization control circuit, comprising: a signal receiving module configured to receive control signals from at least two independent links; a synchronization decision module connected to the signal receiving module and configured to perform synchronization state detection on the at least two control signals; and a path control module connected to the synchronization decision module; wherein the synchronization decision module is further configured to: when all the control signals are detected to have reached a preset threshold, send an enable signal to the path control module; and the path control module is configured to: in response to the enable signal, establish a transmission channel for all the control signals to their respective control targets.

[0005] In one exemplary embodiment of this application, the synchronization decision module includes a level detection unit and a logic generation unit; the level detection unit is configured to detect the level value of each of the control signals; the logic generation unit is configured to compare each of the level values ​​with a preset threshold and generate the enable signal based on the comparison result.

[0006] In one exemplary embodiment of this application, the path control module includes a plurality of controlled switch units, each of which is connected in series on the transmission path of the control signal; the control terminals of each of the controlled switch units jointly receive the enable signal and are configured to synchronously turn on when the enable signal is received.

[0007] In one exemplary embodiment of this application, the multi-link synchronization control circuit further includes a mode management module, which is communicatively connected to the signal receiving module and the path control module and is configured to detect the status of each control signal; the mode management module is further configured to: when a predetermined mode condition is detected to be met, overwrite the output of the synchronization decision module and control the path control module to establish a transmission channel for part of the control signals.

[0008] In one exemplary embodiment of this application, the predetermined mode conditions include: a first control signal reaching the preset threshold, and a second control signal maintaining a flag level below the preset threshold.

[0009] In one exemplary embodiment of this application, the mode management module includes a signal analysis unit and an instruction overwrite unit; the signal analysis unit is configured to identify the flag level; the instruction overwrite unit is configured to output a selective conduction instruction to the path control module when the flag level is identified, so as to block the transmission channel corresponding to the link that maintains the flag level.

[0010] In one exemplary embodiment of this application, the control target includes a signal processing unit, a power management module, an interface circuit, a display driver circuit, or a physical layer circuit in a display timing controller in an electronic device.

[0011] A second aspect of this application provides a multi-link data synchronization control method, the method comprising: receiving control signals from at least two independent links; performing a synchronization state determination on the at least two control signals; generating and sending an enable signal when it is confirmed that all the control signals have reached a preset threshold; and, in response to the enable signal, establishing a synchronization transmission channel for all the control signals to their respective control targets.

[0012] A third aspect of this application provides a timing controller that integrates a multi-link synchronization control circuit as described in any of the preceding claims.

[0013] A fourth aspect of this application provides a display device, comprising: a display panel; and a timing controller as described above, the timing controller being connected to the display panel.

[0014] The multi-link synchronous control circuit, method, timing controller, and display device proposed in this application have at least the following beneficial effects: The multi-link synchronous control circuit of this application uses a synchronization decision module to uniformly detect the level status of signals in each link. An enable signal is only output when all signals reach a preset threshold, achieving timing synchronization of multi-link signals at the hardware level and avoiding control system logic errors caused by signal timing deviations. Simultaneously, the path control module responds to the enable signal by transmitting each link signal to its corresponding control target. This directional transmission mechanism prevents cross-link signal misflow, reduces mutual interference between different link signals, and significantly improves the accuracy and reliability of system signal transmission.

[0015] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 Block diagrams of multi-link synchronization control circuits in some embodiments are shown.

[0019] Figure 2 A schematic diagram of the structure of a multi-link synchronization control circuit in some embodiments is shown.

[0020] Figure 3 A schematic diagram of a mode management module is shown in some embodiments of a multi-link synchronization control circuit.

[0021] Figure 4 A flowchart illustrating a multi-link data synchronization control method in some embodiments is shown.

[0022] Figure 5 The diagram shows a schematic of the connection between the system-on-a-chip and the timing controller in some embodiments.

[0023] Explanation of reference numerals in the attached figures: 10. Display device; 100. Multi-link synchronization control circuit; 110. Signal receiving module; 111. First input terminal; 112. Second input terminal; 120. Synchronization decision module; 121. Level detection unit; T1. First switching element; T2. Second switching element; 130. Path control module; T3. Third switching element; T4. Fourth switching element; 140. Mode management module; Q1. Fifth switching element; Q2. Sixth switching element; 200. Timing controller; 300. Display panel; VCC, power signal; pwr0, first control signal; pwr1, second control signal; phy0, master physical layer; phy1, slave physical layer; A, first node; B, second node. Detailed Implementation

[0024] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0025] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0027] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0028] Example 1 See Figure 1 and Figure 2 As shown, this application embodiment provides a multi-link synchronization control circuit 100, which may include a signal receiving module 110, a synchronization decision module 120, and a path control module 130. The signal receiving module 110 is configured to receive control signals from at least two independent links. The synchronization decision module 120 is connected to the signal receiving module 110 and is configured to perform synchronization status detection on at least two control signals. The path control module 130 is connected to the synchronization decision module 120.

[0029] The synchronization decision module 120 is further configured to send an enable signal to the path control module 130 when it detects that all control signals have reached a preset threshold. The path control module 130 can respond to the enable signal to establish a transmission channel for all control signals to their respective control targets.

[0030] This application uses a synchronization decision module 120 to uniformly detect the level status of signals on each link. An enable signal is only output when all signals reach a preset threshold, achieving timing synchronization of multiple link signals at the hardware level and avoiding control system logic errors caused by signal timing deviations. Simultaneously, the path control module 130 responds to the enable signal by transmitting each link signal to its corresponding control target. This directional transmission mechanism prevents cross-link signal misflow, reduces mutual interference between different link signals, and significantly improves the accuracy and reliability of system signal transmission.

[0031] In addition, the signal receiving module 110 is designed to receive control signals from at least two independent links. The link size can be expanded or reduced as needed, making it compatible with diverse application scenarios. It can achieve high-precision synchronous control without relying on complex application-specific integrated circuits. While simplifying the hardware structure, it reduces cost and power consumption, effectively solving problems such as poor synchronization, error-prone flow, high cost, and weak versatility in traditional multi-link architectures.

[0032] In some embodiments, see Figure 2As shown, the synchronization decision module 120 includes a level detection unit 121 and a logic generation unit. The level detection unit 121 can be configured to detect the level value of each control signal. The logic generation unit can be configured to compare each level value with a preset threshold and generate an enable signal based on the comparison result. The path control module 130 uses the enable signal to transmit the control signal to its respective control target. The synchronization decision module 120 accurately obtains the level value of each control signal through the level detection unit 121, and then the logic generation unit compares each level value with the preset threshold one by one and generates an enable signal accordingly. This achieves accurate determination of the synchronization status of multi-link control signals, provides a reliable control basis for the path control module 130, and avoids synchronization control failure caused by misjudgment of a single signal level.

[0033] In some embodiments, see Figure 2 As shown, the path control module 130 includes multiple controlled switch units. Each controlled switch unit is connected in series on the transmission path of each control signal, and the control terminals of each controlled switch unit receive an enable signal and are configured to synchronously turn on when the enable signal is received. In this way, independent and precise control of the transmission of control signals for each link is achieved to block signal cross-flow of non-target links, while ensuring that the control signals of all qualified links are transmitted simultaneously when triggered by the enable signal, avoiding the synchronization deviation of multi-link signals caused by differences in the switching turn-on timing.

[0034] In some embodiments, see Figure 3 As shown, the multi-link synchronization control circuit 100 also includes a mode management module 140. The mode management module 140 is communicatively connected to the signal receiving module 110 and the path control module 130. The mode management module 140 is configured to detect the status of each control signal. Furthermore, the mode management module 140 is configured to overwrite the output of the synchronization decision module 120 and control the path control module 130 to establish a transmission channel for only a portion of the control signals when a predetermined mode condition is detected. By adding the mode management module 140, which is communicatively connected to the signal receiving module 110 and the path control module 130, when detecting the status of each control signal and determining that the predetermined mode condition is met, it can overwrite the output of the synchronization decision module 120 and control the path control module 130 to establish a transmission channel for only a portion of the control signals. This breaks through the single logic of conventional synchronization control that synchronously conducts or blocks the entire link, achieving flexible adaptation of the multi-link system under special operating conditions such as low power consumption in a single link and fault link avoidance, significantly improving the compatibility and operational flexibility of the system application scenarios.

[0035] It should be noted that the predetermined mode conditions include the first control signal pwr0 reaching a preset threshold and the second control signal pwr1 maintaining a flag level below the preset threshold.

[0036] In some embodiments, the mode management module 140 includes a signal analysis unit and an instruction overwrite unit. The signal analysis unit can be configured to identify flag levels. The instruction overwrite unit is configured to output a selective conduction instruction to the path control module 130 when a flag level is identified, thereby blocking the transmission channel corresponding to the link maintaining the flag level. This achieves precise blocking control of specific links, ensuring that only valid link transmission is maintained in a predetermined mode, improving the accuracy of mode switching and the system's adaptability to diverse scenarios.

[0037] In some embodiments, the control target includes a signal processing unit, power management module, interface circuit, display driver circuit, or physical layer circuit in the display timing controller 200 of an electronic device.

[0038] The following explanation uses two parallel, independent links: For example, see Figure 1 and Figure 2 As shown, the signal receiving module 110 includes a first input terminal 111 and a second input terminal 112, which are respectively used to receive a first control signal pwr0 from a first link and a second control signal pwr1 from a second link. The signal receiving module 110 can physically be represented as a trace on a printed circuit board, a connector pin, or an input pad of an integrated circuit.

[0039] Among them, see Figure 1 and Figure 2 As shown, the first control signal pwr0 and the second control signal pwr1 can be control signals sent by the auxiliary channel to the timing controller 200, which can modify the power state of the timing controller 200. For example, switching the timing controller 200 from sleep mode to power-on mode, or from normal mode to low-power mode.

[0040] For example, see Figure 1 and Figure 2 As shown, the synchronization decision module 120 may include a level detection unit 121. The level detection unit 121 may include a first switching element T1 and a second switching element T2 connected in series. The control terminal of the first switching element T1 is connected to the first input terminal 111, and it can be used to detect the level of the first control signal pwr0. The first terminal of the first switching element T1 is connected to the power supply to receive the power signal VCC. The second terminal of the first switching element T1 is connected to the first terminal of the second switching element T2. The control terminal of the second switching element T2 is connected to the second input terminal 112, and the second terminal of the second switching element T2 is grounded.

[0041] For example, both the first switching element T1 and the second switching element T2 can be NPN transistors, which are turned on at a high level. That is, the preset threshold can be the on-level (high level). In normal operation, when the first control signal pwr0 and the second control signal pwr1 synchronously reach the preset threshold, the first switching element T1 and the second switching element T2 in the synchronization decision module 120 are turned on, and the power signal VCC can flow downwards along the first switching element T1 and the second switching element T2. If either the first switching element T1 or the second switching element T2 is not turned on, the power signal VCC cannot flow downwards.

[0042] In another example, the first switching element T1 and the second switching element T2 can also be PNP transistors, which are turned on at a low level.

[0043] Understandably, the ease of integration and low cost of transistors mean that this multi-link synchronous control circuit 100 will not occupy too much area or cost.

[0044] In another example, the first switching element T1 and the second switching element T2 can also be field-effect transistors (metal-oxide semiconductors, MOS transistors).

[0045] It is worth mentioning that in the multi-link synchronous control circuit 100 of this embodiment, the first switching element T1 and the second switching element T2 have a conduction voltage characteristic of approximately 0.7V. Considering the actual signal voltage used by the timing controller 200 (such as 3.3V, 5V, etc.), its output effective control signal voltage is much higher than the transistor's conduction voltage threshold. Therefore, during circuit operation, as long as the timing controller 200 can identify and output a valid signal, this signal voltage will necessarily meet the transistor's conduction condition, and there will be no situation where the signal is identified but the transistor cannot conduct due to insufficient voltage.

[0046] Therefore, it can be concluded that the situation in which the transistor is in a non-conducting state is unique: that is, the control terminal of the transistor does not detect a valid signal. In a multi-link transmission scenario, this phenomenon of not detecting a signal corresponds to a signal transmission delay between links, which causes the signal of a specific link to not arrive at the control terminal of the transistor on time.

[0047] For example, the synchronization decision module 120 may also include a logic generation unit. In this embodiment, the logic generation unit does not have a complex logic chip; its function is naturally achieved by the level state between the second switching element T2 and ground. The level at the second terminal of the second switching element T2 is the enable signal. The logic is as follows: when both the first control signal pwr0 and the second control signal pwr1 are high, the first switching element T1 and the second switching element T2 are simultaneously turned on. The power supply signal VCC is transmitted through the first switching element T1 and the second switching element T2 to the second terminal of the second switching element T2, causing the second terminal of the second switching element T2 to be pulled up to a high level. At this time, the enable signal is also high. If either the first control signal pwr0 or the second control signal pwr1 is low, then either the first switching element T1 or the second switching element T2 is turned off, the second terminal of the second switching element T2 is low, and the enable signal is also low.

[0048] For example, the second terminal of the second switching element T2 is connected to the first terminal of the resistor, and the second terminal of the resistor is grounded. This resistor stabilizes the second terminal of the second switching element T2 to ground (low level) when it is in the off state, preventing subsequent modules from misinterpreting the signal state due to uncertain voltage levels. Simultaneously, when the second switching element T2 is on, the resistor forms a stable current path with the switching element, limiting the loop current to a safe range and preventing damage to the switching element due to overcurrent. This ensures the stability of the circuit during switching state transitions and the accuracy of signal detection.

[0049] For example, the path control module 130 is electrically connected to the synchronization decision module 120 and is used in response to an enable signal. The path control module 130 includes a third switching element T3 and a fourth switching element T4. The control terminal of the third switching element T3 is connected to the second terminal of the second switching element T2, and the first terminal of the third switching element T3 is connected to the first output terminal. The second terminal of the fourth switching element T4 is connected to the control target. The control terminal of the fourth switching element T4 is connected to the second terminal of the second switching element T2, and the first terminal of the fourth switching element T4 is connected to the second output terminal. The second terminal of the fourth switching element T4 is also connected to the control target.

[0050] It is understandable that the control target connected to the second terminal of the third switching element T3 is different from the control target connected to the second terminal of the fourth switching element T4. For example, the second terminals of the third switching element T3 and the fourth switching element T4 can be connected to the control registers of the main physical layer PHY0 and the slave physical layer PHY1 inside the timing controller 200, respectively. In this way, the directional independent transmission of multi-link control signals can be realized, so that each link signal is only sent to its dedicated control target. This avoids cross-current interference between different link signals and non-target modules, and ensures that each control target only receives specific link signals that match its function. This meets the needs of different control targets for independent control commands, thereby improving the accuracy of signal allocation in the multi-link system and the independence and reliability of the operation of each control target.

[0051] In addition, the control terminal of the third switching element T3, the control terminal of the fourth switching element T4, and the second terminal of the second switching element T2 are connected to the first node A.

[0052] For example, the third switching element T3 and the fourth switching element T4 can both be NPN transistors, which are turned on at a high level.

[0053] In normal operation, see Figure 2 As shown, when the first control signal pwr0 and the second control signal pwr1 synchronously reach a preset threshold (high level), the first switching element T1 and the second switching element T2 of the synchronization decision module 120 are turned on. The power signal VCC is transmitted to the second terminal of the second switching element T2 through the first switching element T1 and the second switching element T2, so that the enable signal becomes high level. This high-level enable signal drives the third switching element T3 and the fourth switching element T4 of the path control module 130 to turn on, so that the first control signal pwr0 is transmitted to the main physical layer phy0 through the third switching element T3, and the second control signal pwr1 is transmitted to the slave physical layer phy1 through the fourth switching element T4. This achieves precise synchronous transmission of the control signals of the two links and effectively avoids deadlock problems caused by signal asynchrony.

[0054] For example, see Figure 3 As shown, the multi-link synchronization control circuit 100 also includes a mode management module 140. The mode management module 140 is connected to the signal receiving module 110, the synchronization decision module 120, and the path control module 130. The core function of the mode management module 140 is to overwrite the normal output of the synchronization decision module 120 and intelligently select the signal path to be turned on when a specific mode condition is detected.

[0055] For example, the mode management module 140 may include a signal analysis unit. The signal analysis unit may be implemented by logic circuitry or a simple comparator within the timing controller 200, with its inputs connected to the first input 111 and the second input 112, for continuously detecting the level states of the first input 111 and the second input 112.

[0056] For example, the mode management module 140 may further include an instruction overwriting unit. The instruction overwriting unit may include a fifth switching element Q1 and a sixth switching element Q2. The first terminal of the fifth switching element Q1, the second terminal of the first switching element T1, and the first terminal of the second switching element T2 are connected to the second node B. The second terminal of the fifth switching element Q1 is connected to the first node A. The control terminal of the fifth switching element Q1 is connected to the output of the signal analysis unit to receive the first mode control signal from the signal analysis unit. The first terminal of the sixth switching element Q2 is connected to the first node A. The second terminal of the sixth switching element Q2 is connected to the control terminal of the fourth switching element T4. The control terminal of the sixth switching element Q2 is connected to the second mode control signal in the signal analysis unit.

[0057] For example, the fifth switching element Q1 and the sixth switching element Q2 can be N-channel enhancement-mode field-effect transistors (metal-oxide semiconductors, MOSFETs). The first mode control signal and the second mode control signal can be pulse width modulation waves.

[0058] See Figure 3 As shown by the dashed line, in high-bandwidth mode (dual-link synchronization), when the signal analysis unit detects that both the first control signal pwr0 and the second control signal pwr1 are high, it determines that it is in high-bandwidth mode. At this time, the signal analysis unit does not recognize the flag level (low level). The signal analysis unit outputs a low-level first-mode control signal to the control terminal of the fifth switch element Q1 and a high-level second-mode control signal to the control terminal of the sixth switch element Q2. At this time, the first switch element T1, the second switch element T2, and the sixth switch element Q2 are turned on, the fifth switch element Q1 is turned off, making the control terminals of the third switch element T3 and the fourth switch element T4 high, and turning on the third switch element T3 and the fourth switch element T4. This allows the first control signal pwr0 to be transmitted to the main physical layer phy0 through the third switch element T3, and the second control signal pwr1 to be transmitted to the slave physical layer phy1 through the fourth switch element T4, achieving precise synchronous transmission of the control signals of the two links and effectively avoiding deadlock problems caused by signal asynchrony.

[0059] See Figure 3As shown by the solid line, in low bandwidth mode (single-link operation), when switching to low bandwidth mode is required, the upstream signal source (the system-on-a-chip in display device 10) will stop sending the second control signal pwr1 (high level) to the second link, and instead send a low-voltage flag signal, which is lower than a preset threshold. The first link continues to send the first control signal pwr0 (whose level reaches the preset threshold).

[0060] The signal analysis unit detects that the first control signal pwr0 is high and the flag signal is low. When this predetermined mode condition is met, a single-link mode instruction is generated. Subsequently, the instruction overwrite unit outputs a high-level first mode control signal to the control terminal of the fifth switch element Q1 and a low-level second mode control signal to the control terminal of the sixth switch element Q2. At this time, the fifth switch element Q1 is turned on, the sixth switch element Q2 is turned off, and the power supply is directly led to the control terminal of the third switch element T3 through the turned-on first switch element T1, turning on the third switch element T3. The first control signal pwr0 is transmitted to the main physical layer phy0 through the third switch element T3, thus realizing the mode of transmission using only a single link.

[0061] In other words, this application intelligently detects the input state through a signal analysis unit and uses the first switching element T1 and the second switching element T2 to precisely overwrite and control the synchronization control circuit and the path control circuit, thus achieving both high-bandwidth synchronization reliability and low-bandwidth power consumption economy. This allows it to meet the needs of low-end and mid-range products, or even provide true frequency reduction functionality for high-end products. In this case, the amount of data is reduced, eliminating the need for multi-link transmission to meet refresh rate and resolution requirements, and avoiding the risk of multi-link interference at high refresh rates.

[0062] In the above embodiments, the first switching element T1, the second switching element T2, the third switching element T3, the fourth switching element T4, the fifth switching element Q1, and the sixth switching element Q2 can all be other types of switching elements, such as PNP transistors or P-channel / N-channel MOSFETs, etc. Their circuit connections need to be adjusted accordingly, all of which fall within the equivalent substitution and protection scope of this invention. The control targets include, but are not limited to, the physical layer, power management unit, voltage regulator, or any other circuit module in the display timing controller 200 that needs to receive synchronization control signals; these also fall within the protection scope of this invention.

[0063] Example 2 See Figure 2 , Figure 3 and Figure 4 As shown, Embodiment 2 of this application also provides a multi-link data synchronization control method, which may include the following steps: S100 receives control signals from at least two independent links.

[0064] S200 performs synchronization state determination on at least two control signals.

[0065] S300 generates and sends an enable signal when it is confirmed that all control signals have reached the preset threshold.

[0066] S400, in response to the enable signal, establishes a synchronous transmission channel for all control signals to their respective control targets.

[0067] In step S100, the signal receiving module 110 built into the timing controller 200 is used to perform this step: The signal receiving module 110 receives the first control signal pwr0 of the first link and the second control signal pwr1 of the second link through two independent input terminals.

[0068] In step S200, the synchronization decision module 120 of the timing controller 200 is used. The synchronization decision module 120 may include a level detection unit 121 and a logic generation unit. Step S200 is executed using the level detection unit 121 and the logic generation unit. The level detection unit 121 collects the level values ​​of the first control signal pwr0 and the second control signal pwr1 respectively, and compares the collected level values ​​of the first control signal pwr0 and the second control signal pwr1 with preset thresholds to obtain the comparison results.

[0069] The logic generation unit performs an AND operation on the two comparison results. It outputs a synchronization valid signal only when both the first control signal pwr0 and the second control signal pwr1 are high; otherwise, it outputs a synchronization invalid signal.

[0070] In step S300, this step is performed using the logic generation unit of the synchronization decision module 120: When the logic generation unit outputs a synchronous valid signal, it generates a high-level valid enable signal and transmits the enable signal to the path control module 130 of the timing controller 200.

[0071] If the decision result is that the synchronization is invalid, the logic generation unit outputs a low-level enable signal and does not trigger subsequent path establishment actions.

[0072] In step S400, the path control module 130 of the timing controller 200, which may include a third switching element T3 and a fourth switching element T4, executes step S400 according to the enable signal: After receiving the enable signal, the control terminal of the path control module 130 triggers the switch conduction logic. When the enable signal is high, the third switch element T3 and the fourth switch element T4 are turned on, so that the first control signal pwr0 is transmitted to the enable terminal of the main physical layer phy0 circuit through an independent transmission line, triggering the main physical layer phy0 to start link training. After the fourth switch element T4 is turned on, the second control signal pwr1 is similarly transmitted to the slave physical layer phy1 circuit, realizing the synchronous start of the two physical layers.

[0073] It is understandable that this control method may also include: The signal analysis unit analyzes the level states of the detected first control signal pwr0 and second control signal pwr1 to determine whether the predetermined mode conditions are met. If the first condition is met (both the first control signal pwr0 and the second control signal pwr1 are at a high level): the signal analysis unit outputs a low-level first mode control signal and a high-level second mode control signal circuit, and the first control signal pwr0 and the second control signal pwr1 are synchronously transmitted to the physical layer circuit to achieve synchronous startup of the two physical layers.

[0074] If the second condition is met (the first control signal pwr0 is high and the second control signal pwr1 is low), the signal analysis unit determines that it needs to enter single-link operating mode. Subsequently, it outputs a high-level first-mode control signal and a low-level second-mode control signal, thus achieving single-link transmission.

[0075] The multi-link data synchronization control method of this application realizes the automation of decision-making and execution by responding to signal state changes in real time through hardware circuits, and has the advantages of high reliability, low latency and low power consumption.

[0076] Example 3 See Figure 5 As shown, this embodiment discloses a timing controller 200 that integrates a multi-link synchronization control circuit 100, which is suitable for 4K / 8K high-resolution display devices 10, and is especially suitable for eDP (embedded DisplayPort) multi-link transmission scenarios.

[0077] For example, the timing controller 200 may include a control unit, the aforementioned multi-link synchronization control circuit 100, a physical layer interface unit, and a power management unit.

[0078] The control unit can use a dedicated timing control chip to generate the horizontal synchronization signal, vertical synchronization signal and pixel clock required by the display panel 300.

[0079] The multi-link synchronization control circuit 100 can be integrated into the hardware circuit of the timing controller 200. It may include the signal receiving module 110, the synchronization decision module 120, the path control module 130 and the mode management module 140 mentioned above. For details, please refer to the above description. It will not be elaborated here.

[0080] The physical layer interface unit may include a master physical layer phy0 circuit and a slave physical layer phy1 circuit, which may correspond to two independent eDP links respectively, for converting the received differential signal into parallel data.

[0081] The power management unit provides operating voltage to each module inside the timing controller 200 and switches the power supply mode in response to the control signals of the multi-link synchronization control circuit 100.

[0082] Among them, the signal receiving module 110 of the multi-link synchronization control circuit 100 is connected to an external link (such as the eDP master / slave link output by the system-level chip board), and the output terminal of the path control module 130 is connected to the enable terminal of the master physical layer phy0 circuit and the slave physical layer phy1 circuit respectively, so as to realize the synchronous control of the signal transmission of the two links.

[0083] When the display device 10 operates in dual-link mode, the first link sends a first control signal pwr0, and the second link sends a second control signal pwr1. The signal receiving module 110 receives the first control signal pwr0 and the second control signal pwr1 and transmits them to the synchronization decision module 120. After level detection and logic judgment, and confirming that both have reached a high level (preset threshold), an enable command is generated. The third switch element T3 and the fourth switch element T4 of the path control module 130 are synchronously turned on, transmitting the first control signal pwr0 and the second control signal pwr1 to the main physical layer phy0 circuit and the slave physical layer phy1 circuit, respectively, triggering the simultaneous start of link training in both physical layers. Based on the synchronously transmitted link data, the core control unit generates a matching display timing sequence to ensure that the dual-link data is synthesized without deviation at the display panel 300.

[0084] Example 4 See Figure 5 As shown, Embodiment 4 of this application provides a display device 10, including a display panel 300 and a timing controller 200. The display panel 300 may be an 8K resolution organic light-emitting diode or liquid crystal panel. The timing controller 200 is connected to the system-on-a-chip board of the display panel 300 via a flexible flat cable (FFC), and its multi-link synchronization control circuit 100 is connected to the eDP transmitter of an external motherboard.

[0085] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0086] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A multi-link synchronous control circuit, characterized in that, include: The signal receiving module is configured to receive control signals from at least two independent links; A synchronization decision module, connected to the signal receiving module, is configured to perform synchronization state detection on the at least two control signals; the synchronization decision module includes a level detection unit and a logic generation unit. The level detection unit is configured to detect the level value of each of the control signals; the logic generation unit is configured to compare each of the level values ​​with a preset threshold, and when all the control signals are detected to have reached the preset threshold, generate an enable signal based on the comparison result. A path control module is connected to the synchronization decision module; the path control module includes multiple controlled switch units, each of which is connected in series on the transmission path of each control signal; the control terminals of each controlled switch unit jointly receive the enable signal and are configured to synchronously conduct when the enable signal is received, so as to establish a synchronous transmission channel for all control signals to their respective control targets.

2. The multi-link synchronous control circuit according to claim 1, characterized in that, The multi-link synchronization control circuit also includes a mode management module, which is communicatively connected to the signal receiving module and the path control module, and is configured to detect the status of each control signal. The mode management module is also configured to: when a predetermined mode condition is detected to be met, overwrite the output of the synchronization decision module and control the path control module to establish a transmission channel for part of the control signal.

3. The multi-link synchronous control circuit according to claim 2, characterized in that, The predetermined mode conditions include: the first control signal reaches the preset threshold, and the second control signal is maintained at a flag level lower than the preset threshold.

4. The multi-link synchronous control circuit according to claim 3, characterized in that, The mode management module includes a signal analysis unit and an instruction overwrite unit; The signal analysis unit is configured to identify the flag level; The instruction overwrite unit is configured to output a selective conduction instruction to the path control module when the flag level is detected, so as to block the transmission channel corresponding to the link that maintains the flag level.

5. The multi-link synchronous control circuit according to claim 4, characterized in that, The control targets include signal processing units, power management modules, interface circuits, display driver circuits, or physical layer circuits in display timing controllers of electronic devices.

6. A multi-link data synchronization control method, characterized in that, The method, applied to the multi-link synchronization control circuit of claim 1, comprises: The signal receiving module receives control signals from at least two independent links. The level detection unit detects the level value of each control signal, and the logic generation unit compares each level value with the preset threshold. When it is confirmed that the level values ​​of all the control signals have reached the preset threshold, an enable signal is generated and sent by the logic generation unit. The path control module responds to the enable signal to synchronously turn on each of the controlled switch units, thereby establishing a synchronous transmission channel for all the control signals to their respective control targets.

7. A timing controller, characterized in that, It integrates the multi-link synchronization control circuit as described in any one of claims 1 to 6.

8. A display device, characterized in that, include: Display panel; as well as The timing controller as described in claim 7, wherein the timing controller is connected to the display panel.

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