A step-down dc-dc converter circuit for improving frequency stability

Abstract

The application discloses a step-down DC-DC converter circuit for improving frequency stability, and belongs to the technical field of power conversion, which comprises: a conduction time generation circuit; the conduction time generation circuit comprises three input ends and an output end, the first input end is used for inputting an input voltage; the second input end is used for inputting an output voltage of the converter circuit; the third input end is connected with an inverter and receives a discharge control signal from the inverter; the output end is connected with a logic control circuit; the conduction time generation circuit adjusts the conduction time by introducing a correction amount positively related to the input voltage, generates a conduction time signal according to the output voltage as a reference and the discharge control signal, and outputs the conduction time signal to the logic control circuit through the output end. By introducing a correction amount positively related to the input voltage, the switching frequency is kept highly constant, the noise spectrum is effectively tightened, the electromagnetic interference level of the system is reduced, and the overall electromagnetic compatibility is improved.

Description

Technical Field

[0001] This invention relates to the field of power conversion technology, and more specifically to a step-down DC-DC converter circuit that improves frequency stability. Background Technology

[0002] Currently, traditional buck DC-DC converters use a fixed-frequency pulse width modulation (PWM) control method, which has a very stable frequency. Its switching frequency does not change with the input voltage. However, this type of DC-DC converter has poor load dynamic response; that is, the output voltage fluctuates significantly when the output load current changes rapidly. With technological advancements, COT (constant on-time) architecture DC-DC converters have gradually emerged. Based on this, ACOT (Adaptive constant on-time) architecture buck DC-DC converters have evolved. The design concept of ACOT is to design an on-time that is inversely proportional to the VIN voltage and directly proportional to the output voltage, i.e., Ton = K * VO / VIN, where Ton is the main switch on-time, VO is the output voltage, VIN is the input voltage, and K is a design constant. Buck DC-DC converters satisfy the volt-second balance formula: Ton / Ts = D = VO / VIN, where Ton is the main switch on-time, VO is the output voltage, VIN is the input voltage, D is the duty cycle of the main switch, and Ts is the switching period. Based on the two formulas above, we can obtain: Ts = Ton * VIN / VO = (K * VO / VIN) * VIN / VO = K. Therefore, a near-constant switching cycle can be achieved.

[0003] However, in actual circuit design, Ton is also affected by the comparator delay time and the drive circuit delay time in the actual implementation. For example, due to non-ideal factors, Ton = K*VO / VIN + Ta. Substituting this into the second formula, we get: Ts = K + Ta*VIN / VO. It can be seen that as VIN increases, Ts increases, and therefore the frequency decreases as VIN increases. Many buck DC-DC converters exhibit the characteristic that the switching frequency decreases as VIN increases. However, in some applications, a more constant switching frequency is desired for the DC-DC converter, as a changing switching frequency can introduce noise over a wider frequency range.

[0004] Therefore, how to solve the problem of unstable switching frequency of buck DC-DC converters in the prior art, which easily introduces noise over a wider frequency range, is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a buck DC-DC converter circuit that improves frequency stability, thereby overcoming or at least partially solving the above problems. To achieve the above objectives, the present invention adopts the following technical solution: This invention provides a buck DC-DC converter circuit for improving frequency stability; specifically, it includes: an on-time generation circuit; The conduction time generation circuit includes three input terminals and one output terminal. The first input terminal is used to connect the input voltage; the second input terminal is used to connect the output voltage of the converter circuit; the third input terminal is connected to the inverter and receives the discharge control signal from the inverter; the output terminal is connected to the logic control circuit. The conduction time generation circuit adjusts the conduction time by introducing a correction amount that is positively correlated with the input voltage, and generates a conduction time signal based on the output voltage as a reference and the discharge control signal; and outputs the conduction time signal to the logic control circuit through the output terminal.

[0006] Furthermore, it also includes: comparator circuits and power switching circuits; The logic control circuit is connected to the comparator circuit and the power switch circuit respectively; The comparison circuit outputs a pulse signal to the logic control circuit. The logic control circuit generates a switch control signal based on the conduction time signal and the pulse signal, and outputs the switch control signal to the power switch circuit.

[0007] Furthermore, the power switching circuit includes: a high-side driver, a high-side switch, a low-side driver, a low-side switch, a voltage regulator, and a bootstrap capacitor; The high-side driver and the low-side driver are respectively connected to the logic control circuit and receive the switch control signal; The high-side driver and the high-side switch are connected, and the drive signal is output to the high-side switch; The low-side driver is connected to the low-side switch, and outputs the drive signal to the low-side switch; The voltage regulator is connected to one end of the bootstrap capacitor via a diode to provide a stable voltage to the bootstrap capacitor; the other end of the bootstrap capacitor is connected to one end of the high-side switch and the low-side switch, respectively.

[0008] Furthermore, the comparator circuit includes: a first positive input terminal, a first negative input terminal, a second positive input terminal, and a second negative input terminal. The first positive input terminal is used to connect to the first reference voltage; the first negative input terminal is connected to a voltage divider circuit. Both the second positive input terminal and the second negative input terminal are connected to a ripple injection circuit; The voltage divider circuit divides the output voltage to generate a feedback signal, and outputs the feedback signal to the comparator circuit. The first reference voltage provides a target reference voltage for the comparator circuit; The ripple injection circuit provides a differential signal to the comparator circuit.

[0009] Furthermore, the ripple injection circuit includes: a first voltage divider resistor, a second voltage divider resistor, a first filter circuit, and a second filter circuit; The first filter circuit includes a first resistor and a first capacitor for generating a first ripple signal; the second filter circuit includes a second resistor and a second capacitor for generating a second ripple signal. in, The first voltage divider resistor and the second voltage divider resistor are connected in series and connected to the intermediate node to divide the voltage at the intermediate node; The circuit between the first voltage divider resistor and the second voltage divider resistor is connected to one end of the first resistor and the second resistor, respectively; the other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is grounded. The other end of the second resistor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded.

[0010] Furthermore, the on-time generation circuit includes: The third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the eighth resistor, the operational amplifier, the comparator, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor, and the third capacitor; The first input terminal is connected to one end of the third resistor, the source (S) terminal of the first PMOS transistor, and the source (S) terminal of the second PMOS transistor, respectively. The other end of the third resistor is connected to one end of the fourth resistor, and the line between the third resistor and the fourth resistor is connected to the positive input terminal of the operational amplifier. The other end of the fourth resistor is grounded and is connected to one end of the seventh resistor, the source of the second NMOS transistor, one end of the eighth resistor, and one end of the sixth resistor, respectively. The gate (G) of the first PMOS transistor is connected to the gate (G) of the second PMOS transistor; the drain (D) of the first PMOS transistor is connected to the drain (D) of the first NMOS transistor; the source (S) of the first NMOS transistor is connected to the other end of the seventh resistor; and the line between the first NMOS transistor and the seventh resistor is connected to the negative input terminal of the operational amplifier. The drain (D) of the second PMOS transistor is connected to one end of the third capacitor and the drain of the second NMOS transistor. The source (S) of the second NMOS transistor is grounded, and the gate (G) is connected to the third input terminal. The other end of the third capacitor is connected to the other end of the eighth resistor. One end of the fifth resistor is connected to the second input terminal, and the other end is connected to the other end of the sixth resistor; The line between the drain of the second PMOS transistor and the third capacitor is connected to the positive input terminal of the comparator, and the line between the fifth resistor and the sixth resistor is connected to the negative input terminal of the comparator. The comparator outputs an on-time signal.

[0011] Furthermore, the on-time generation circuit includes: Ninth resistor, tenth resistor, eleventh resistor, twelfth resistor, thirteenth resistor, operational amplifier, comparator, third PMOS transistor, fourth PMOS transistor, fifth PMOS transistor, third NMOS transistor, fourth NMOS transistor, fifth NMOS transistor, sixth NMOS transistor, and fourth capacitor; The first input terminal is connected to one end of the ninth resistor, the source terminal of the third PMOS transistor, the source terminal of the fourth PMOS transistor, and the source terminal of the fifth PMOS transistor, respectively. The other end of the ninth resistor is connected to one end of the tenth resistor, and the line between the ninth resistor and the tenth resistor is connected to the positive input terminal of the operational amplifier. The other end of the tenth resistor is grounded and is connected to one end of the thirteenth resistor, the source of the fourth NMOS transistor, one end of the twelfth resistor, the source of the sixth NMOS transistor, and the source of the fifth NMOS transistor, respectively. The gate (G) of the third PMOS transistor is connected to the gate (G) of the fourth PMOS transistor, the drain (D) of the third PMOS transistor is connected to the drain (D) of the third NMOS transistor, the source (S) of the third NMOS transistor is connected to the other end of the thirteenth resistor, and the line between the third NMOS transistor and the thirteenth resistor is connected to the negative input terminal of the operational amplifier. The drain (D) of the fourth PMOS transistor is connected to one end of the fourth capacitor and the drain (D) of the fourth NMOS transistor. The source (S) of the fourth NMOS transistor is grounded, the gate (G) is connected to the third input terminal, and the other end of the fourth capacitor is grounded. One end of the eleventh resistor is connected to the second input terminal, and the other end is connected to one end of the twelfth resistor, with the other end of the twelfth resistor grounded. The line between the eleventh resistor and the twelfth resistor is connected to the drain (D) of the sixth NMOS transistor. The source (S) of the sixth NMOS transistor is grounded, and its gate (G) is connected to the gate (G) of the fifth NMOS transistor. The source (S) of the fifth NMOS transistor is grounded, and its drain (D) is connected to the drain (D) of the fifth PMOS transistor. The gate (G) of the fifth PMOS transistor is connected to the drain (D) of the third PMOS transistor. The line between the drain of the fourth PMOS transistor and one end of the fourth capacitor is connected to the positive input terminal of the comparator, and the line between the eleventh resistor and the twelfth resistor is connected to the negative input terminal of the comparator. The comparator outputs an on-time signal.

[0012] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a buck DC-DC converter circuit with improved frequency stability, which has the following beneficial effects: 1. This invention actively and in real-time compensates for non-ideal frequency drift by introducing a correction factor positively correlated with the input voltage into the conduction time generation circuit. Specifically, when the input voltage increases, this correction factor correspondingly reduces the conduction time of the circuit, thereby offsetting the trend of prolonged switching cycle caused by the voltage increase; the switching frequency can remain highly constant throughout the entire input voltage variation range, effectively tightening the noise spectrum, reducing the electromagnetic interference level of the system, and improving overall electromagnetic compatibility. 2. This invention generates correction values ​​through internal voltage division, current mirroring, and charging timing control, eliminating the need for complex external circuits, expensive precision components, or digital control algorithms. It provides a highly cost-effective and technically feasible path to achieving high-performance, high-stability power supply solutions, suitable for large-scale applications in cost-sensitive and noise-critical fields such as consumer electronics, communication equipment, and automotive electronics. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0014] Figure 1 This is a circuit diagram of a DC-DC converter provided in an embodiment of the present invention; Figure 2 This is a structural diagram of the conduction time generation circuit provided in an embodiment of the present invention; Figure 3 This is a structural diagram of the conduction time generation circuit provided in an embodiment of the present invention; Figure 4 This is a structural diagram of the ripple injection circuit provided in an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This invention discloses a buck DC-DC converter circuit for improving frequency stability; such as... Figure 1 As shown, the specific components include: resistors Rf1 and Rf2, RippleGen module (ripple injection circuit), TONGEN module (on-time generation circuit), SumCOMP (comparator circuit), COT CTL module (logic control circuit), high-side driver HDRV, low-side driver LDRV, voltage regulator LDO, diode D1, inverter INV, bootstrap capacitor Cbs, output capacitor C1, inductor L1, and load RL.

[0017] The RippleGen module generates differential ripple injection signals RP and RN. These ripple signals are necessary for stabilization when using a low ESR (Equivalent Series Resistance) output capacitor. Resistors Rf1 and Rf2 divide the output voltage VO to generate the FB signal, which is input to the first negative input terminal of the SumCOMP module. VR1 is a reference voltage, which can be provided by a bandgap reference circuit and is input to the first positive input terminal of the SumCOMP module. The differential ripple injection signals RP and RN generated by the RippleGen module are connected to the second positive and second negative input terminals of the SumCOMP module, respectively. When the FB voltage drops below VR1, the SumCOMP module outputs a high PWM signal, triggering the high-side switch to conduct via the TON CTL module (i.e., both HD1 and HD2 become high). The falling edges of HD1 and HD2 are determined by the rising edge of the TON output signal from the TONGEN module. This ensures that the high-side switch conduction time matches the control time in the TONGEN module (explained in detail later when describing the working principle of the TONGEN module).

[0018] Cbs is the bootstrap capacitor. Here, the high-side power switch S1 is generally implemented by an NMOS, so the high level of its drive voltage needs to be raised to higher than VIN through the capacitor Cbs. When the switch S2 is turned on, the SW node is brought down to ground level. The LDO charges Cbs through the diode D1. When fully charged, it is close to the LDO output voltage minus the forward voltage drop of the diode. Here, VLDO-VD is used to represent the voltage of the capacitor Cbs, where VLDO is the output voltage of the LDO and VD is the forward voltage drop of the diode. When the high-side switch S1 is turned on, SW rises. Since Cbs maintains its voltage across its terminals, the voltage of the Vbs node also rises, always remaining higher than SW by VLDO-VD.

[0019] During normal operation, switches S1 and S2 are alternately turned on. SW is approximately a square wave signal, with its high level approximately equal to VIN and its low level approximately equal to ground. Its duty cycle is controlled by loop negative feedback. Inductor L1 and capacitor C1 filter the waveform of SW into an approximate DC voltage, the value of which satisfies VO = D * VIN, where VO is the output voltage of the buck DC-DC converter, D is the duty cycle of the SW signal, and VIN is the input power supply voltage VIN. In this invention... Figure 1 The novel TON generation circuit TONGEN according to the present invention is used, which can realize the characteristic that the compensation frequency decreases as VIN increases, and realize that the switching frequency changes less with VIN.

[0020] This invention relates to two specific implementation methods for the TONGEN module: Example 1: like Figure 2 As shown, the circuit includes resistors R1~R6, operational amplifier OP, comparator Comp, PMOS transistors MP1 and MP2, NMOS transistors MN1 and MN2, and capacitor C1. The VIN voltage is divided by resistors R1 and R2 to generate VR2 (VR2 = VIN * R2 / (R1 + R2)), which is connected to the positive input of operational amplifier OP. The operational amplifier and MN1 form negative feedback, adjusting to make the voltage at node VR5 equal to the voltage at node VR2. Therefore, the voltage across resistor R5 is equal to the voltage at node VR2, which is also equal to VIN * R2 / (R1 + R2), and is proportional to VIN.

[0021] The current IR5 of resistor R5 is calculated as IR5 = VIN * R2 / [(R1 + R2) * R5], where VIN is the voltage at node VIN, R1 is the resistance of resistor R1, R2 is the resistance of resistor R2, and R5 is the resistance of resistor R5. MP2 and MP1 form a current mirror; MP2 replicates the current of MP1, which is equal to the current through resistor R5. The current in MP2 charges the capacitor and simultaneously flows through resistor R6.

[0022] When the VCP node voltage rises to equal the VCN node voltage, the comparator Comp output flips, and the TON signal changes from low to high. When the HSDOFF signal is high, MN2 conducts, discharging the charge from capacitor C1. Therefore, the time it takes for the capacitor to restart charging until the comparator Comp output voltage flips (changes from low to high) can be calculated using the following formula: Tch*IR5 / C1+IR5*R6=VCN=VO*R4 / (R3+R4) Where Tch is the time from when the capacitor restarts charging until the comparator Comp output voltage flips (changes from low to high), that is, the time from when HSDOFF changes from high to low (i.e., the falling edge of HSDOFF) to when the Comp output voltage TON changes from low to high (i.e., the rising edge of TON). IR5 is the current through resistor R5, C1 is the capacitance of capacitor C1, R6 is the resistance of resistor R6, VO is the voltage at node VO, R3 is the resistance of resistor R3, and R4 is the resistance of resistor R4.

[0023] The above formula yields: Tch = {VO * R4 / (R3 + R4) - IR5 * R6} Tch=[VO*R4 / (R3+R4)-IR5*R6]*C1 / IR5 If R6=0, then Tch=[VO*R4 / (R3+R4)]*C1 / IR5 As can be seen from the traditional Ton design, Tch is directly proportional to VO and inversely proportional to IR5 (i.e., inversely proportional to VIN, since IR5 is directly proportional to VIN).

[0024] When R6≠0, a correction amount is formed. As VIN increases, the correction amount IR5*R6 increases, which leads to a decrease in Tch. This further leads to a decrease in the switching period as VIN increases. That is, this correction amount can be used to compensate for the trend of the switching frequency of traditional DC-DC converters decreasing as VIN increases. By designing a suitable R6 resistor value, the effect of the switching frequency remaining approximately constant with VIN can be achieved.

[0025] Example 2: like Figure 3 As shown, it includes resistors R1~R5, operational amplifier OP, comparator Comp, PMOS transistors MP1, MP2, MP3, NMOS transistors MN1, MN2, MN3, MN4, and capacitor C1.

[0026] Figure 2 This is equivalent to introducing a correction amount into the VCP node voltage. Figure 3 This is equivalent to introducing a correction amount into the VCN node voltage.

[0027] MP3, MP2, and MP1 form a current mirror; MN4 and MN3 form a current mirror.

[0028] Figure 3 The correction amount in the middle replicates the current of MP1 through MP3, and then replicates the current of MN3 through MN4 (the drain current of MN3 is equal to the drain current of MP3). The current of MN4 is injected into the common connection point of R3 and R4, which causes the VCN node to be corrected and reduced as VIN increases, thereby correcting and reducing the Tch time.

[0029] According to Kirchhoff's laws: (VO-VCN) / R3=VCN / R4+IR5 Where: VO is the voltage value of node VO, VCN is the voltage value of node VCN, R3 is the resistance value of resistor R3, R4 is the resistance value of resistor R4, and IR5 is the current of resistor R5.

[0030] The above equation can be simplified to: VCN=(VO / R3-IR5)*R3*R4 / (R3+R4) Compared to the case where IR5 is set to 0 in the above formula, the voltage value of VCN is effectively reduced. As VIN increases, IR5 increases, and the amount of VCN reduction is also increased. That is, as VIN increases, VCN is reduced, which causes the time from the moment HSDOFF changes from high level to low level (i.e., the falling edge of HSDOFF) to the moment when the Comp output voltage TON changes from low level to high level (i.e., the rising edge of TON) to be reduced as VIN increases. This achieves the correction and compensation of the switching frequency, resulting in the switching frequency changing less with VIN after correction.

[0031] The amount of correction injected can be set by adjusting the ratio of MP3 copying MP1 current and the ratio of MN4 copying MN3 current. The larger the correction current injected into the VCN node, the larger the correction amount and the more obvious the compensation effect.

[0032] This invention also provides an implementation of the RippleGen module: like Figure 4 As shown, the voltage at node SW is divided by resistors Rs1 and Rs2, then filtered by resistor Rs3 and capacitor Cs1 to generate RP; and filtered by resistor Rs4 and capacitor Cs2 to generate RN. Generally, the low-pass filters Rs4 and Cs2 have lower cutoff frequencies, so RN is designed to be filtered to near-DC voltage; while the low-pass filters Rs3 and Cs1 have higher cutoff frequencies, so RP still retains a relatively large ripple signal. The differential signals of RP and RN are injected into the loop control to achieve loop stabilization.

[0033] This invention actively and in real-time compensates for non-ideal frequency drift by introducing a correction factor positively correlated with the input voltage into the conduction time generation circuit. Specifically, when the input voltage increases, this correction factor correspondingly reduces the circuit's conduction time, thereby offsetting the trend of prolonged switching cycles caused by the voltage increase. Throughout the entire input voltage variation range, the switching frequency remains highly constant, effectively tightening the noise spectrum, reducing the system's electromagnetic interference level, and improving overall electromagnetic compatibility.

[0034] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0035] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A step-down DC-DC converter circuit for improving frequency stability, characterized in that, include: On-time generation circuit and logic control circuit; The conduction time generation circuit includes three input terminals and one output terminal. The first input terminal is used to connect to the input voltage; the second input terminal is used to connect to the output voltage of the converter circuit; the third input terminal is connected to an inverter and receives a discharge control signal from the inverter; and the output terminal is connected to the logic control circuit. The conduction time generation circuit adjusts the conduction time by introducing a correction amount positively correlated with the input voltage, and generates a conduction time signal based on the output voltage as a reference and the discharge control signal; and outputs the conduction time signal to the logic control circuit through the output terminal; The on-time generation circuit includes: Ninth resistor, tenth resistor, eleventh resistor, twelfth resistor, thirteenth resistor, operational amplifier, comparator, third PMOS transistor, fourth PMOS transistor, fifth PMOS transistor, third NMOS transistor, fourth NMOS transistor, fifth NMOS transistor, sixth NMOS transistor, and fourth capacitor; The first input terminal is connected to one end of the ninth resistor, the source terminal of the third PMOS transistor, the source terminal of the fourth PMOS transistor, and the source terminal of the fifth PMOS transistor, respectively. The other end of the ninth resistor is connected to one end of the tenth resistor, and the line between the ninth resistor and the tenth resistor is connected to the positive input terminal of the operational amplifier. The other end of the tenth resistor is grounded and is connected to one end of the thirteenth resistor, the source of the fourth NMOS transistor, one end of the twelfth resistor, the source of the sixth NMOS transistor, and the source of the fifth NMOS transistor, respectively. The gate (G) of the third PMOS transistor is connected to the gate (G) of the fourth PMOS transistor, the drain (D) of the third PMOS transistor is connected to the drain (D) of the third NMOS transistor, the source (S) of the third NMOS transistor is connected to the other end of the thirteenth resistor, and the line between the third NMOS transistor and the thirteenth resistor is connected to the negative input terminal of the operational amplifier. The drain (D) of the fourth PMOS transistor is connected to one end of the fourth capacitor and the drain (D) of the fourth NMOS transistor. The source (S) of the fourth NMOS transistor is grounded, the gate (G) is connected to the third input terminal, and the other end of the fourth capacitor is grounded. One end of the eleventh resistor is connected to the second input terminal, and the other end is connected to one end of the twelfth resistor, with the other end of the twelfth resistor grounded. The line between the eleventh resistor and the twelfth resistor is connected to the drain (D) of the sixth NMOS transistor. The source (S) of the sixth NMOS transistor is grounded, and its gate (G) is connected to the gate (G) of the fifth NMOS transistor. The source (S) of the fifth NMOS transistor is grounded, and its drain (D) is connected to the drain (D) of the fifth PMOS transistor. The gate (G) of the fifth PMOS transistor is connected to the drain (D) of the third PMOS transistor. The line between the drain of the fourth PMOS transistor and one end of the fourth capacitor is connected to the positive input terminal of the comparator, and the line between the eleventh resistor and the twelfth resistor is connected to the negative input terminal of the comparator. The comparator outputs an on-time signal.

2. The step-down DC-DC converter circuit for improving frequency stability as described in claim 1, characterized in that, Also includes: Comparison circuits and power switching circuits; The logic control circuit is connected to the comparator circuit and the power switch circuit respectively; The comparison circuit outputs a pulse signal to the logic control circuit. The logic control circuit generates a switch control signal based on the conduction time signal and the pulse signal, and outputs the switch control signal to the power switch circuit.

3. The step-down DC-DC converter circuit for improving frequency stability as described in claim 2, characterized in that, The power switching circuit includes: a high-side driver, a high-side switch, a low-side driver, a low-side switch, a voltage regulator, and a bootstrap capacitor; The high-side driver and the low-side driver are respectively connected to the logic control circuit and receive the switch control signal; The high-side driver and the high-side switch are connected, and the drive signal is output to the high-side switch; The low-side driver is connected to the low-side switch, and outputs the drive signal to the low-side switch; The voltage regulator is connected to one end of the bootstrap capacitor via a diode, providing a stable voltage to the bootstrap capacitor; The other end of the bootstrap capacitor is connected to one end of the high-side switch and the low-side switch, respectively.

4. The step-down DC-DC converter circuit for improving frequency stability as described in claim 2, characterized in that, The comparator circuit includes: a first positive input terminal, a first negative input terminal, a second positive input terminal, and a second negative input terminal. The first positive input terminal is used to connect to the first reference voltage; the first negative input terminal is connected to a voltage divider circuit. Both the second positive input terminal and the second negative input terminal are connected to a ripple injection circuit; The voltage divider circuit divides the output voltage to generate a feedback signal, and outputs the feedback signal to the comparator circuit. The first reference voltage provides a target reference voltage for the comparator circuit; The ripple injection circuit provides a differential signal to the comparator circuit.

5. The step-down DC-DC converter circuit for improving frequency stability as described in claim 4, characterized in that, The ripple injection circuit includes: a first voltage divider resistor, a second voltage divider resistor, a first filter circuit, and a second filter circuit; The first filter circuit includes a first resistor and a first capacitor for generating a first ripple signal; the second filter circuit includes a second resistor and a second capacitor for generating a second ripple signal. in, The first voltage divider resistor and the second voltage divider resistor are connected in series and connected to the intermediate node to divide the voltage at the intermediate node; The circuit between the first voltage divider resistor and the second voltage divider resistor is connected to one end of the first resistor and the second resistor, respectively; the other end of the first resistor is connected to one end of the first capacitor, and the other end of the first capacitor is grounded. The other end of the second resistor is connected to one end of the second capacitor, and the other end of the second capacitor is grounded.

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