Frequency-locked loop and frequency-locked method of adaptive delay signal cancellation filter

Abstract

The application discloses a frequency-locked loop of an adaptive time-delay signal cancellation filter, comprising a first filter, a second filter, a Park transformation module, a low-pass filter, an amplitude normalization module, an inverse Park transformation module, a frequency estimation module and a low-pass filter; the first filter is used for high harmonic elimination; the second filter is used for low single harmonic elimination; a signal after the filter is converted into a direct current component in a dq coordinate system through the Park transformation module, and then high-frequency noise is filtered through the low-pass filter; subsequently, the signal is input into the amplitude normalization module to standardize the signal amplitude to 1; then the signal is recovered into an alternating current signal through the inverse Park transformation module; the alternating current signal is input into the frequency estimation module; finally, a stable power grid frequency estimation value is obtained after the signal is processed through the low-pass filter. The application aims at eliminating rounding errors and introducing a new pre-filter with a small time delay, so as to improve the dynamic and steady-state performance of the first-order frequency-locked loop.

Description

Technical Field

[0001] This application relates to the field of frequency detection technology, and in particular to a frequency-locking loop and frequency-locking method for an adaptive delay signal cancellation filter. Background Technology

[0002] Inertia is fundamental to power system stability, acting as a buffer to mitigate the impact of sudden changes in supply and demand. In renewable energy generation systems, virtual inertial control is an enhancement technique that essentially involves acquiring real-time grid frequency data and performing differential calculations to provide necessary power compensation. Therefore, fast and accurate frequency detection technology is indispensable for optimizing the performance of virtual inertial control. Currently available frequency detection technologies include zero-crossing detection, discrete Fourier transform, adaptive notch filters, Kalman filters, phase-locked loops (PLLs), and frequency-locked loops (FLLs). Among these, the synchronous rotating coordinate system phase-locked loop (SRF-PLL) is the most widely used technology in three-phase power electronics and power system applications.

[0003] However, under conditions of power grid imbalance and distortion, the anti-interference performance of SRF-PLL is poor. To address this limitation, many improved SRF-PLL methods have been developed to increase detection speed while maintaining anti-interference capability in such situations. The basic idea behind these improvements is to introduce specific filtering elements within the control loop (in-loop filtering) or at the input (pre-filtering) to eliminate the main interference. Common filtering techniques include traditional low-pass filters (SLPF) with selective harmonic filtering capabilities, notch filters, second-order generalized integrators (SOGI), and complex bandpass filters (CBF). Coordinate system delay signal cancellation ( The PLL employs several filtering methods, including the dq coordinate system delay cancellation (dqDSC) operator and the multiple delay cancellation (MDSC) operator. These methods effectively reduce or eliminate specific types of interference, thereby improving the performance of PLLs under complex power grid conditions. However, when using existing PLL methods, frequency locking requires approximately two fundamental frequency cycles, which degrades the dynamic and steady-state performance of virtual inertial control.

[0004] In recent years, a faster frequency detection technique, frequency-locked loop (FLL), has been proposed and studied. FLL mainly consists of two key components: an orthogonal signal generator (OSG) and a frequency estimator. For three-phase signals, the OSG only requires the Clarke transform, making the frequency estimator even more crucial. Existing frequency estimators can be broadly classified into three categories: gradient descent (GD) based estimators, and those based on stationary frequency characteristics. Estimators operating in a reference coordinate system, and amplitude normalization estimators operating in a synchronously rotated dq reference coordinate system. These three types of frequency estimators have driven the development of various types of FLLs. A classic example is the ROGI-FLL based on the GD algorithm. Another well-known type is the Type-1 FLL, which employs a dq estimator.

[0005] However, given the unavoidable presence of harmonics and voltage imbalances in the mains grid, achieving efficient frequency locking using the aforementioned FLL still requires dedicated filters. But widely used filters (such as SLPF and SOGI) have certain limitations in practical scenarios. For example, in discrete systems operating at low sampling frequencies, the discrete errors generated by the integrators of SLPF and SOGI can hinder complete harmonic elimination, leading to frequency locking fluctuations. Similarly, in discrete systems, DSC filters cannot ensure that the delay corresponds to an integer sampling period; this phenomenon, known as rounding error, results in insufficient filtering. These limitations are particularly pronounced under conditions of low-order harmonics and unbalanced power grids. Summary of the Invention

[0006] In view of this, this application provides a frequency-locking loop and frequency-locking method for an adaptive delay signal cancellation filter, which solves the problem of discrete error or rounding error caused by the filter in discrete cases in the prior art, and realizes fast frequency detection with low steady-state fluctuations.

[0007] According to a first aspect of the embodiments of this application, a frequency-locked loop for an adaptive delay signal cancellation filter is provided, comprising:

[0008] The system comprises a first filter, a second filter, a Park transform module, a low-pass filter, an amplitude normalization module, an inverse Park transform module, a frequency estimation module, and a low-pass filter. The first filter is used for high-order harmonic cancellation, and the second filter is used for low-order single-harmonic cancellation.

[0009] For the first filter, the input signal is processed by time delay and rotation to obtain the first signal, and then the first signal is processed by time delay and rotation to obtain the second signal. The first composite vector is obtained by adding the input signal and the second signal. The harmonic compensation coefficient is introduced by quantitative calculation to make the h-th harmonic amplitude of the first signal equal to the h-th harmonic amplitude of the first composite vector. The h-th harmonic can be eliminated by subtracting them. Finally, the amplitude of the fundamental wave is restored by the fundamental wave compensation coefficient.

[0010] For the second filter, the input signal is processed by time delay and rotation to obtain the third signal, and the h-th harmonic component is processed by time delay and reverse rotation to obtain the fourth signal. The third signal and the input signal are added to obtain the second composite vector, and the fourth signal and the input signal are added to obtain the third composite vector. The third composite vector is rotated to make the two composite vectors have the same phase. Then, the harmonic compensation coefficient and the fundamental frequency compensation coefficient are used to eliminate the harmonics and keep the fundamental frequency unchanged.

[0011] The signal after passing through the filter is converted into a DC component in the dq coordinate system by the Park transform module, and then high-frequency noise is filtered out by the low-pass filter. It then enters the amplitude normalization module to normalize the signal amplitude to 1, and then passes through the inverse Park transform module to restore it to an AC signal. This AC signal is input into the frequency estimation module, and finally processed by the low-pass filter to obtain a stable power grid frequency estimate.

[0012] Optionally, for the first filter, the time delay and rotation angle include:

[0013] In discrete systems, a delay parameter is set. And satisfy ,in If the harmonic order to be eliminated is [number], then the rotation angle is [angle]. and delay time for:

[0014] ;

[0015] Delay period for:

[0016] ;

[0017] in Here, f is the system sampling frequency, and f is the fundamental frequency of the power grid.

[0018] Dynamic adjustment based on real-time feedback. And use rounding down to ensure Integer :

[0019] ;

[0020] Where floor represents rounding down. By incorporating a filter structure, the elimination While minimizing harmonics, rounding errors should also be avoided.

[0021] Optionally, for the first filter, the harmonic compensation coefficient and fundamental frequency compensation coefficient The calculation formula is as follows:

[0022] ;

[0023] In the formula: For intermediate functions, For harmonic compensation coefficients, The fundamental frequency compensation coefficient is... For delay parameters, The order of the harmonic to be eliminated. .

[0024] Optionally, for the second filter, the time delay and rotation angle include:

[0025] Set delay parameters Then the rotation angle and delay time All are:

[0026] ;

[0027] The number of delay cycles is:

[0028] ;

[0029] Dynamic adjustment based on real-time feedback. And use rounding down to ensure Integer :

[0030] ;

[0031] Will By incorporating a filter structure, the elimination While minimizing harmonics, rounding errors should also be avoided.

[0032] Optionally, for the second filter, the harmonic compensation coefficient and fundamental frequency compensation coefficient The calculation formula is as follows:

[0033] ;

[0034] In the formula, is intermediate function For harmonic compensation coefficients, The fundamental frequency compensation coefficient is... For delay parameters, The order of the harmonic to be eliminated.

[0035] According to a second aspect of the embodiments of this application, a frequency-locking method for an adaptive delay signal cancellation filter is provided. This method is implemented based on the frequency-locking loop of the adaptive delay signal cancellation filter described in the first aspect. The method includes the following steps:

[0036] S1: Real-time acquisition of three-phase power grid voltage signals The stationary state is obtained by Clarke transform. Voltage components in coordinate system ;

[0037] S2: Will Middle and high harmonics are eliminated in pairs through the first filter; Low- and mid-frequency single harmonics are eliminated using a second filter;

[0038] S3: The signal after filtering is converted into a DC component in the dq coordinate system by the Park transform module. Then, high-frequency noise is filtered out by a low-pass filter, and then the signal enters the amplitude normalization module to normalize the signal amplitude to 1.

[0039] S4: Then, the signal is restored to AC signal through the inverse Park transform module. ;

[0040] S5: Input the AC signal into the frequency estimation module, and after processing by the low-pass filter, obtain a stable power grid frequency estimate.

[0041] Alternatively, the normalization calculation method is as follows:

[0042] ;

[0043] In the formula The voltage component along the d-axis. The voltage component is the q-axis. The normalized d-axis voltage component. This represents the normalized q-axis voltage component.

[0044] Optionally, the frequency estimation module includes frequency calculation and error compensation using the backward difference method combined with Taylor series:

[0045] ;

[0046] ;

[0047] In the formula For normalized Axis voltage components, For normalized Axis voltage components, For the estimated frequency, The sampling frequency.

[0048] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0049] As can be seen from the above embodiments, this application adopts a dual-filter collaborative structure of adaptive delay signal cancellation (ATDSC), that is, the first filter is used for pairwise cancellation of high-order harmonics and the second filter is used for precise filtering of low-frequency single harmonics. This overcomes the contradiction between dynamic response and steady-state accuracy in traditional delay signal cancellation (DSC) filters and the performance degradation caused by rounding errors. In this way, it improves the technical effect of the first-order frequency locking loop in achieving high-precision frequency detection with low steady-state fluctuations while ensuring fast dynamic response.

[0050] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0052] Figure 1 The present invention provides a frequency-locked loop for an adaptive delay signal cancellation filter.

[0053] Figure 2 This is a block diagram of the ATDSC-1 filter;

[0054] Figure 3 The block diagram used to ensure the elimination of rounding errors for the ATDSC-1 filter;

[0055] Figure 4 This is a block diagram of the ATDSC-2 filter;

[0056] Figure 5 The block diagram used to ensure the elimination of rounding errors in the ATDSC-2 filter;

[0057] Figure 6 The experimental structure diagrams for two conventional methods are shown, where (a) is the experimental structure diagram of the conventional method DSC-FLL and (b) is the experimental structure diagram of the conventional method SLPF-FLL.

[0058] Figure 7 The experimental results and analysis figures of two traditional methods, DSC-FLL and SLPF-FLL, and the frequency-locked loop method ATDSC-FLL proposed in this application are shown. Among them, (a) is the steady-state experimental result figure of the two traditional methods, DSC-FLL and SLPF-FLL, and the proposed frequency-locked loop method ATDSC-FLL; (b) is the FFT analysis result of the steady-state experimental result figure of the two traditional methods, DSC-FLL and SLPF-FLL, and the proposed frequency-locked loop method ATDSC-FLL.

[0059] Figure 8The figure shows the experimental results of the 1Hz step dynamic response of two traditional methods, DSC-FLL and SLPF-FLL, and the proposed frequency-locked loop method, ATDSC-FLL.

[0060] Figure 9 The figures show the experimental results of the 12.5 Hz / s ramp response of two traditional methods, DSC-FLL and SLPF-FLL, and the proposed frequency-locked loop method, ATDSC-FLL.

[0061] Figure 10 The figures show the experimental results of the dynamic response of two traditional methods, DSC-FLL and SLPF-FLL, and the proposed frequency-locked loop method, ATDSC-FLL, at a 40° phase angle step. Detailed Implementation

[0062] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0063] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0064] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0065] refer to Figure 1This invention provides a frequency-locked loop for an adaptive delay signal cancellation filter, comprising: a first filter ATDSC-1, a second filter ATDSC-2, a Park transform module, a low-pass filter, an amplitude normalization module, an inverse Park transform module, a frequency estimation module, and a low-pass filter. The first filter ATDSC-1 is used for high-order harmonic cancellation, and the second filter ATDSC-2 is used for low-order single-harmonic cancellation.

[0066] For the first filter ATDSC-1, the input signal is processed by time delay and rotation to obtain the first signal, and then the first signal is processed by time delay and rotation to obtain the second signal. The first composite vector is obtained by adding the input signal and the second signal. The harmonic compensation coefficient is introduced by quantitative calculation to make the h-th harmonic amplitude of the first signal equal to the h-th harmonic amplitude of the first composite vector. The h-th harmonic can be eliminated by subtracting them. Finally, the amplitude of the fundamental wave is restored by the fundamental wave compensation coefficient.

[0067] For the second filter ATDSC-2, the input signal is processed by time delay and rotation to obtain the third signal, and the h-th harmonic component is processed by time delay and reverse rotation to obtain the fourth signal. The third signal and the input signal are added to obtain the second composite vector, and the fourth signal and the input signal are added to obtain the third composite vector. The third composite vector is rotated to make the two composite vectors have the same phase. Then, the harmonic compensation coefficient and the fundamental frequency compensation coefficient are used to eliminate the harmonics and keep the fundamental frequency unchanged.

[0068] The signal after passing through the filter is converted into a DC component in the dq coordinate system by the Park transform module, and then high-frequency noise is filtered out by the low-pass filter. It then enters the amplitude normalization module to normalize the signal amplitude to 1, and then passes through the inverse Park transform module to restore it to an AC signal. This AC signal is input into the frequency estimation module, and finally processed by the low-pass filter to obtain a stable power grid frequency estimate.

[0069] The first filter, ATDSC-1, will be explained in detail below.

[0070] Figure 2 The steps of the ATDSC-1 filter for discrete systems are shown below:

[0071]

[0072] in The number of sampling periods. The bit offset satisfies , For harmonic compensation coefficient, The fundamental frequency compensation coefficient is... Indicates delay and rotation The phase angle changes after the operation. For delay parameters, since Determine the delay time The value of , when The time delay is actually larger than that of the DSC filter, so it is meaningless. Therefore, it is defined here to satisfy the following condition: Harmonic compensation coefficient Used to ensure The amplitudes of the second harmonics are equal, and the fundamental frequency compensation coefficient is equal. This is used to ensure that the fundamental amplitude remains constant. The intermediate function in the calculation process is represented as:

[0073]

[0074] Will Through delay and rotation The signal obtained after the operation is ,Will The signal obtained after performing the same operation is Then we have:

[0075]

[0076] Will and Add and multiply by the coefficient The obtained signal is :

[0077]

[0078] because and The harmonic amplitudes and phases are the same; by subtracting them and multiplying by... This can eliminate harmonics and output a signal. for:

[0079]

[0080] The above process Discrete Only with It is relevant, but in the steps above There are no strict rules regarding the value of , only that... That's it. Therefore, it can be done through... Figure 3 The process utilizes f and f s and pre-set Calculate Then, using the calculated to replace Substitute Figure 2 In the filter structure to ensure The integer value is used to avoid rounding errors.

[0081] The second filter, ATDSC-2, will be explained in detail below.

[0082] Figure 4 This demonstrates the steps of the ATDSC-2 filter for discrete systems. The calculation process is similar to that of the ATDSC-1 filter. , , , and Unlike ATDSC-1, when filtering The following are examples of subharmonic frequencies:

[0083]

[0084] in The number of sampling periods. The bit offset satisfies , For harmonic compensation coefficient, The fundamental frequency compensation coefficient is... Indicates delay and rotation The phase angle changes after the operation. For delay parameters, This is an intermediate function used in the calculation process.

[0085] By formula Input to Figure 4 In the structure, the output signal It can be represented as:

[0086]

[0087] in The factor representing the amplitude of the residual harmonics is:

[0088]

[0089] It can be observed that this method cannot eliminate the problem in one go. Subharmonics and Secondary harmonics, and when it is necessary to eliminate them When the second harmonic is present, its output signal for

[0090]

[0091] and , , Values ​​and Filtering The second harmonic is different, and has the following characteristics:

[0092]

[0093] Same as ATDSC-1, It can be done as follows Figure 5 Obtained through this method, and has:

[0094]

[0095] Figure 6 In the middle (a) and (b), respectively, are the conventional method DSC-FLL and the conventional method SLPF-FLL, and the present application's... Figure 1 In comparison, the present application's block diagram consists of one ATDSC-2 filter, two ATDSC-1 filters, and a Type-1 frequency-locked loop structure. The method may include the following steps:

[0096] S1: Real-time acquisition of three-phase power grid voltage signals The stationary state is obtained by Clarke transform. Voltage components in coordinate system .

[0097] S2: Will Middle and high harmonics are eliminated in pairs through the first filter ATDSC-1; The low- and mid-frequency single harmonics are eliminated using the second filter ATDSC-2.

[0098] S3: The signal after filtering is converted into a DC component in the dq coordinate system by the Park transform module. Then, high-frequency noise is filtered out by a low-pass filter, and then the signal enters the amplitude normalization module to normalize the signal amplitude to 1.

[0099] S4: Then, the signal is restored to AC signal through the inverse Park transform module. The normalization method is as follows:

[0100]

[0101] In the formula The voltage component along the d-axis. The voltage component is the q-axis. The normalized d-axis voltage component. This represents the normalized q-axis voltage component.

[0102] S5: The AC signal is input to the frequency estimation module, and after processing by a low-pass filter, a stable power grid frequency estimate is obtained. The frequency estimation module includes frequency calculation and error compensation using the backward differential method combined with Taylor series.

[0103]

[0104] In the formula For normalized Axis voltage components, For normalized Axis voltage components, For the estimated frequency, The sampling frequency.

[0105] Figure 7 Figures (a) and (b) show the steady-state experimental results and FFT analysis results of two traditional methods, DSC-FLL and SLPF-FLL, and the proposed frequency-locked loop method, ATDSC-FLL, respectively. Figure 7 It can be seen that, compared with the two traditional FLL methods, ATDSC-FLL has smaller steady-state fluctuations and complete filtering of specific harmonics, without being affected by discretization error and rounding error.

[0106] Figure 8 , Figure 9 and Figure 10 The dynamic responses of the three methods are presented under 1Hz step, 12.5Hz / s ramp, and 40° phase angle jump conditions. It can be observed that under the 1Hz step condition, ATDSC-FLL exhibits the fastest response speed among all methods. This superior performance is mainly attributed to the use of the ATDSC-2 filter, which reduces the time delay for low-frequency harmonic cancellation, significantly improving its response speed. In the ramp response, since all methods are type I frequency-locked loops (FLLs), zero steady-state frequency error cannot be achieved. However, due to the superior dynamic characteristics of ATDSC-FLL, it still produces the smallest steady-state frequency error. In the phase angle jump scenario, ATDSC-FLL maintains its advantage of the fastest response speed and consistently outperforms other methods in transient characteristics.

[0107] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0108] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A frequency-locked loop for an adaptive delay signal cancellation filter, characterized in that, include: The system comprises a first filter, a second filter, a Park transform module, a low-pass filter, an amplitude normalization module, an inverse Park transform module, a frequency estimation module, and a low-pass filter. The first filter is used for high-order harmonic cancellation, and the second filter is used for low-order single-harmonic cancellation. For the first filter, the input signal is processed by time delay and rotation to obtain the first signal. The first signal is then processed by time delay and rotation to obtain the second signal. The first composite vector is obtained by adding the input signal and the second signal. Harmonic compensation coefficients are introduced through quantitative calculation to optimize the first signal. h The amplitude of the second harmonic and the first composite vector h The second harmonics can be eliminated by subtracting them from each other, since their amplitudes are equal. h The amplitude of the fundamental wave is finally restored by the fundamental wave compensation coefficient; For the second filter, the input signal is processed by time delay and rotation to obtain the third signal. h The fourth signal is obtained after the subharmonic component is processed by time delay and reverse rotation. The third signal and the input signal are added together to obtain the second composite vector. The fourth signal and the input signal are added together to obtain the third composite vector. The third composite vector is rotated to make the two composite vectors have the same phase. Then, the harmonic compensation coefficient and the fundamental wave compensation coefficient are used to eliminate the harmonics and keep the fundamental wave unchanged. The signal after passing through the filter is converted into a DC component in the dq coordinate system by the Park transform module, and then high-frequency noise is filtered out by the low-pass filter. It then enters the amplitude normalization module to normalize the signal amplitude to 1, and then passes through the inverse Park transform module to restore it to an AC signal. This AC signal is input into the frequency estimation module, and finally processed by the low-pass filter to obtain a stable power grid frequency estimate.

2. The frequency-locked loop of the adaptive delay signal cancellation filter according to claim 1, characterized in that, For the first filter, the time delay and rotation angle include: In discrete systems, a delay parameter is set. And satisfy ,in If the harmonic order to be eliminated is [the harmonic order], then the rotation angle is [the rotation angle]. and delay time for: ； Delay period for: ； in The system sampling frequency, f It is the fundamental frequency of the power grid; Through real-time feedback f Dynamic adjustment And use rounding down to ensure Integer : ； Where floor represents rounding down. By incorporating a filter structure, the elimination While minimizing harmonics, rounding errors should also be avoided.

3. The frequency-locked loop of the adaptive delay signal cancellation filter according to claim 1, characterized in that, For the first filter, the harmonic compensation coefficient and fundamental frequency compensation coefficient The calculation formula is as follows: ； In the formula: For intermediate functions, For harmonic compensation coefficients, The fundamental frequency compensation coefficient is... For delay parameters, The order of the harmonic to be eliminated. .

4. The frequency-locked loop of the adaptive delay signal cancellation filter according to claim 1, characterized in that, For the second filter, the time delay and rotation angle include: Set delay parameters Then the rotation angle and delay time All are: ； The number of delay cycles is: ； Through real-time feedback f Dynamic adjustment And use rounding down to ensure Integer : ； Will By incorporating a filter structure, the elimination While minimizing harmonics, rounding errors should also be avoided.

5. The frequency-locked loop of an adaptive delay signal cancellation filter according to claim 1, characterized in that, For the second filter, the harmonic compensation coefficient and fundamental frequency compensation coefficient The calculation formula is as follows: ； In the formula, is intermediate function For harmonic compensation coefficients, The fundamental frequency compensation coefficient is... For delay parameters, The order of the harmonic to be eliminated.

6. A frequency-locking method for an adaptive delay signal cancellation filter, characterized in that, This method is based on the frequency-locked loop of the adaptive delay signal cancellation filter described in claim 1, and includes the following steps: S1: Real-time acquisition of three-phase power grid voltage signals The stationary state is obtained by Clarke transformation. Voltage components in coordinate system ; S2: Will Middle and high harmonics are eliminated in pairs through the first filter; Low- and mid-frequency single harmonics are eliminated using a second filter; S3: The signal after filtering is converted into a DC component in the dq coordinate system by the Park transform module. Then, high-frequency noise is filtered out by a low-pass filter, and then the signal enters the amplitude normalization module to normalize the signal amplitude to 1. S4: Then, the signal is restored to AC signal through the inverse Park transform module. ; S5: Input the AC signal into the frequency estimation module, and after processing by the low-pass filter, obtain a stable power grid frequency estimate.

7. The frequency locking method for an adaptive delay signal cancellation filter according to claim 6, characterized in that, The normalization calculation method is as follows: ； In the formula for d Axis voltage components, for q Axis voltage components, For normalized d Axis voltage components, For normalized q Axis voltage component.

8. The frequency locking method for an adaptive delay signal cancellation filter according to claim 6, characterized in that, The frequency estimation module includes frequency calculation and error compensation using the backward difference method combined with Taylor series: ； ； In the formula For normalized Axis voltage components, For normalized Axis voltage components, For the estimated frequency, The sampling frequency.

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