A CAN bus wake-up device and CAN bus communication chip
By designing a CAN bus wake-up device and using a logic processing unit and a delay unit to control the enable signal of the RC oscillator, the high power consumption and information loss problems caused by the RC oscillator being constantly on are solved, achieving a balance between low power consumption and information integrity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI GUOXINWEI HIGH-TECH CO LTD
- Filing Date
- 2025-12-15
- Publication Date
- 2026-07-31
AI Technical Summary
The existing CAN bus specific frame wake-up scheme cannot further reduce power consumption because the RC oscillator is always on, and there will be cases of information loss during the time when the RC oscillator clock is stable.
A CAN bus wake-up device is designed, including a CAN simulation unit, a first logic processing unit, an enable unit, an RC oscillator, a delay unit, a first decoding unit, a second decoding unit, and a second logic processing unit. By controlling the enable signal of the RC oscillator and the delay time of the delay unit, power consumption is reduced in the CAN bus idle state, and complete CAN bus information is output when the state changes.
This approach achieves reduced power consumption in a specific frame wake-up scheme for the CAN bus while avoiding information loss and ensuring information integrity and real-time performance.
Smart Images
Figure CN121356937B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of CAN bus wake-up technology, specifically to a CAN bus wake-up device and a CAN bus communication chip. Background Technology
[0002] The CAN communication protocol was developed by Bosch in Germany in 1986 to solve the problem of efficient and reliable communication between electronic control units (ECUs) in automobiles, and has become an international standard (ISO 11898). It adopts a multi-master structure and a non-destructive arbitration mechanism, and resolves bus access conflicts based on message identifier priority to ensure the real-time transmission of high-priority information.
[0003] In CAN communication, CAN specific frame wake-up is an efficient low-power management mechanism for the CAN bus, implemented based on the CAN 2.0 protocol. It allows CAN application nodes in sleep mode to respond only to pre-configured specific identifiers (such as specific remote frames), rather than any frame on the bus. Its working principle is to perform hardware filtering through registers and masks within the CAN transceiver, and only trigger the local power management circuit to exit sleep mode when the target frame is detected.
[0004] In practical applications, CAN specific frame wake-up significantly reduces the invalid wake-up and power consumption caused by traditional "arbitrary frame wake-up," effectively reducing system standby power consumption and bus load, which is of great significance for extending the driving range of electric vehicles. For existing CAN bus communication chips, the internal clock is implemented by an RC oscillator. When the RC oscillator is turned on, the chip incurs analog circuit power consumption and clock tree power consumption in the digital circuit before clock gating. Compared to arbitrary frame wake-up, CAN specific frame wake-up requires a clock signal provided by the RC oscillator to keep the digital circuit running for logic parsing. Therefore, in existing CAN specific frame wake-up technology, the chip power consumption cannot be further reduced because the RC oscillator is turned on; in addition, the clock needs a stabilization time after the RC oscillator turns off, and during this time when the clock is unavailable, the CAN bus is already transmitting data, resulting in lost information and inability to parse frames. Summary of the Invention
[0005] In view of the shortcomings of the prior art, the present invention provides a CAN bus wake-up device and a CAN bus communication chip. The technical problem to be solved is that the existing CAN bus specific frame wake-up scheme cannot further reduce power consumption because the RC oscillator is always on. Moreover, if the RC oscillator is turned off, there will be a loss of transmitted information during the time when the RC oscillator clock is stable.
[0006] To solve the above technical problems, the present invention provides the following technical solution: a CAN bus wake-up device, comprising a CAN simulation unit, a first logic processing unit, an enable unit, an RC oscillator, a delay unit, a first decoding unit, a second decoding unit, and a second logic processing unit; The CAN analog unit is used to convert the two input differential signals into digital signals, and the digital signals are respectively input to the first logic processing unit, the delay unit and the first decoding unit; The first logic processing unit inputs a control signal to the enable unit based on the level state of the digital signal. The enable unit inputs an enable signal to the RC oscillator based on the control signal. After receiving the enable signal, the RC oscillator inputs clock signals to the first logic processing unit, the enable unit, the first decoding unit, the second decoding unit, and the second logic processing unit, respectively. The first decoding unit is used to decode the input digital signal and output real-time decoding information; The delay unit is used to delay the digital signal and input the delayed digital signal to the second decoding unit, and the delay time of the delay unit is greater than the start time of the RC oscillator; The second decoding unit is used to decode the delayed digital signal and output delayed decoding information; The second logic processing unit is electrically connected to the first decoding unit and the second decoding unit respectively, and outputs complete CAN bus information based on the real-time decoding information and the delayed decoding information.
[0007] In one implementation, the first logic processing unit counts the high-level state time of the digital signal when the digital signal is in a high-level state, and inputs a low-level control signal to the enable unit when the counting time is greater than a set time. When the digital signal is in a low-level state, the first logic processing unit inputs a high-level control signal to the enable unit.
[0008] In one embodiment, the enabling unit outputs an enabling signal when the control signal is high, and stops outputting the enabling signal when the control signal is low.
[0009] In one embodiment, the enabling unit includes a D flip-flop, the D input of which is used to input the control signal, the clock input of which is used to input the clock signal, the set input of which is used to input the digital signal, and the Q output of which is electrically connected to the RC oscillator and used to output the enabling signal.
[0010] In one implementation, the set time is adjustable.
[0011] In one embodiment, the CAN simulation unit also inputs an ACK drive signal and outputs a low-level digital signal when the ACK drive signal is input; the ACK drive signal is taken from the complete CAN bus information and is in a low-level state.
[0012] In one embodiment, the second logic processing unit performs correlation analysis on the real-time decoding information and the delayed decoding information to obtain the number of delayed bytes X of the real-time decoding information, and then combines the latest X bit information of the real-time decoding information with the delayed decoding information to obtain the complete CAN bus information.
[0013] In one implementation, the second logic processing unit performs correlation analysis on the real-time decoding information and the delayed decoding information to obtain the number of delayed bytes X of the real-time decoding information as follows: S1: Delay the currently parsed Y-bit real-time decoding information by one bit, where Y is a positive integer, to obtain Y+1 bits of processing decoding information. At the same time, increment the number of delayed bytes by 1. The initial value of the number of delayed bytes is 0. S2: Determine whether the processed decoding information matches the current delayed decoding information. The matching is along the parsing order. Determine whether the last Y bits of the processed decoding information are the same as the corresponding Y bits of delayed decoding information. If they are the same, end step S2 and obtain the final number of delayed bytes. Otherwise, return to step S1.
[0014] In one implementation, the Y-bit real-time decoding information in step S1 includes at least a portion of the CRC segment information from the CAN information.
[0015] In addition, the present invention also provides a CAN bus communication chip, which includes the aforementioned CAN bus wake-up device.
[0016] The beneficial effects of this invention compared to the prior art are: First, the first logic processing unit processes the level of the digital signal output by the CAN analog unit. Then, the enable unit controls whether the RC oscillator outputs a clock. In this way, when the CAN bus is in an idle state, that is, when the digital signal is at a high level for a long time, the RC oscillator can stop outputting a clock, thereby reducing power consumption. Secondly, when the CAN bus changes from idle to active state, the level of the digital signal changes. The first logic processing unit controls the RC oscillator to output a clock based on the digital signal of the level change through the enable unit, so that the device can transmit information. At this time, the delay unit can delay to avoid the loss of digital signal. The second logic processing unit processes the real-time decoding information and the delayed decoding information to output complete CAN bus information, which can ensure the integrity of CAN bus information. Attached Figure Description
[0017] Figure 1 This is the complete CAN2.0 information frame format; Figure 2 This is a schematic diagram of the CAN bus wake-up device in Embodiment 1; Figure 3 This is a waveform diagram of data analysis when performing interchangeability analysis on the second logic processing unit in Example 1. Detailed Implementation
[0018] The illustrative embodiments of this application include, but are not limited to, a CAN bus wake-up device and a CAN bus communication chip.
[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0020] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Words such as “comprising” or “including” mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and does not exclude other elements or objects. Words such as “connected” or “linked” are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.
[0021] First, the information frame format of CAN2.0 will be explained, such as... Figure 1As shown, the Start of Frame (SOF) of CAN information is fixed at 1 bit of 0; the subsequent data from ID to DATA contains valid information; CRC checks all data values from SOF to DATA; CRCL is fixed at 1 bit of 1, ACK is fixed at 1 bit of 0, ACKL is fixed at 1 bit of 1, and the End of Frame (EOF) is fixed at 7 bits of 1. The 1 bit of 0 in ACK is driven by the receiver and used to feedback the reception status to the sender; a successful reception returns 0, and a failure returns 1. Additionally, in this segment, 0 represents a low-level signal, and 1 represents a high-level signal.
[0022] During non-transmission frames in CAN, the bus remains at a high level (1). After the frame begins, the bus changes from 1 to 0 (from high to low). Due to the bit-stuffing mechanism of the CAN protocol, no more than five consecutive bits with the same value are allowed before the CRCL segment. Therefore, the bus remaining at 1 for an extended period only occurs during the 7-bit End-of-Frame (EOF) segment and during non-transmission frames.
[0023] Therefore, a bus value of 0 can be used as the clock generation condition for the RC oscillator, and a bus value of 1 for too long can be used as the clock stopping condition for the RC oscillator, thereby enabling the RC oscillator's clock to follow the CAN frame.
[0024] In order to further reduce power consumption by disabling the RC oscillator in the CAN bus specific frame wake-up scheme, and to prevent loss of transmitted information during the time when the RC oscillator clock is stable, this embodiment provides a CAN bus wake-up device, wherein the design concept of the CAN bus wake-up device is generated from the CAN2.0 information frame format.
[0025] In this embodiment, the structure of the CAN bus wake-up device is as follows: Figure 2 As shown, it includes a CAN simulation unit 1, a first logic processing unit 2, an enable unit 6, an RC oscillator 7, a delay unit 3, a first decoding unit 4, a second decoding unit 5, and a second logic processing unit 8.
[0026] The CAN analog unit 1 is used to convert the two input differential signals into digital signals, and the digital signals are respectively input to the first logic processing unit 2, the delay unit 3 and the first decoding unit 4; The first logic processing unit 2 inputs a control signal CON to the enable unit 6 based on the level state of the digital signal. The enable unit 6 inputs an enable signal EN to the RC oscillator 7 based on the control signal CON. After receiving the enable signal EN, the RC oscillator 7 inputs a clock signal CLK to the first logic processing unit 2, the enable unit 6, the first decoding unit 4, the second decoding unit 5, and the second logic processing unit 8, respectively. The clock signal CLK is used to control the operation of the first logic processing unit 2, the enable unit 6, the first decoding unit 4, the second decoding unit 5, and the second logic processing unit 8. The first decoding unit 4 is used to decode the input digital signal and output real-time decoding information; The delay unit 3 is used to delay the digital signal and input the delayed digital signal to the second decoding unit 5. The delay time of the delay unit 3 is greater than the start-up time of the RC oscillator 7. By ensuring that the delay time of the delay unit 3 is greater than the start-up time of the RC oscillator, it is possible to ensure that the delayed digital signal input to the second decoding unit 5 is complete and correct, without any loss. In addition, in some embodiments, the delay time of the delay unit 3 is adjustable and is not necessarily a fixed value. It should be further noted that in actual use, the delay unit 3 is not a digital timing circuit, and its actual delay time will be affected by many factors such as temperature, voltage, and process deviation. In order to ensure that the complete CAN bus information is finally parsed, the minimum delay time of the delay unit 3 in the changing working environment needs to be greater than the start-up time of the RC oscillator 7. The second decoding unit 5 is used to decode the delayed digital signal and output the delayed decoding information; The second logic processing unit 8 is electrically connected to the first decoding unit 4 and the second decoding unit 5 respectively, and outputs complete CAN bus information based on real-time decoding information and delayed decoding information.
[0027] In this embodiment, the four-way structure design of the delay unit 3, the first decoding unit 4, and the second decoding unit 5 is as follows: Because the CAN protocol uses non-return-to-zero (NRZ) encoding, the decoding unit must rely on the timing of edge changes to synchronize with the CAN bus and parse information. Without a clock, the decoding unit cannot recognize the falling edge of the SOF (Self-of-Flight) transitioning from 1 to 0 at the start of a frame and loses synchronization. However, due to the bit stuffing mechanism, the edge will inevitably change again within 5 bits, so the decoding unit can resynchronize with the bus using the next edge change. The maximum information loss is the clock startup time plus a maximum of 5 bits. Therefore, in this embodiment, the CAN bus is delayed by the delay unit 3 to a delay exceeding the clock startup time before being input to the second decoding unit 5, thus obtaining the complete information at the start of the frame.
[0028] In practical use, the CAN bus wake-up device in this embodiment processes the level state of the digital signal output by the CAN analog unit 1 by setting the first logic processing unit 2, and then controls whether the RC oscillator 7 outputs the clock signal CLK by the enable unit 6. In this way, when the CAN bus is in an idle state, that is, when the digital signal is at a high level for a long time, the RC oscillator 7 can stop outputting the clock signal CLK, thereby reducing power consumption. Secondly, when the CAN bus changes from idle to active state, the level of the digital signal changes. The first logic processing unit 2 controls the RC oscillator 7 to output a clock based on the digital signal of the level change through the enable unit 6, so that the device can transmit information. At this time, the delay unit 3 can delay the digital signal to avoid loss. The second logic processing unit 8 processes the real-time decoding information and the delayed decoding information to output complete CAN bus information, which can ensure the integrity of the CAN bus information.
[0029] More specifically, in this embodiment, the process by which the first logic processing unit 2 processes the digital signal output by the CAN analog unit 1 is as follows: The first logic processing unit 2 counts the high-level state time of the digital signal when the digital signal is in a high-level state, and inputs a low-level control signal to the enable unit 6 when the counting time is longer than the set time. When the digital signal is at a low level, the first logic processing unit 2 inputs a high-level control signal CON to the enable unit 6.
[0030] In some implementations, the set time is adjustable and is not necessarily a fixed value.
[0031] In one implementation, the digital signal can also be input to the first logic processing unit 2 via an inverter. Correspondingly, when the first logic processing unit 2 inputs a low-level signal, it counts the low-level state time and inputs a low-level control signal to the enable unit 6 when the count time is greater than a set time. When the input signal is at a high level, the first logic processing unit 2 inputs a high-level control signal CON to the enable unit 6.
[0032] In this embodiment, the process by which the enabling unit 6 outputs the enabling signal EN based on the control signal CON is as follows: Enable unit 6 outputs enable signal EN when control signal CON is high, and stops outputting enable signal EN when control signal CON is low.
[0033] Furthermore, in this implementation, Figure 2In the above, the enable unit 6 includes a D flip-flop. The D input of the D flip-flop is used to input the control signal CON, the clock input of the D flip-flop is used to input the clock signal CLK, the set input of the D flip-flop is used to input the digital signal, and the Q output of the D flip-flop is electrically connected to the RC oscillator 7 to output the enable signal EN.
[0034] Specifically, in this embodiment, the CAN analog unit 1 also inputs an ACK drive signal and outputs a low-level digital signal when the ACK drive signal is input; the ACK drive signal is taken from complete CAN bus information and is in a low-level state.
[0035] In practical use, the real-time decoding information without delay is incomplete, so it is unknown whether the frame is complete and correct; the delayed decoding information is complete, but there is a delay relative to the bus; neither can reliably and timely return ACK. Therefore, it is necessary to obtain a complete and real-time CAN frame based on the real-time decoding information and the delayed decoding information before the ACK return time; in addition, the first edge detected by the delay path composed of delay unit 3 and the second decoding unit 5 is random in which bit, and the actual delay time of delay unit 3 is also random. Based on the above two considerations, in order to obtain complete CAN bus information, in this embodiment, the second logic processing unit 8 performs correlation analysis on the real-time decoding information and the delayed decoding information to obtain the number of delayed bytes X of the real-time decoding information, and then combines the latest X bit information of the real-time decoding information with the delayed decoding information to obtain complete CAN bus information.
[0036] More specifically, in this embodiment, the second logic processing unit 8 performs correlation analysis on the real-time decoding information and the delayed decoding information to obtain the number of delayed bytes X of the real-time decoding information as follows: S1: Delay the currently parsed Y-bit real-time decoding information by one bit, where Y is a positive integer, to obtain Y+1 bits of processing decoding information. At the same time, increment the number of delayed bytes by 1. The initial value of the number of delayed bytes is 0. S2: Determine whether the processed decoding information matches the current delayed decoding information. If they match, it means following the parsing order. Determine whether the last Y bits of the processed decoding information are the same as the corresponding Y bits of delayed decoding information. If they are the same, end step S2 and obtain the final number of delayed bytes. Otherwise, return to step S1.
[0037] For example, the process of performing correlation analysis on real-time decoding information and delayed decoding information is as follows: Figure 3 As shown, Figure 3 The horizontal axis represents the time axis, and the vertical axis represents the waveform of each frame decoding. Each small square on the horizontal axis represents the duration of 1 bit at the CAN baud rate.
[0038] exist Figure 3In the process, the CAN frame begins at time T=2, and RC oscillator 7 is enabled to output clock signal CLK. The clock stabilization time of this RC oscillator 7 is 1.5T, and the clock becomes valid at time T=3.5. The first decoding unit 4 detects the first edge after the clock signal CLK is valid, i.e., at time T=6, and begins parsing the frame data. Additionally, delay unit 3 creates a 3.5T delay, so the second decoding unit 5 begins parsing the frame data at time T=5.5. Assuming the first 7 bits decoded by the first decoding unit 4 are 0010110, and the first 12 bits decoded by the second decoding unit are 01110010110, it should be noted that these 7 and 12 bits are examples, and in reality, they will continue until the ACK. In the actual correlation analysis, the decoding result of the first decoding unit 4 is delayed by 1T, then the result of the first 8 bits is x0010110, and the equivalent waveform is delayed by 1T. At this time, the number of delayed bytes is 1. Since the last seven bits of x0010110 are not completely the same as 01110010110 when compared with the parsing order; Therefore, if the decoding result of the first decoding unit 4 is delayed by 2T, the result of the first 9 bits is xx0010110, and the equivalent waveform is delayed by 2T. At this time, the number of delayed bytes is 2. Since the last seven bits of xx0010110 are not completely the same as 01110010110 when compared along the parsing order, if the decoding result of the first decoding unit 4 is delayed by 3T, the result of the first 10 bits is xxx0010110, and the equivalent waveform is delayed by 3T. At this time, the number of delayed bytes is 3. Since the last seven bits of xxx0010110 are not completely the same as 01110010110 when compared along the parsing order, the number of delayed bytes is 3. Therefore, the decoding result of the first decoding unit 4 is delayed by 4T, resulting in the first 11 bits being xxxx0010110, with an equivalent waveform delayed by 4T. The number of delayed bytes is 4, and the last seven bits of xxxx0010110 are identical to 01110010110 in the parsing order. After obtaining the number of delayed bytes, the second logic processing unit 8 combines the latest 4 bits decoded by the first decoding unit 4 with all bits of all delayed decoding information output by the second decoding unit to obtain complete and real-time CAN frame information, thus ensuring the timeliness of the ACK return.
[0039] In addition, when performing correlation analysis, the decoding result of the first decoding unit 4, i.e., the real-time decoding information, must include at least a portion of the CRC segment content of the CAN protocol. This is to avoid the situation where the decoding result of the first decoding unit 4 and the decoding result of the second decoding unit are mistakenly the same when performing correlation analysis due to data coincidence.
[0040] Example 2 This embodiment provides a CAN bus communication chip, which includes the CAN bus wake-up device from Embodiment 1. Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.
Claims
1. A CAN bus wake-up device, characterized in that, It includes a CAN simulation unit, a first logic processing unit, an enable unit, an RC oscillator, a delay unit, a first decoding unit, a second decoding unit, and a second logic processing unit; The CAN analog unit is used to convert the two input differential signals into digital signals, and the digital signals are respectively input to the first logic processing unit, the delay unit and the first decoding unit; The first logic processing unit inputs a control signal to the enable unit based on the level state of the digital signal. The enable unit inputs an enable signal to the RC oscillator based on the control signal. After receiving the enable signal, the RC oscillator inputs clock signals to the first logic processing unit, the enable unit, the first decoding unit, the second decoding unit, and the second logic processing unit, respectively. The first decoding unit is used to decode the input digital signal and output real-time decoding information; The delay unit is used to delay the digital signal and input the delayed digital signal to the second decoding unit, and the delay time of the delay unit is greater than the start time of the RC oscillator; The second decoding unit is used to decode the delayed digital signal and output delayed decoding information; The second logic processing unit is electrically connected to the first decoding unit and the second decoding unit respectively, and outputs complete CAN bus information based on the real-time decoding information and the delayed decoding information.
2. The CAN bus wake-up device according to claim 1, characterized in that, The first logic processing unit counts the high-level state time of the digital signal when the digital signal is in a high-level state, and inputs a low-level control signal to the enable unit when the counting time is greater than a set time. When the digital signal is in a low-level state, the first logic processing unit inputs a high-level control signal to the enable unit.
3. A CAN bus wake-up device according to claim 2, characterized in that, The enabling unit outputs an enabling signal when the control signal is high, and stops outputting the enabling signal when the control signal is low.
4. A CAN bus wake-up device according to claim 3, characterized in that, The enabling unit includes a D flip-flop, the D input of which is used to input the control signal, the clock input of which is used to input the clock signal, the set input of which is used to input the digital signal, and the Q output of which is electrically connected to the RC oscillator and used to output the enabling signal.
5. A CAN bus wake-up device according to claim 2, characterized in that, The set time is adjustable.
6. A CAN bus wake-up device according to claim 1, characterized in that, The CAN simulation unit also receives an ACK drive signal and outputs a low-level digital signal when the ACK drive signal is received; the ACK drive signal is taken from the complete CAN bus information and is in a low-level state.
7. A CAN bus wake-up device according to claim 1, characterized in that, The second logic processing unit performs correlation analysis on the real-time decoding information and the delayed decoding information to obtain the number of delayed bytes X of the real-time decoding information. Then, it combines the latest X bit information of the real-time decoding information with the delayed decoding information to obtain the complete CAN bus information.
8. A CAN bus wake-up device according to claim 7, characterized in that, The second logic processing unit performs correlation analysis on the real-time decoding information and the delayed decoding information to obtain the number of delayed bytes X of the real-time decoding information as follows: S1: Delay the currently parsed Y-bit real-time decoding information by one bit, where Y is a positive integer, to obtain Y+1 bits of processing decoding information. At the same time, increment the number of delayed bytes by 1. The initial value of the number of delayed bytes is 0. S2: Determine whether the processed decoding information matches the current delayed decoding information. The matching is along the parsing order. Determine whether the last Y bits of the processed decoding information are the same as the corresponding Y bits of delayed decoding information. If they are the same, end step S2 and obtain the final number of delayed bytes. Otherwise, return to step S1.
9. A CAN bus wake-up device according to claim 8, characterized in that, The Y-bit real-time decoding information in step S1 includes at least a portion of the CRC segment information from the CAN information.
10. A CAN bus communication chip, characterized in that, The CAN bus communication chip includes the CAN bus wake-up device as described in any one of claims 1-9.