A shielded gate trench VDMOS field plate manufacturing method, system and structure

Abstract

The present application relates to the technical field of semiconductor devices, and particularly relates to a shield gate trench VDMOS field plate preparation method, system and structure. At present, the large depth-width ratio of the trench of the VDMOS device makes it easy to appear bottom filling pores and through-trench gaps in the gap filling process of the shield gate polysilicon, and the gaps lead to the formation of fork-shaped topography of the shield gate polysilicon in the subsequent etching process. The present application performs rapid thermal annealing on the original polysilicon layer, promotes the grain growth in the original polysilicon layer by using the rapid high-temperature annealing technology, eliminates the pore and gap topography defects in the polysilicon deposition process, obtains a seamless, flat and dense large-grain polysilicon layer, so that the subsequent etching of the large-grain polysilicon layer will not form a V-shaped topography, and finally a flat and dense shield gate polysilicon layer is obtained to avoid the formation of fork-shaped topography, so as to improve the electric field distribution quality near the shield gate and improve the performance and quality of the VDMOS device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method, system and structure for fabricating a shielded gate trench VDMOS field plate. Background Technology

[0002] In the field of power metal-oxide-semiconductor field-effect transistors (MOSFETs), vertical double-diffused metal-oxide-semiconductor (VDMOS) devices with shielded gate trench (SGT) structures have attracted widespread attention due to their superior electrical characteristics. These devices, by introducing a shielded gate structure at the bottom of the trench, achieve a more uniform current distribution at the trench bottom compared to traditional planar trench power devices, thereby reducing the on-resistance and switching losses and improving overall performance. With the continuous development of process technology, in pursuit of even lower on-resistance, the trench pitch of existing VDMOS devices has been continuously reduced, resulting in a corresponding decrease in trench size (CD) and a further increase in trench aspect ratio. This poses a significant challenge to the filling process of the shielded gate polysilicon.

[0003] Under current process conditions, the excessively large trench aspect ratio of VDMOS devices easily leads to bottom-fill voids and through-trenches during the filling process of the polysilicon gap in the shield gate. These voids cause fork-shaped morphologies to frequently form on the top of the shield gate polysilicon during subsequent etching processes. This fork-shaped morphology further reduces the oxide layer thickness between the shield gate polysilicon and the gate polysilicon, severely affecting the leakage current characteristics between the source and gate in SGT VDMOS devices and interfering with the electric field distribution near the shield gate, ultimately leading to deterioration of the device's electrical parameters. Therefore, there is an urgent need in the art for a technical solution that can improve the top morphology of the shield gate in SGT VDMOS devices under low specific on-resistance conditions, in order to improve the performance and quality of SGT VDMOS devices. Summary of the Invention

[0004] The present invention aims to provide a method, system and structure for fabricating a shielded gate trench VDMOS field plate, in order to eliminate the fork-shaped morphological defects at the top of the shielded gate, thereby improving the performance and quality of the SGT VDMOS device.

[0005] To achieve the above objectives, a first aspect of the present invention provides a method for fabricating a shielded gate trench VDMOS field plate, comprising:

[0006] A substrate is provided, and an epitaxial layer is formed on the surface of the substrate;

[0007] Etch shielding trenches in the epitaxial layer;

[0008] A first oxide layer is formed on the surface of the epitaxial layer, and a second oxide layer is formed on the surface of the shielding gate trench;

[0009] A raw polysilicon layer is deposited in the shielding trench, the raw polysilicon layer having a gap morphology;

[0010] The original polycrystalline silicon layer is subjected to rapid thermal annealing to eliminate the gap morphology and form a large-grain polycrystalline silicon layer.

[0011] The large-grain polycrystalline silicon layer is etched back to form a shielding gate polycrystalline silicon layer;

[0012] Etch the first oxide layer and the second oxide layer to form a field oxide layer;

[0013] An interlayer oxide layer is formed on the surface of the field oxide layer and the shielding gate polysilicon layer, and a needle-like morphology is formed at the top of the shielding gate polysilicon layer;

[0014] A gate oxide layer is formed on both the surface of the epitaxial layer and the sidewalls of the shielding gate trench;

[0015] A gate polysilicon layer is deposited on the surface of both the interlayer oxide layer and the gate oxide layer.

[0016] It should be noted that when the aspect ratio of the shielding gate trench is too large, a gap morphology will appear in the original polysilicon layer, penetrating the polysilicon layer. This gap morphology causes the etching gas to penetrate along the gap morphology when the original polysilicon layer is etched back to form the shielding gate polysilicon layer, forming a V-shaped morphology at the top of the shielding gate polysilicon layer. This gap morphology and V-shaped morphology cause a fork-like morphology at the top of the shielding gate polysilicon layer when the interlayer oxide layer is subsequently formed on the surface of the field oxide layer and the shielding gate polysilicon layer, severely affecting the leakage current performance between the source and gate in the SGT VDMOS device. Therefore, the aforementioned VDMOS field plate fabrication method employs a rapid thermal annealing process on the original polysilicon layer. This rapid high-temperature annealing technology promotes grain growth in the original polysilicon layer, eliminating porosity and seam morphology defects from the polysilicon deposition process. This results in a seamless, flat, and dense large-grain polysilicon layer. This prevents the formation of V-shaped morphologies during subsequent etch-back of the large-grain polysilicon layer, ultimately resulting in a flat and dense shielding gate polysilicon layer that avoids fork-like morphologies and instead forms a needle-like morphology. This improves the electric field distribution quality near the shielding gate and enhances the performance and quality of the VDMOS device. Specifically, the needle-like morphology effectively improves the electric field distribution quality near the shielding gate and enhances the performance and quality of the VDMOS device.

[0017] Further, the rapid thermal annealing of the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer includes:

[0018] The original polycrystalline silicon layer is subjected to rapid thermal annealing to recrystallize the original polycrystalline silicon layer, thereby causing the grains in the original polycrystalline silicon layer to grow and fill the gap morphology, forming a large-grain polycrystalline silicon layer.

[0019] It should be noted that Rapid Thermal Annealing (RTA) is a processing technique that uses high-intensity light or infrared radiation to rapidly heat up and cool down the surface of a material. This invention has found that when polycrystalline silicon is heated using RTA, the grain structure in the polycrystalline silicon recrystallizes. Furthermore, as the annealing temperature increases, the recrystallization rate of the grain structure in the polycrystalline silicon accelerates, and the grain size gradually increases. This fills and eliminates the gaps in the polycrystalline silicon layer, forming a flat and dense large-grain polycrystalline silicon layer. This method utilizes rapid high-temperature annealing technology to promote polycrystalline silicon grain growth and eliminate porosity and defects during the polycrystalline silicon deposition process. Eliminating the filling porosity before etching the shielding gate prevents etching gas from drilling along the gaps. During etching at the top of the shielding gate, the morphology changes from a V-shape to a flat morphology, which in turn causes the subsequent shielding gate oxide layer to change from a fork-shaped morphology to a needle-like morphology during the formation of the sacrificial oxide layer and the gate oxide layer. This improves the quality of the electric field distribution near the shielding gate and enhances the performance and quality of the VDMOS device.

[0020] Furthermore, before performing rapid thermal annealing on the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer, the process further includes:

[0021] The original polycrystalline silicon layer is subjected to chemical mechanical polishing to obtain a first polycrystalline silicon layer, which is then used as the original polycrystalline silicon layer.

[0022] It should be noted that the surface of the original polysilicon layer formed in trenches with high aspect ratios may have uneven morphology, which can easily lead to unevenness on the surface of the polysilicon layer formed during subsequent etch-back, affecting the electrical performance of the VDMOS device. Furthermore, the large-grain polysilicon layer formed after rapid thermal annealing has a denser grain structure, making chemical mechanical polishing (CMP) even more difficult. Therefore, this implementation first performs CMP on the original polysilicon layer before rapid thermal annealing and etch-back to make its surface smooth, which is beneficial for the subsequent formation of a smooth shielding gate oxide layer. This improves the quality of the electric field distribution near the shielding gate and enhances the performance and quality of the VDMOS device.

[0023] Further, the step of forming an interlayer oxide layer on the surface of the field oxide layer and the shielding gate polysilicon layer, and forming a needle-like morphology at the tip of the shielding gate polysilicon layer, includes:

[0024] A sacrificial oxide layer is deposited on the surface of the epitaxial layer, the surface of the shielding gate polysilicon layer, and the sidewall of the shielding gate trench using a thin film deposition process, and a needle-like morphology is formed at the top of the shielding gate polysilicon layer.

[0025] The sacrificial oxide layer is etched to remove excess sacrificial oxide layer covering the surface of the epitaxial layer and the sidewalls of the shielding gate trench, thereby forming the interlayer oxide layer.

[0026] This implementation simultaneously deposits sacrificial oxide layers on both the surface of the shielding gate polysilicon layer and the sidewalls of the shielding gate trench in a single thin-film deposition process. The sacrificial oxide layer on the surface of the shielding gate polysilicon layer acts as an interlayer oxide layer to isolate the shielding gate polysilicon and the gate polysilicon, preventing short circuits and leakage between them. This ensures the leakage characteristics between the source and gate in the VDMOS device, thereby improving the performance and quality of the VDMOS device. Depositing the sacrificial oxide layer on the sidewalls of the shielding gate trench removes damage and defects, facilitating the subsequent formation of a high-quality gate oxide layer on the sidewalls. This further improves the electric field distribution quality near the shielding gate and enhances the performance and quality of the VDMOS device.

[0027] Meanwhile, in a specific embodiment of this implementation, since the shielding gate polysilicon layer forms a dense and flat large-grain structure after rapid thermal annealing, when a sacrificial oxide layer is deposited on this structure using a thin-film deposition process, a needle-like morphology is formed at the tip of the shielding gate polysilicon. Compared to the fork-like morphology defects in the prior art, the interlayer oxide layer formed on this needle-like morphology has a higher thickness, thereby improving the insulation performance between the shielding gate polysilicon and the gate polysilicon, ensuring the leakage characteristics between the source and gate in the VDMOS device, and thus improving the performance and quality of the VDMOS device.

[0028] Further, the step of forming a first oxide layer on the surface of the epitaxial layer and a second oxide layer on the surface of the shielding gate trench includes:

[0029] Thermal oxidation deposition is performed on the epitaxial layer, thereby causing oxidation reactions on the surface of the epitaxial layer and the surface of the shielding gate trench, thereby forming a first oxide layer on the surface of the epitaxial layer and a second oxide layer on the surface of the shielding gate trench.

[0030] A second aspect of the present invention provides a shielded gate trench VDMOS field plate fabrication system, comprising:

[0031] An epitaxial layer fabrication module is used to provide a substrate and form an epitaxial layer on the surface of the substrate;

[0032] A trench etching module is used to etch shielding gate trenches in the epitaxial layer;

[0033] An oxide deposition module is used to form a first oxide layer on the surface of the epitaxial layer and a second oxide layer on the surface of the shielding gate trench.

[0034] A raw polysilicon deposition module is used to deposit a raw polysilicon layer in the shielding gate trench, the raw polysilicon layer having a gap morphology;

[0035] A rapid thermal annealing module is used to rapidly thermal anneal the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer.

[0036] A shielding gate polysilicon forming module is used to etch back the large-grain polysilicon layer to form a shielding gate polysilicon layer;

[0037] A field oxide layer forming module is used to etch the first oxide layer and the second oxide layer to form a field oxide layer;

[0038] An interlayer oxide layer forming module is used to form an interlayer oxide layer on the surface of the field oxide layer and the shielding gate polysilicon layer, and to form a needle-like morphology at the top of the shielding gate polysilicon layer.

[0039] A gate oxide layer forming module is used to form a gate oxide layer on both the surface of the epitaxial layer and the sidewall of the shielding gate trench;

[0040] A gate polysilicon forming module is used to deposit a gate polysilicon layer on both the surface of the interlayer oxide layer and the gate oxide layer.

[0041] Further, the rapid thermal annealing of the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer includes:

[0042] The original polycrystalline silicon layer is subjected to rapid thermal annealing to recrystallize the original polycrystalline silicon layer, thereby causing the grains in the original polycrystalline silicon layer to grow and fill the gap morphology, forming a large-grain polycrystalline silicon layer.

[0043] Furthermore, before performing rapid thermal annealing on the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer, the process further includes:

[0044] The original polycrystalline silicon layer is subjected to chemical mechanical polishing to obtain a first polycrystalline silicon layer, which is then used as the original polycrystalline silicon layer.

[0045] Further, the step of forming an interlayer oxide layer on the surfaces of the field oxide layer and the shielding gate polysilicon layer, and forming a needle-like morphology at the tip of the shielding gate polysilicon layer, includes:

[0046] A sacrificial oxide layer is deposited on the surface of the epitaxial layer, the surface of the shielding gate polysilicon layer, and the sidewall of the shielding gate trench using a thin film deposition process, and a needle-like morphology is formed at the top of the shielding gate polysilicon layer.

[0047] The sacrificial oxide layer is etched to remove excess sacrificial oxide layer covering the surface of the epitaxial layer and the sidewalls of the shielding gate trench, thereby forming the interlayer oxide layer.

[0048] A third aspect of the present invention provides a shielded gate trench VDMOS field plate structure, comprising:

[0049] A substrate, the surface of which is covered with an epitaxial layer;

[0050] The surface of the epitaxial layer is covered with a first oxide layer, and a shielding gate trench is provided in the epitaxial layer;

[0051] The bottom of the shielding grid trench is covered with a field oxide layer;

[0052] A shielding gate polysilicon layer is disposed on the surface of the field oxide layer, and the top of the shielding gate polysilicon layer has a needle-like shape.

[0053] The surface of the field oxide layer and the shielding gate polysilicon layer is covered with an interlayer oxide layer;

[0054] The sidewalls of the shielding gate trench are also covered with a gate oxide layer, and the gate oxide layer is located above the interlayer oxide layer;

[0055] The surfaces of the first oxide layer, the interlayer oxide layer, and the gate oxide layer are all covered with a gate polysilicon layer.

[0056] In the aforementioned shielded gate trench VDMOS field plate structure, the top of the shielded gate polysilicon is formed into a needle-like morphology. Compared to the fork-like morphology defects at the top of the shielded gate polysilicon in the prior art, the interlayer oxide layer thickness formed on this needle-like morphology is higher, thereby improving the insulation performance between the shielded gate polysilicon and the gate polysilicon, ensuring the leakage characteristics between the source and gate in the VDMOS device, and thus improving the performance and quality of the VDMOS device. Attached Figure Description

[0057] Figure 1 This is a schematic flowchart of a method for fabricating a shielded gate trench VDMOS field plate;

[0058] Figure 2 a is a schematic diagram of a VDMOS structure with normal aspect ratio provided in an embodiment of the present invention;

[0059] Figure 2 b is a schematic diagram of the on-resistance of another normal aspect ratio VDMOS structure provided in an embodiment of the present invention;

[0060] Figure 2 c is a schematic diagram of the trench spacing of a VDMOS with a normal aspect ratio;

[0061] Figure 3 a is a schematic diagram of a high aspect ratio VDMOS structure provided in an embodiment of the present invention;

[0062] Figure 3 b is a schematic diagram of the internal on-resistance of another high aspect ratio VDMOS structure provided in an embodiment of the present invention;

[0063] Figure 3 c is a schematic diagram of a high aspect ratio VDMOS trench spacing;

[0064] Figure 4 This is a schematic diagram of the morphological defects of a high aspect ratio shielding gate polysilicon gap.

[0065] Figure 5 This is a schematic diagram of a V-shaped morphology of a high aspect ratio shielding gate polysilicon.

[0066] Figure 6 This is a schematic diagram of the fork-shaped morphology at the top of a polysilicon shielding layer provided in an embodiment of the present invention;

[0067] Figure 7 This is a schematic diagram of the needle-like morphology at the top of a polycrystalline silicon shielding layer provided in an embodiment of the present invention;

[0068] Figure 8 a to Figure 12 b is a schematic diagram of the structural changes corresponding to the shielded gate trench VDMOS field plate fabrication method provided by the present invention;

[0069] Figure 13 a to Figure 15 b is a schematic diagram of the structural changes corresponding to a prior art VDMOS field plate fabrication method provided by the present invention;

[0070] Figure 16 This is a schematic diagram of a shielded gate trench VDMOS field plate fabrication system.

[0071] Wherein: 1. Substrate; 2. Epitaxial layer; 21. Shielding gate trench; 31. First oxide layer; 32. Second oxide layer; 41. Original polysilicon layer; 42. Large-grain polysilicon layer; 43. Shielding gate polysilicon layer; 33. Field oxide layer; 51. Sacrificial oxide layer; 52. Interlayer oxide layer; 6. Gate oxide layer; 7. Gate polysilicon layer. Detailed Implementation

[0072] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that the following detailed descriptions are exemplary and intended to provide further detailed explanation of the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0073] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0074] Before describing this application in detail with reference to the accompanying drawings and embodiments, the terms and application scenarios involved in this application will first be explained.

[0075] Please refer to Figure 2 a to Figure 2 c, Figure 2 a is a schematic diagram of a normal aspect ratio VDMOS structure provided in an embodiment of the present invention, wherein N-type Substrate represents N-type substrate 1, N-type EPI represents N-type epitaxial layer 2, Gate represents gate polysilicon, GATE OX represents gate oxide layer 6, field ox represents field oxide layer 33, and Field plate represents shielding gate oxide layer 6. Figure 2 b is Figure 2 A schematic diagram of the on-resistance of a normal aspect ratio VDMOS structure, where R represents resistance, corresponding to... Figure 2 In the shielding groove of 'a', 'I' represents the current. Figure 2 c reflects Figure 2 The spacing and aspect ratio of the shielding grid grooves 21 in section a are as follows: the width of the shielding grid grooves 21 is 0.9, and the spacing of the shielding grid grooves 21 is 2.0.

[0076] Please compare the above content with... Figure 3 a to Figure 3 c is used as a control. Among them, Figure 3 b is Figure 3 Schematic diagram of the on-resistance of a high aspect ratio VDMOS structure. Figure 3 c reflects Figure 3 The spacing and aspect ratio of the shielding grid grooves 21 in section a are as follows: the width of the shielding grid grooves 21 is 0.4, and the spacing of the shielding grid grooves 21 is 1.2.

[0077] It is evident that with the development of VDMOS trench structures with lower specific on-resistance, smaller trench pitch values ​​have further reduced the trench width in VDMOS, resulting in a continuous increase in trench depth-to-width ratio.

[0078] Please refer to Figure 4 Observation of the shielding gate polysilicon during the etching process at the nanoscale reveals that, in conventional structures and processes, when depositing shielding gate polysilicon in the shielding gate trench 21 with a very large aspect ratio, a seam appears that runs from top to bottom through the shielding gate polysilicon; this is referred to as the seam morphology in this invention. Please refer to further details. Figure 5 This gap morphology resulted in a V-shaped morphology on the top of the polysilicon during subsequent etch-back of the shielding gate. Please refer to further details. Figure 6 This V-shaped morphology results in a fork-like morphology at the top of the shielding gate polysilicon during subsequent deposition of the sacrificial oxide layer 51, formation of the interlayer oxide layer 52, and formation of the gate oxide layer 6. Figure 6 As can be seen, the shortest spacing between the shielding gate polysilicon and the gate polysilicon in the figure is only 44.95 nm and 37.98 nm, respectively. This indicates that the fork-shaped morphology leads to a further reduction in the thickness of the interlayer oxide layer 52 between the shielding gate polysilicon and the gate polysilicon, which affects the leakage characteristics of the source and gate of the SGT VDMOS and the electric field distribution near the shielding gate, thereby causing the device's electrical parameters to deteriorate.

[0079] To solve the above technical problems, please refer to Figure 1 , Figure 8 a to Figure 12 b. A first aspect of the present invention provides a method for fabricating a shielded gate trench 21VDMOS field plate, comprising:

[0080] refer to Figure 8 a. Step S1 includes: providing a substrate 1 and forming an epitaxial layer 2 on the surface of the substrate 1.

[0081] refer to Figure 8 a. Step S2 includes: etching a shielding gate trench 21 in the epitaxial layer 2.

[0082] refer to Figure 8b. Step S3 includes: forming a first oxide layer 31 on the surface of the epitaxial layer 2 and forming a second oxide layer 32 on the surface of the shielding trench 21.

[0083] In one specific embodiment, the step of forming a first oxide layer 31 on the surface of the epitaxial layer 2 and forming a second oxide layer 32 on the surface of the shielding gate trench 21 includes:

[0084] Thermal oxidation deposition is performed on the epitaxial layer 2, thereby causing oxidation reactions on the surface of the epitaxial layer 2 and the surface of the shielding gate trench 21, thereby forming a first oxide layer 31 on the surface of the epitaxial layer 2 and a second oxide layer 32 on the surface of the shielding gate trench 21.

[0085] refer to Figure 9 a. Step S4 includes: depositing a raw polysilicon layer 41 in the shielding trench 21, the raw polysilicon layer 41 having a gap morphology.

[0086] In one specific embodiment, before the rapid thermal annealing of the original polycrystalline silicon layer 41 in step S5 to eliminate the gap morphology and form the large-grain polycrystalline silicon layer 42, the method further includes:

[0087] The original polycrystalline silicon layer 41 is subjected to chemical mechanical polishing to obtain a first polycrystalline silicon layer, which is then used as the original polycrystalline silicon layer 41.

[0088] It should be noted that the surface of the original polysilicon layer 41 formed in trenches with high aspect ratios may have uneven undulations, which can easily lead to unevenness on the surface of the subsequent etch-back formation of the shielding gate polysilicon layer 43, affecting the electrical performance of the VDMOS device. Furthermore, the large-grain polysilicon layer 42 formed after rapid thermal annealing has a denser grain structure, making chemical mechanical polishing (CMP) more difficult. Therefore, in this embodiment, the original polysilicon layer 41 is first chemically mechanically polished before rapid thermal annealing and etch-back to make its surface smooth, which is beneficial for the subsequent formation of a smooth shielding gate oxide layer 6, thereby improving the quality of the electric field distribution near the shielding gate and enhancing the performance and quality of the VDMOS device.

[0089] refer to Figure 9 b. Step S5 includes: performing rapid thermal annealing on the original polycrystalline silicon layer 41 to eliminate the gap morphology and form a large-grain polycrystalline silicon layer 42.

[0090] In one specific embodiment, the rapid thermal annealing of the original polycrystalline silicon layer 41 to eliminate the gap morphology and form a large-grain polycrystalline silicon layer 42 includes:

[0091] The original polycrystalline silicon layer 41 is subjected to rapid thermal annealing to recrystallize the original polycrystalline silicon layer 41, thereby causing the grains in the original polycrystalline silicon layer 41 to grow and fill the gap morphology, forming a large-grain polycrystalline silicon layer 42.

[0092] It should be noted that Rapid Thermal Annealing (RTA) is a processing technique that uses high-intensity light or infrared radiation to rapidly heat up and cool down the surface of a material. This invention has found that when polycrystalline silicon is heated using RTA, the grain structure in the polycrystalline silicon recrystallizes. Furthermore, as the annealing temperature increases, the recrystallization rate of the grain structure in the polycrystalline silicon accelerates, and the grain size gradually increases, thereby filling and eliminating the gaps in the polycrystalline silicon layer, forming a flat and dense large-grain polycrystalline silicon layer 42. This embodiment utilizes rapid high-temperature annealing technology to promote polycrystalline silicon grain growth and eliminate porosity and defects during the polycrystalline silicon deposition process. Eliminating the filling porosity before etching the shielding gate prevents etching gas from drilling along the gaps. During etching at the top of the shielding gate, the morphology changes from a V-shape to a flat morphology, which in turn causes the subsequent shielding gate oxide layer 6 to change from a fork-shaped morphology to a needle-like morphology during the formation of the sacrificial oxide layer 51 and the gate oxide layer 6. This improves the electric field distribution quality near the shielding gate and enhances the performance and quality of the VDMOS device.

[0093] refer to Figure 10 a. Step S6 includes: etching back the large-grain polysilicon layer 42 to form a shielding gate polysilicon layer 43.

[0094] refer to Figure 10 b. Step S7 includes: etching the first oxide layer 31 and the second oxide layer 32 to form a field oxide layer 33.

[0095] refer to Figure 11 a and Figure 11 b. Step S8 includes: forming an interlayer oxide layer 52 on the surface of the field oxide layer 33 and the shielding gate polysilicon layer 43.

[0096] In one specific embodiment, forming an interlayer oxide layer 52 on the surfaces of the field oxide layer 33 and the shielding gate polysilicon layer 43 includes:

[0097] A sacrificial oxide layer 51 is deposited on the surface of the epitaxial layer 2, the surface of the shielding gate polysilicon layer 43, and the sidewall of the shielding gate trench 21 by a thin film deposition process, and the top of the shielding gate polysilicon layer 43 is formed into a needle tip shape.

[0098] The sacrificial oxide layer 51 is etched to remove excess sacrificial oxide layer 51 covering the surface of the epitaxial layer 2 and the sidewall of the shielding trench 21, thereby forming the interlayer oxide layer 52.

[0099] This embodiment simultaneously deposits sacrificial oxide layers 51 on both the surface of the shielding gate polysilicon layer 43 and the sidewalls of the shielding gate trench 21 using a single thin-film deposition process. The sacrificial oxide layer 51 on the surface of the shielding gate polysilicon layer 43 acts as an interlayer oxide layer 52 to isolate the shielding gate polysilicon and the gate polysilicon, preventing short circuits and leakage between them. This ensures the leakage characteristics between the source and gate in the VDMOS device, thereby improving the performance and quality of the VDMOS device. Depositing the sacrificial oxide layer 51 on the sidewalls of the shielding gate trench 21 removes damage and defects, facilitating the subsequent formation of a high-quality gate oxide layer 6 on the sidewalls of the shielding gate trench 21. This further improves the electric field distribution quality near the shielding gate and enhances the performance and quality of the VDMOS device.

[0100] Meanwhile, in a specific embodiment of this example, since the shielding gate polysilicon layer 43 forms a dense and flat large-grain structure after rapid thermal annealing, when the sacrificial oxide layer 51 is deposited on the shielding gate polysilicon using a thin film deposition process, a needle-like morphology will form at the top of the shielding gate polysilicon. Compared to the fork-like morphology defects in the prior art, the interlayer oxide layer 52 formed on this needle-like morphology has a higher thickness, thereby improving the insulation performance between the shielding gate polysilicon and the gate polysilicon, ensuring the leakage characteristics between the source and gate in the VDMOS device, and thus improving the performance and quality of the VDMOS device.

[0101] refer to Figure 12 a. Step S9 includes: forming a gate oxide layer 6 on both the surface of the epitaxial layer 2 and the sidewall of the shielding gate trench 21.

[0102] refer to Figure 12 b. Step S10 includes: depositing a gate polysilicon layer 7 on both the surface of the interlayer oxide layer 52 and the gate oxide layer 6.

[0103] To further illustrate the dense and flat large-grain structure formed by the shielding gate polysilicon layer 43 after a rapid thermal annealing process in the above embodiments, please refer to the needle-like morphology formed at the tip of the shielding gate polysilicon when the sacrificial oxide layer 51 is deposited on the shielding gate polysilicon using a thin film deposition process. Figure 7 .like Figure 7 The image shows the needle-like morphology of the shielding gate polysilicon layer 43 prepared according to an embodiment of the present invention. For further explanation of the technical effects achieved in this embodiment, please refer to [the relevant documentation / reference]. Figure 6 and Figure 7It can be observed that in the aforementioned needle-like morphology, the minimum spacing between the shielding gate polysilicon layer 43 and the gate polysilicon layer 7 is 58.08 nm, 59.69 nm, and 75.82 nm, respectively, which is greater than the shortest spacing of 44.95 nm and 37.98 nm between the shielding gate polysilicon and the gate polysilicon in the fork-like morphology under the same scale process. With the increase in the thickness of the interlayer oxide layer 52, the aforementioned needle-like morphology shielding gate polysilicon layer 43 improves the insulation capability between the two polysilicon layers, greatly improves the leakage current problem of the shielding gate, and realizes the improvement of the electrical performance of the shielding gate in a VDMOS trench structure with a smaller trench pitch and a lower specific on-resistance.

[0104] It should be noted that when the aspect ratio of the shielding gate trench 21 is too large, a gap morphology will appear in the original polysilicon layer 41, penetrating the polysilicon layer. This gap morphology causes the etching gas to penetrate along the gap morphology when the original polysilicon layer 41 is etched back to form the shielding gate polysilicon layer 43, forming a V-shaped morphology at the top of the shielding gate polysilicon layer 43. This gap morphology and V-shaped morphology cause a fork-shaped morphology at the top of the shielding gate polysilicon layer 43 when the interlayer oxide layer 52 is subsequently formed on the surface of the field oxide layer 33 and the shielding gate polysilicon layer 43, severely affecting the leakage current performance between the source and gate in the SGT VDMOS device. Therefore, the above-mentioned VDMOS field plate fabrication method performs a rapid thermal annealing process on the original polysilicon layer 41. The rapid high-temperature annealing technology promotes the grain growth in the original polysilicon layer 41, eliminates the morphological defects of pores and gaps in the polysilicon deposition process, and obtains a seamless, flat and dense large-grain polysilicon layer 42. This ensures that the subsequent etch-back of the large-grain polysilicon layer 42 will not form a V-shaped morphology, and finally obtains a flat and dense shielding gate polysilicon layer 43, avoiding the formation of a fork-shaped morphology. This improves the quality of the electric field distribution near the shielding gate and enhances the performance and quality of the VDMOS device.

[0105] To further illustrate the technical effects of this invention, please refer to... Figure 13 a to Figure 15 b. In contrast, embodiments of the present invention also provide a process flow for forming fork-shaped morphological defects for reference.

[0106] Step 1, as follows Figure 8 a to Figure 9 As shown in Figure a, a substrate 1 is provided, an epitaxial layer 2 is formed on the surface of the substrate 1, and a shielding gate trench 21 is etched therein; a first oxide layer 31 is formed on the surface of the epitaxial layer 2, and a second oxide layer 32 is formed on the surface of the shielding gate trench 21; a raw polysilicon layer 41 is deposited in the shielding gate trench 21, and the raw polysilicon layer 41 has a gap morphology.

[0107] like Figure 13As shown in a, if the original polysilicon layer 41 is directly etched back to form a shielding gate polysilicon layer 43, the top of the shielding gate polysilicon layer 43 will form a V-shaped defect due to the etching gas drilling along the gap.

[0108] like Figure 13 As shown in b, the first oxide layer 31 and the second oxide layer 32 are etched to form a field oxide layer 33;

[0109] like Figure 14 a and Figure 14 As shown in b, forming an interlayer oxide layer 52 on the surface of the field oxide layer 33 and the shielding gate polysilicon layer 43 includes: depositing a sacrificial oxide layer 51 on the surface of the epitaxial layer 2, the surface of the shielding gate polysilicon layer 43, and the sidewall of the shielding gate trench 21; etching the sacrificial oxide layer 51 to remove excess sacrificial oxide layer 51 covering the surface of the epitaxial layer 2 and the sidewall of the shielding gate trench 21, thereby forming the interlayer oxide layer 52.

[0110] As can be seen, due to the presence of the aforementioned V-shaped morphological defects, a fork-shaped morphological defect is formed at the top of the shielding gate polysilicon layer 43.

[0111] like Figure 15 As shown in Figure a, a gate oxide layer 6 is formed on both the surface of the epitaxial layer 2 and the sidewall of the shielding gate trench 21;

[0112] like Figure 15 As shown in b, a gate polysilicon layer 7 is deposited on both the interlayer oxide layer 52 and the gate oxide layer 6.

[0113] Therefore, without the shielded gate trench 21VDMOS field plate fabrication method provided by the present invention, it is impossible to overcome the gap morphology defects of the shielded gate polysilicon layer 43 during the fabrication of the high aspect ratio shielded gate trench 21. The shielded gate polysilicon layer 43 will form V-shaped morphology defects due to the etching gas drilling along the gaps, and then the V-shaped morphology defects will form fork-shaped morphology defects when depositing the interlayer oxide layer 52 and the gate oxide layer 6.

[0114] refer to Figure 16 A second aspect of the present invention provides a shielded gate trench 21V DMOS field plate fabrication system, comprising:

[0115] Epitaxial layer 2 fabrication module 100 is used to provide substrate 1 and form epitaxial layer 2 on the surface of substrate 1;

[0116] The trench etching module 200 is used to etch the shielding gate trench 21 in the epitaxial layer 2;

[0117] The oxide deposition module 300 is used to form a first oxide layer 31 on the surface of the epitaxial layer 2 and a second oxide layer 32 on the surface of the shielding gate trench 21.

[0118] A raw polysilicon deposition module 400 is used to deposit a raw polysilicon layer 41 in the shielding trench 21, the raw polysilicon layer 41 having a gap morphology.

[0119] The rapid thermal annealing module 500 is used to rapidly thermal anneal the original polycrystalline silicon layer 41 to eliminate the gap morphology and form a large-grain polycrystalline silicon layer 42.

[0120] The shielding gate polysilicon forming module 600 is used to etch back the large-grain polysilicon layer 42 to form the shielding gate polysilicon layer 43.

[0121] The field oxide layer forming module 700 is used to etch the first oxide layer 31 and the second oxide layer 32 to form the field oxide layer 33;

[0122] Interlayer oxide layer forming module 800 is used to form an interlayer oxide layer 52 on the surface of the field oxide layer 33 and the shielding gate polysilicon layer 43;

[0123] A gate oxide layer forming module 900 is used to form a gate oxide layer 6 on both the surface of the epitaxial layer 2 and the sidewall of the shielding gate trench 21.

[0124] A gate polysilicon forming module 1000 is used to deposit a gate polysilicon layer 7 on both the surface of the interlayer oxide layer 52 and the gate oxide layer 6.

[0125] Further, the rapid thermal annealing of the original polycrystalline silicon layer 41 to eliminate the gap morphology and form a large-grain polycrystalline silicon layer 42 includes:

[0126] The original polycrystalline silicon layer 41 is subjected to rapid thermal annealing to recrystallize the original polycrystalline silicon layer 41, thereby causing the grains in the original polycrystalline silicon layer 41 to grow and fill the gap morphology, forming a large-grain polycrystalline silicon layer 42.

[0127] Furthermore, before rapidly thermally annealing the original polycrystalline silicon layer 41 to eliminate the gap morphology and form the large-grain polycrystalline silicon layer 42, the process further includes:

[0128] The original polycrystalline silicon layer 41 is subjected to chemical mechanical polishing to obtain a first polycrystalline silicon layer, which is then used as the original polycrystalline silicon layer 41.

[0129] Further, the formation of an interlayer oxide layer 52 on the surfaces of the field oxide layer 33 and the shielding gate polysilicon layer 43 includes:

[0130] A sacrificial oxide layer 51 is deposited on the surface of the epitaxial layer 2, the surface of the shielding gate polysilicon layer 43, and the sidewall of the shielding gate trench 21 by a thin film deposition process, and the top of the shielding gate polysilicon layer 43 is formed into a needle tip shape.

[0131] The sacrificial oxide layer 51 is etched to remove excess sacrificial oxide layer 51 covering the surface of the epitaxial layer 2 and the sidewall of the shielding trench 21, thereby forming the interlayer oxide layer 52.

[0132] refer to Figure 12 b. A shielded gate trench 21VDMOS field plate structure according to a third aspect of the present invention includes:

[0133] Substrate 1, wherein the surface of substrate 1 is covered with an epitaxial layer 2;

[0134] The surface of the epitaxial layer 2 is covered with a first oxide layer 31, and a shielding gate trench 21 is provided in the epitaxial layer 2;

[0135] The bottom end of the shielding grid trench 21 is covered with a field oxide layer 33;

[0136] A shielding gate polysilicon layer 43 is disposed on the surface of the field oxide layer 33, and the top of the shielding gate polysilicon layer 43 has a needle-like shape.

[0137] The surface of the field oxide layer 33 and the shielding gate polysilicon layer 43 is covered with an interlayer oxide layer 52;

[0138] The sidewall of the shielding trench 21 is also covered with a gate oxide layer 6, and the gate oxide layer 6 is located above the interlayer oxide layer 52.

[0139] The surfaces of the first oxide layer 31, the interlayer oxide layer 52, and the gate oxide layer 6 are all covered with a gate polysilicon layer 7.

[0140] In the aforementioned 21VDMOS field plate structure with a shielded gate trench, the top of the shielded gate polysilicon is formed into a needle-like morphology. Compared to the fork-like morphology defects at the top of the shielded gate polysilicon in the prior art, the thickness of the interlayer oxide layer 52 formed on this needle-like morphology is higher, thereby improving the insulation performance between the shielded gate polysilicon and the gate polysilicon, ensuring the leakage characteristics between the source and gate in the VDMOS device, and thus improving the performance and quality of the VDMOS device.

[0141] This invention provides a method, system, and structure for fabricating a 21V DMOS field plate with a shielded gate trench. Based on the traditional 21V DMOS field-effect transistor with a shielded gate trench, it eliminates the top fork-shaped etching morphology by changing the surface structure of the shielded gate, and simultaneously increases the minimum thickness of the interlayer oxide from 38 nanometers to 58 nanometers. Figure 6 and Figure 7 As shown. Without adding new process technology or photomask quantity, this structure not only optimizes electrical parameters, but also further promotes the development of shielded gate trench 21VDMOS towards lower specific on-resistance and higher integration.

[0142] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; however, any combination of these technical features that does not contradict each other should be considered within the scope of this specification.

[0143] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the concept of this application, and these improvements and substitutions should also be considered within the scope of protection of this invention. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A method for fabricating a shielded gate trench VDMOS field plate, characterized in that, include: A substrate is provided, and an epitaxial layer is formed on the surface of the substrate; Etch shielding trenches in the epitaxial layer; A first oxide layer is formed on the surface of the epitaxial layer, and a second oxide layer is formed on the surface of the shielding gate trench; A raw polysilicon layer is deposited in the shielding trench, the raw polysilicon layer having a gap morphology; The original polycrystalline silicon layer is subjected to rapid thermal annealing to eliminate the gap morphology and form a large-grain polycrystalline silicon layer. The large-grain polycrystalline silicon layer is etched back to form a shielding gate polycrystalline silicon layer; Etch the first oxide layer and the second oxide layer to form a field oxide layer; An interlayer oxide layer is formed on the surface of the field oxide layer and the shielding gate polysilicon layer, and a needle-like morphology is formed at the top of the shielding gate polysilicon layer; A gate oxide layer is formed on both the surface of the epitaxial layer and the sidewalls of the shielding gate trench; A gate polysilicon layer is deposited on both the interlayer oxide layer and the gate oxide layer.

2. The method for fabricating a shielded gate trench VDMOS field plate according to claim 1, characterized in that, The step of rapidly thermally annealing the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer includes: rapidly thermally annealing the original polycrystalline silicon layer to cause recrystallization of the original polycrystalline silicon layer, thereby causing grains in the original polycrystalline silicon layer to grow and fill the gap morphology, forming a large-grain polycrystalline silicon layer.

3. The method for fabricating a shielded gate trench VDMOS field plate according to claim 1, characterized in that, Before performing rapid thermal annealing on the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer, the process further includes: The original polycrystalline silicon layer is subjected to chemical mechanical polishing to obtain a first polycrystalline silicon layer, which is then used as the original polycrystalline silicon layer.

4. The method for fabricating a shielded gate trench VDMOS field plate according to claim 1, characterized in that, The step of forming an interlayer oxide layer on the surfaces of the field oxide layer and the shielding gate polysilicon layer, and forming a needle-like morphology at the tip of the shielding gate polysilicon layer, includes: A sacrificial oxide layer is deposited on the surface of the epitaxial layer, the surface of the shielding gate polysilicon layer, and the sidewall of the shielding gate trench using a thin film deposition process, and a needle-like morphology is formed at the top of the shielding gate polysilicon layer. The sacrificial oxide layer is etched to remove excess sacrificial oxide layer covering the surface of the epitaxial layer and the sidewalls of the shielding gate trench, thereby forming the interlayer oxide layer.

5. The method for fabricating a shielded gate trench VDMOS field plate according to claim 1, characterized in that, The step of forming a first oxide layer on the surface of the epitaxial layer and a second oxide layer on the surface of the shielding gate trench includes: Thermal oxidation deposition is performed on the epitaxial layer, thereby causing oxidation reactions on the surface of the epitaxial layer and the surface of the shielding gate trench, thereby forming a first oxide layer on the surface of the epitaxial layer and a second oxide layer on the surface of the shielding gate trench.

6. A shielded gate trench VDMOS field plate fabrication system, characterized in that, include: An epitaxial layer fabrication module is used to provide a substrate and form an epitaxial layer on the surface of the substrate; A trench etching module is used to etch shielding gate trenches in the epitaxial layer; An oxide deposition module is used to form a first oxide layer on the surface of the epitaxial layer and a second oxide layer on the surface of the shielding gate trench. A raw polysilicon deposition module is used to deposit a raw polysilicon layer in the shielding gate trench, the raw polysilicon layer having a gap morphology; A rapid thermal annealing module is used to rapidly thermally anneal the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer. A shielding gate polysilicon forming module is used to etch back the large-grain polysilicon layer to form a shielding gate polysilicon layer; A field oxide layer forming module is used to etch the first oxide layer and the second oxide layer to form a field oxide layer; An interlayer oxide layer forming module is used to form an interlayer oxide layer on the surface of the field oxide layer and the shielding gate polysilicon layer, and to form a needle-like morphology at the top of the shielding gate polysilicon layer. A gate oxide layer forming module is used to form a gate oxide layer on both the surface of the epitaxial layer and the sidewall of the shielding gate trench; A gate polysilicon forming module is used to deposit a gate polysilicon layer on both the surface of the interlayer oxide layer and the gate oxide layer.

7. The shielded gate trench VDMOS field plate fabrication system according to claim 6, characterized in that, The step of rapidly thermally annealing the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer includes: rapidly thermally annealing the original polycrystalline silicon layer to cause recrystallization of the original polycrystalline silicon layer, thereby causing grains in the original polycrystalline silicon layer to grow and fill the gap morphology, forming a large-grain polycrystalline silicon layer.

8. The shielded gate trench VDMOS field plate fabrication system according to claim 6, characterized in that, Before performing rapid thermal annealing on the original polycrystalline silicon layer to eliminate the gap morphology and form a large-grain polycrystalline silicon layer, the process further includes: The original polycrystalline silicon layer is subjected to chemical mechanical polishing to obtain a first polycrystalline silicon layer, which is then used as the original polycrystalline silicon layer.

9. The shielded gate trench VDMOS field plate fabrication system according to claim 6, characterized in that, The step of forming an interlayer oxide layer on the surfaces of the field oxide layer and the shielding gate polysilicon layer, and forming a needle-like morphology at the tip of the shielding gate polysilicon layer, includes: A sacrificial oxide layer is deposited on the surface of the epitaxial layer, the surface of the shielding gate polysilicon layer, and the sidewall of the shielding gate trench using a thin film deposition process, and a needle-like morphology is formed at the top of the shielding gate polysilicon layer. The sacrificial oxide layer is etched to remove excess sacrificial oxide layer covering the surface of the epitaxial layer and the sidewalls of the shielding gate trench, thereby forming the interlayer oxide layer.

10. A shielded gate trench VDMOS field plate structure, characterized in that, The shielded gate trench VDMOS field plate structure is fabricated by the shielded gate trench VDMOS field plate fabrication method according to any one of claims 1 to 5, and the structure includes: A substrate, the surface of which is covered with an epitaxial layer; The surface of the epitaxial layer is covered with a first oxide layer, and a shielding gate trench is provided in the epitaxial layer; The bottom of the shielding grid trench is covered with a field oxide layer; A shielding gate polysilicon layer is disposed on the surface of the field oxide layer, and the top of the shielding gate polysilicon layer has a needle-like shape. The surface of the field oxide layer and the shielding gate polysilicon layer is covered with an interlayer oxide layer; The sidewalls of the shielding gate trench are also covered with a gate oxide layer, and the gate oxide layer is located above the interlayer oxide layer; The surfaces of the first oxide layer, the interlayer oxide layer, and the gate oxide layer are all covered with a gate polysilicon layer.

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