Boosting mosfet structure for boosting charging current and method of manufacturing the same

Abstract

This invention provides a boost MOSFET structure and its manufacturing method for increasing charging current. The structure adds an N-type injection layer and a P-type injection layer within a P-type substrate, below the N-type epitaxial layer serving as the drift region. These two layers together form an additional current path connected in parallel with the drift region. This design effectively reduces the total on-resistance of the device and significantly increases the charging current. Simultaneously, when the device is subjected to reverse voltage, the vertical JFET structure formed by the P-type injection layer and the substrate can pinch off this additional path and collaboratively optimize the electric field distribution, transforming a single electric field peak into two lower peaks. This further improves the reverse breakdown voltage while increasing the charging current. This invention resolves the inherent contradiction between high withstand voltage and high current in ultra-high voltage devices, comprehensively improving the overall performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a boost MOSFET structure for increasing charging current and a method for manufacturing the same. Background Technology

[0002] Power MOSFETs, especially ultra-high voltage lateral double-diffused metal-oxide-semiconductor (NLDMOS) devices, play a crucial role in modern power electronics technology due to their combination of the high voltage and high current characteristics of discrete devices with the high density and intelligent logic control advantages of integrated circuits. These devices can achieve functions that previously required multiple chips through single-chip integration, significantly reducing product area, lowering manufacturing costs, and improving system energy efficiency, perfectly aligning with the trend of power electronic devices towards miniaturization, intelligence, and low energy consumption.

[0003] For ultra-high voltage devices, breakdown voltage is one of their core performance indicators. To improve the breakdown voltage capability of devices, existing technologies typically introduce a charge compensation layer in the surface region of the drift region, such as forming a P-type top-injection (PTOP) layer, to enhance the depletion of the drift region and optimize the electric field distribution through the surface electric field reduction (Resurf) effect, thereby improving the breakdown voltage of the device.

[0004] However, while improving reverse voltage withstand capability, traditional ultra-high voltage boost MOSFET device structures inherently face the problem of limited charging current. To withstand ultra-high reverse bias voltages, the drift region of the device must employ a low doping concentration and a large width, which directly results in a very high resistance in the drift region. During forward conduction, the charging current mainly flows through the channel and the high-resistance drift region. The large drift region resistance limits the magnitude of the conduction current, i.e., the charging current is relatively small. This not only reduces the switching speed of the device but also increases switching losses, constituting a technical bottleneck for improving the overall system efficiency. Therefore, how to effectively increase the charging current of ultra-high voltage boost MOSFETs without sacrificing or even improving reverse voltage withstand capability is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that, in order to ensure the withstand voltage capability, the existing ultra-high voltage boost MOSFET has a large drift region resistance, resulting in a small charging current, which limits the switching speed and increases the system power consumption.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] An ultra-high voltage boost MOSFET structure includes:

[0008] P-type substrate;

[0009] An N-type epitaxial layer is disposed on the P-type substrate and serves as a drift region;

[0010] The source region, drain region, and gate structure are disposed within or on the N-type epitaxial layer;

[0011] An N-type implantation layer is disposed within the P-type substrate and located below the N-type epitaxial layer; and

[0012] A P-type injection layer is disposed within the region of the N-type injection layer;

[0013] The N-type injection layer and the P-type injection layer form an additional current path below the drift region.

[0014] Preferably, it further includes an N-type buried layer disposed within the P-type substrate.

[0015] Preferably, it further includes a P-well and an N-well disposed within the N-type epitaxial layer.

[0016] Preferably, the gate structure includes:

[0017] The gate oxide layer formed on the N-type epitaxial layer; and

[0018] A polysilicon gate formed on the gate oxide layer.

[0019] Preferably, it further includes a field oxide layer formed on the N-type epitaxial layer.

[0020] Preferably, it further includes a Ptop injection layer formed on the surface of the N-type epitaxial layer.

[0021] Preferably, the arrangement of the P-type injection layer and the P-type substrate is used to form a vertical junction field-effect transistor when the device is subjected to a reverse voltage, thereby pinching off the additional current path.

[0022] Preferably, compared to a structure without the N-type injection layer and the P-type injection layer, the additional current path increases the charging current of the structure by 40%.

[0023] A method for manufacturing an ultra-high voltage boost MOSFET includes the following steps:

[0024] Step 1: Provide a P-type substrate;

[0025] Step 2: Form an N-type implantation layer and a P-type implantation layer located within the N-type implantation layer region in the P-type substrate;

[0026] Step 3: Form an N-type epitaxial layer on the P-type substrate as a drift region; and

[0027] Step 4: Form the source region, drain region, and gate structure within or on the N-type epitaxial layer;

[0028] The N-type injection layer and the P-type injection layer form an additional current path below the drift region.

[0029] Preferably, step two further includes forming an N-type buried layer within the P-type substrate.

[0030] Preferably, after step three, a step of forming a field oxide layer on the N-type epitaxial layer is further included.

[0031] Preferably, the method further includes the step of forming a Ptop implantation layer on the surface of the N-type epitaxial layer after the formation of the field oxide layer.

[0032] Preferably, before forming the gate structure, the method further includes the step of forming a P-well and an N-well by ion implantation within the N-type epitaxial layer.

[0033] Preferably, the step of forming the gate structure in step four includes:

[0034] A gate oxide layer is grown on the N-type epitaxial layer;

[0035] A polysilicon layer is deposited on the gate oxide layer; and

[0036] The polysilicon layer is etched to form a gate.

[0037] Preferably, by performing step two, the charging current of the manufactured ultra-high voltage boost MOSFET is increased by 40%.

[0038] Preferably, the reverse breakdown voltage of the manufactured ultra-high voltage boost MOSFET reaches 1525V. As described above, the boost MOSFET structure and manufacturing method for increasing charging current of the present invention have the following beneficial effects:

[0039] This application provides a parallel low-resistance path for forward current by adding an additional current path composed of an N-type injection layer and a P-type injection layer below the drift region, which effectively reduces the total on-resistance of the device and significantly increases the charging current (e.g., by 40%), thereby improving the switching speed of the device and reducing switching losses.

[0040] This application forms a vertical JFET structure with the substrate through a P-type injection layer and performs electric field modulation in conjunction with Ptop injection, which can effectively pinch off the additional current path when the device is reverse cut off, and optimize the single electric field peak into two lower peaks. Not only does it not sacrifice the withstand voltage, but it also further improves the reverse breakdown voltage, ensuring the reliability of the device under high voltage applications. Attached Figure Description

[0041] Figure 1 The diagram shows a process flow diagram of a method for manufacturing an ultra-high voltage boost MOSFET according to the present invention.

[0042] Figure 2 The diagram shows the structure after the implantation layer is formed in a P-type substrate according to an embodiment of the present invention.

[0043] Figure 3 The diagram shown is a structural schematic of the N-type epitaxial layer after formation according to an embodiment of the present invention.

[0044] Figure 4 The diagram shows the structure after the formation of the field oxide layer and the Ptop implantation layer in an embodiment of the present invention.

[0045] Figure 5 The diagram shows the structure after the P-well and N-well are formed according to an embodiment of the present invention.

[0046] Figure 6 The diagram shown is a schematic representation of the structure after the gate structure is formed according to an embodiment of the present invention.

[0047] Figure 7 The diagram shows the final structure of an ultra-high voltage boost MOSFET according to an embodiment of the present invention.

[0048] Figure 8 The diagram shows a simulation of the forward charging current distribution of a MOSFET structure in the prior art.

[0049] Figure 9 The diagram shows a simulation schematic of the reverse breakdown voltage longitudinal electric field distribution of a MOSFET structure in the prior art.

[0050] Figure 10 The diagram shown is a simulation schematic of the forward charging current distribution of an ultra-high voltage boost MOSFET according to an embodiment of the present invention.

[0051] Figure 11 The diagram shown is a simulation schematic of the reverse withstand voltage longitudinal electric field distribution of an ultra-high voltage boost MOSFET according to an embodiment of the present invention. Detailed Implementation

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] This invention provides an ultra-high voltage boost metal-oxide-semiconductor field-effect transistor (MOSFET) structure, aiming to solve the technical problems of excessively small charging current and large switching losses in existing ultra-high voltage devices in order to ensure voltage withstand capability.

[0054] Please see Figure 7 An ultra-high voltage boost MOSFET structure includes: a P-type substrate 101; an N-type epitaxial layer 105 disposed on the P-type substrate 101 as a drift region; a source region 112a, a drain region 112b, and a gate structure disposed within or on the N-type epitaxial layer 105; an N-type injection layer 103 disposed within the P-type substrate 101 and below the N-type epitaxial layer 105; and a P-type injection layer 104 disposed within the region of the N-type injection layer 103; wherein the N-type injection layer 103 and the P-type injection layer 104 form an additional current path below the drift region. This additional current path is connected in parallel with the original drift region current path, effectively reducing the total on-resistance of the device, thereby allowing a larger current to pass through during forward conduction.

[0055] In some embodiments, the structure further includes an N-type buried layer 102 disposed within the P-type substrate 101. The N-type buried layer 102 can further optimize the electric field distribution and provide better latch-up immunity for the device, thereby enhancing the stability and reliability of the device.

[0056] In some embodiments, the structure further includes a P-well 108 and an N-well 109 disposed within the N-type epitaxial layer 105. The P-well 108 and N-well 109 are key structures constituting the basic unit of a MOSFET, used to define the channel region, connect the source, and isolate different active regions, forming the basis for the normal switching function of the device. The structure also includes a heavily p-doped region 113 for forming ohmic contacts.

[0057] In some embodiments, the gate structure includes: a gate oxide layer 110 formed on an N-type epitaxial layer 105; and a polysilicon gate 111 formed on the gate oxide layer 110.

[0058] In some embodiments, the structure further includes a field oxide layer 106 formed on the N-type epitaxial layer 105. The field oxide layer 106 serves as a dielectric isolation structure, used to electrically isolate different active devices or different parts of devices on the chip surface, preventing unnecessary electrical crosstalk between them and ensuring normal operation of the devices.

[0059] In some embodiments, a Ptop injection layer 107 formed on the surface of the N-type epitaxial layer 105 is also included. The Ptop injection layer 107 helps to deplete the drift region by introducing charges of the opposite conductivity type to the drift region, thereby achieving a surface electric field reduction (Resurf) effect, significantly improving the reverse breakdown voltage of the device and ensuring the safety of the device under high voltage applications.

[0060] In some embodiments, the P-type injection layer 104 and the P-type substrate 101 are configured to form a vertical junction field-effect transistor (JFET) when the device is subjected to a reverse voltage, thereby pinching off the additional current path. When the device is in the reverse cut-off state, the vertical JFET automatically pinches off the additional current path below, preventing leakage current from passing through the path and avoiding the breakdown voltage drop problem that may be caused by the electric field concentration at this location.

[0061] In some embodiments, compared to a structure without the N-type injection layer 103 and the P-type injection layer 104, the additional current path increases the charging current of the structure by 40%. This significant performance improvement means faster switching speeds and lower switching losses, which is crucial for improving the efficiency of the entire power management system, especially for applications such as fast charging and high-frequency switching power supplies. Simulation data shows that when the gate voltage Vg is 20V and the source voltage Vs is 15V, the charging current Id of the original structure is 1.114e-0.5A / µm, while the charging current Id of the new structure of this invention is increased to 1.568e-0.5A / µm.

[0062] The present invention also provides a method for manufacturing the above-mentioned ultra-high voltage boost MOSFET.

[0063] Please see Figure 1 A method for manufacturing an ultra-high voltage boost MOSFET includes the following steps:

[0064] Step 1: Provide a P-type substrate 101;

[0065] Step 2: Form an N-type implantation layer 103 and a P-type implantation layer 104 located within the N-type implantation layer 103 region in the P-type substrate 101, forming as shown in the figure. Figure 2 The structure shown;

[0066] In some embodiments, step two further includes forming an N-type buried layer 102 within the P-type substrate 101.

[0067] Step 3: Form an N-type epitaxial layer 105 on the P-type substrate 101 as a drift region, forming a layer as shown in the figure. Figure 3 The structure shown;

[0068] In some embodiments, after step three, a step of forming a field oxide layer 106 on the N-type epitaxial layer 105 is further included.

[0069] In some embodiments, the method further includes the step of forming a Ptop implantation layer 107 on the surface of the N-type epitaxial layer 105 after the field oxide layer 106 is formed, to form a Ptop implantation layer 107 as shown in the figure. Figure 4The structure shown is as follows. The Ptop implantation layer 107 formed in this step works synergistically with the N-type implantation layer 103 and P-type implantation layer 104 formed in step two and the N-type epitaxial layer 105 formed in step three to simultaneously optimize the surface electric field and the bulk electric field, optimizing one electric field peak in the original structure into two lower electric field peaks, thereby further improving the overall breakdown voltage capability of the device.

[0070] In some embodiments, prior to forming the gate structure, the method further includes the step of forming a P-well 108 and an N-well 109 within the N-type epitaxial layer 105 by ion implantation, forming a structure as shown below. Figure 5 The structure shown.

[0071] Step 4: Form source region 112a, drain region 112b and gate structure in or on the N-type epitaxial layer 105;

[0072] Among them, the N-type injection layer 103 and the P-type injection layer 104 form an additional current path below the drift region.

[0073] In some embodiments, step four, forming the gate structure, includes: growing a gate oxide layer 110 on the N-type epitaxial layer 105; depositing a polysilicon layer 111 on the gate oxide layer 110; and etching the polysilicon layer 111 to form a gate, forming a structure as shown in the figure. Figure 6 The structure shown. Step four also includes forming an N-type heavily doped source region 112a and a drain region 112b, as well as a P-type heavily doped region 113, forming a structure as shown. Figure 7 The structure shown.

[0074] In some embodiments, by performing step two, the charging current of the manufactured ultra-high voltage boost MOSFET is increased by 40%.

[0075] In some embodiments, the reverse breakdown voltage of the manufactured ultra-high voltage boost MOSFET reaches 1525V. In contrast, the reverse breakdown voltage of a conventional device without the core structure of this invention is only 1476V. This indicates that the technical solution of this invention not only significantly increases the charging current but also further enhances the device's withstand voltage capability, achieving a comprehensive performance improvement.

[0076] To further illustrate the technical effects of the present invention, please refer to the appendix. Figure 8 To be continued Figure 11 These accompanying figures, through simulation comparisons, intuitively demonstrate the significant advantages of the structure of the embodiments of the present invention over existing technology structures in terms of forward charging current and reverse withstand voltage performance.

[0077] Please refer to the appendix first. Figure 8 and attached Figure 10 The diagrams illustrate the forward charging current distribution of both the prior art structure and the structure of the present invention. Figure 8 As shown, in the existing technology structure, when conduction occurs, the current path exists only within the drift region formed by the N-type epitaxial layer. Because the drift region is designed to withstand high voltage, its resistance is relatively high, resulting in a small total conduction current, which is represented as a relatively narrow current path in the figure. In contrast, as... Figure 10 As shown in the embodiment of the present invention, an additional parallel current channel is introduced below the drift region through an N-type injection layer 103 and a P-type injection layer 104. Therefore, during forward charging, the current can flow through both the upper drift region and the lower additional channel simultaneously, significantly reducing the total equivalent resistance and enabling it to carry a larger charging current. The figure also visually shows a wider and stronger current distribution.

[0078] Please refer to the appendix. Figure 9 and attached Figure 11 The diagrams illustrate the longitudinal electric field distribution of the prior art structure and the structure of the present invention when subjected to a reverse voltage. Figure 9 As shown, the electric field in the existing technology structure forms a single, sharp peak within the device, and the highest point of this peak determines the device's breakdown voltage. In contrast, as... Figure 11 As shown in the figure, the electric field distribution curve of the novel structure in this embodiment of the invention effectively modulates and redistributes the electric field due to the synergistic effect of the P-type injection layer 104, N-type injection layer 103, and Ptop injection layer 107. This successfully decomposes the originally concentrated single electric field peak into two lower and more gently distributed electric field peaks. This optimization of the electric field peaks avoids excessive concentration of the electric field in local areas, thereby enabling the device to withstand higher reverse bias voltages, thus further improving the reverse withstand voltage capability of the device.

[0079] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A boost MOSFET structure to boost charging current, characterized by include: P-type substrate; An N-type epitaxial layer is disposed on the P-type substrate and serves as a drift region; The source region, drain region, and gate structure are disposed within or on the N-type epitaxial layer; An N-type implantation layer is disposed within the P-type substrate and located below the N-type epitaxial layer; as well as A P-type injection layer is disposed within the region of the N-type injection layer; The N-type injection layer and the P-type injection layer form an additional current path below the drift region.

2. The boost MOSFET structure for boosting the charging current according to claim 1, characterized in that: It also includes an N-type buried layer disposed within the P-type substrate.

3. The boost MOSFET structure for increasing charging current according to claim 1, characterized in that: It also includes P-wells and N-wells disposed within the N-type epitaxial layer.

4. The boost MOSFET structure for increasing charging current according to claim 1, characterized in that: The gate structure includes: a gate oxide layer formed on the N-type epitaxial layer; and a polysilicon gate formed on the gate oxide layer.

5. The boost MOSFET structure for increasing charging current according to claim 1, characterized in that: It also includes a field oxide layer formed on the N-type epitaxial layer.

6. The boost MOSFET structure for increasing charging current according to claim 5, characterized in that: It also includes a Ptop injection layer formed on the surface of the N-type epitaxial layer.

7. The boost MOSFET structure for increasing charging current according to claim 1, characterized in that: The P-type injection layer and the P-type substrate are configured to form a vertical junction field-effect transistor when the device is subjected to a reverse voltage, thereby pinching off the additional current path.

8. The boost MOSFET structure for increasing charging current according to claim 1, characterized in that: Compared to a structure without the N-type injection layer and the P-type injection layer, the additional current path increases the charging current of the structure by 40%.

9. A method for manufacturing a boost MOSFET structure to increase charging current, characterized in that... include: Step 1: Provide a P-type substrate; Step 2: Form an N-type implantation layer and a P-type implantation layer located within the N-type implantation layer region in the P-type substrate; Step 3: Form an N-type epitaxial layer on the P-type substrate as a drift region; as well as Step 4: Form the source region, drain region, and gate structure within or on the N-type epitaxial layer; The N-type injection layer and the P-type injection layer form an additional current path below the drift region.

10. The method for manufacturing a boost MOSFET structure for increasing charging current according to claim 9, characterized in that: Step two also includes forming an N-type buried layer within the P-type substrate.

11. The method for manufacturing a boost MOSFET structure for increasing charging current according to claim 9, characterized in that: Following step three, the method further includes forming a field oxide layer on the N-type epitaxial layer.

12. The method for manufacturing a boost MOSFET structure for increasing charging current according to claim 11, characterized in that: It also includes the step of forming a Ptop implantation layer on the surface of the N-type epitaxial layer after the formation of the field oxide layer.

13. The method for manufacturing a boost MOSFET structure for increasing charging current according to claim 9, characterized in that: Before forming the gate structure, the method further includes the step of forming a P-well and an N-well by ion implantation within the N-type epitaxial layer.

14. The method for manufacturing a boost MOSFET structure for increasing charging current according to claim 9, characterized in that: The step of forming the gate structure in step four includes: growing a gate oxide layer on the N-type epitaxial layer; depositing a polysilicon layer on the gate oxide layer; and etching the polysilicon layer to form the gate.

15. The method for manufacturing a boost MOSFET structure for increasing charging current according to claim 9, characterized in that: By performing step two, the charging current of the manufactured boost MOSFET is increased by 40%.

16. The method for manufacturing a boost MOSFET structure for increasing charging current according to claim 9, characterized in that: The reverse breakdown voltage of the manufactured boost MOSFET reaches 1525V.

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