A semiconductor structure and a method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, and particularly relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, wherein a gate structure and a side wall structure are formed on the substrate, the side wall structure is located on both sides of the gate structure, and source-drain regions are formed in the substrate on both sides of the gate structure; performing wet pre-etching on the source-drain regions to form first grooves; performing dry etching on the first grooves to form second grooves; performing wet etching on the second grooves to form sigma trenches; and performing germanium-silicon epitaxial growth in the sigma trenches to form a germanium-silicon epitaxial layer. The method can significantly reduce the consumption of hard masks above the gate and the side wall caused by etching, protect the hard mask above the gate, and control the consistency of the germanium-silicon critical dimension.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its manufacturing method. Background Technology

[0002] With the development of semiconductor technology, the feature sizes of various semiconductor devices are constantly decreasing, and the performance requirements for semiconductor devices are becoming increasingly stringent. Carrier mobility is one of the main factors affecting the performance of semiconductor devices, and effectively improving carrier mobility has become a key research direction in semiconductor device manufacturing processes. Stress can alter the bandgap and carrier mobility of silicon materials; therefore, forming stress layers in the source and drain doped regions to improve the performance of metal-oxide-semiconductor (MOS) field-effect transistors is becoming an increasingly common method. Specifically, in NMOS devices, stress layers that provide tensile stress are formed to improve electron mobility, while in PMOS devices, stress layers that provide compressive stress are formed to improve hole mobility.

[0003] PMOS devices typically employ embedded silicon germanium (SiGe) strain technology to improve channel stress. This SiGe epitaxial process first forms Sigma trenches in the drain and source regions of the PMOS device, then forms a SiGe epitaxial layer within these trenches to apply compressive stress and improve device performance. Currently, the process of forming Sigma trenches in the source and drain regions inevitably damages the hard mask above the gate and on the sidewalls. This causes the silicon nitride hard mask above the gate to be etched away, losing its function. Combined with process variations from previous layer accumulation, this ultimately leads to poor uniformity in SiGe dimensions, resulting in non-convergence of device electrical parameters and affecting yield. Summary of the Invention

[0004] In view of the problems existing in the prior art, the present invention provides a semiconductor structure and a method for manufacturing the same, so as to improve the problem of damage to the hard mask above the gate and the sidewalls caused by the etching of the source and drain regions in germanium-silicon epitaxy.

[0005] To achieve the above and other related objectives, the first aspect of the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0006] A substrate is provided on which a gate structure and a sidewall structure are formed, the sidewall structure being located on both sides of the gate structure, and active / drain regions are formed in the substrate on both sides of the gate structure.

[0007] The source / drain region is pre-etched using a wet method to form a first groove;

[0008] The first groove is dry-etched to form the second groove;

[0009] The second groove is wet-etched to form a sigma trench;

[0010] Germanium-silicon epitaxial growth is performed in the sigma trench to form a germanium-silicon epitaxial layer.

[0011] In one embodiment of the present invention, wet pre-etching of the source / drain region includes: wet pre-etching of the source / drain region with a tetramethylamine hydroxide solution until the first inverted triangular groove is formed.

[0012] In one embodiment of the present invention, the wet pre-etching process for the source and drain regions lasts for 2 to 4 minutes.

[0013] In one embodiment of the present invention, the first groove is subjected to dry etching, including plasma etching of the first groove to form a second groove with a U-shaped structure, wherein the depth of the second groove is 50~55nm.

[0014] In one embodiment of the present invention, wet etching of the second groove includes using a tetramethylammonium hydroxide solution to wet etch the second groove into a sigma trench by selective etching of the crystal planes of the substrate by the tetramethylammonium hydroxide solution.

[0015] In one embodiment of the present invention, the step of forming the gate structure on the substrate includes:

[0016] A gate material layer is formed on the substrate;

[0017] A hard mask material layer is formed on the gate material layer;

[0018] A sacrificial material layer is formed on the hard mask material layer;

[0019] The sacrificial material layer, the hard mask material layer, and the gate material layer are etched sequentially to form a sacrificial protection layer, a hard mask layer, and a gate layer stacked from top to bottom.

[0020] In one embodiment of the present invention, the step of forming the sidewall structure on the substrate includes:

[0021] A first sidewall material layer is formed on the substrate, the first sidewall material layer covering the gate structure and the source / drain regions;

[0022] The first sidewall material layer of the source / drain region is dry-etched to form the first sidewall.

[0023] In one embodiment of the present invention, the step of forming the sidewall structure on the substrate further includes: forming a second sidewall material layer on the substrate, the second sidewall material layer covering the top of the gate structure, the first sidewall and the source / drain region;

[0024] A third sidewall material layer is formed on the second sidewall material layer;

[0025] The third sidewall material layer and the second sidewall material layer of the source / drain region are etched sequentially to expose the source / drain region, and the second sidewall and the third sidewall are formed sequentially on the outside of the first sidewall.

[0026] In one embodiment of the present invention, after germanium-silicon epitaxial growth is performed in the sigma trench, the method further includes: wet etching to remove the third sidewall.

[0027] A second aspect of the present invention provides a semiconductor structure manufactured using any of the above-described manufacturing methods; the semiconductor structure includes: a substrate, a gate structure, a sidewall structure, a source / drain region, a sigma trench, and a germanium-silicon epitaxial layer; the gate structure and the sidewall structure are formed on the substrate, with the sidewall structure located on both sides of the gate structure; the source / drain region is formed within the substrate on both sides of the gate structure; the sigma trench is formed within the source / drain region; and the germanium-silicon epitaxial layer is formed within the sigma trench.

[0028] This invention provides a method for manufacturing a semiconductor structure. When etching sigma trenches using germanium-silicon processes, a first groove with a certain depth is first formed in the source and drain regions using wet pre-etching. Based on this, dry etching and wet etching are then performed to form sigma trenches.

[0029] Unexpected effect: Wet pre-etching can significantly reduce the consumption of the hard mask above the gate and sidewalls by subsequent dry etching, protect the hard mask above the gate, and wet pre-etching will not cause damage to the hard mask above the gate, nor will it cause side effects to other areas.

[0030] In addition, a tetramethylamine hydroxide (TMAH) solution is used for wet pre-etching of the substrate. Taking advantage of the high crystal plane selectivity of TMAH for silicon substrates, once the inverted triangular structure is etched, even if the etching time of TMAH is briefly increased, the silicon will not continue to be etched. This increases the process window, so that the patterns in different locations and environments of the wafer remain in the first groove stage of the same depth. This not only offsets the differences brought about by the previous process, but also improves the stability of subsequent dry and wet etching, and makes it easier to control the consistency of the critical dimensions of germanium and silicon.

[0031] This application only requires an additional wet pre-etching step before dry etching, without the need for a new photomask. The process is simple, highly operable, and cost-effective. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0033] Figure 1 Transmission electron microscopy (TEM) images of sigma trenches formed in the prior art;

[0034] Figure 2 This is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the substrate structure in one embodiment of the semiconductor structure manufacturing method of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure forming the first sidewall in one embodiment of the semiconductor structure manufacturing method of the present invention;

[0037] Figure 5 This is a schematic diagram of the structure forming the second sidewall material layer in one embodiment of the semiconductor structure manufacturing method of the present invention;

[0038] Figure 6 This is a schematic diagram of the structure forming a third sidewall material layer in one embodiment of the semiconductor structure manufacturing method of the present invention;

[0039] Figure 7 This is a schematic diagram of a method for manufacturing a semiconductor structure according to the present invention, showing the dry etching of a third sidewall material layer in one embodiment.

[0040] Figure 8 This is a schematic diagram of a method for manufacturing a semiconductor structure according to the present invention, specifically a dry etching of a second sidewall material layer.

[0041] Figure 9 This is a schematic diagram of a method for manufacturing a semiconductor structure according to the present invention, in which a wet pre-etching process is used to form a first groove in the source / drain region.

[0042] Figure 10 This is a schematic diagram of a method for manufacturing a semiconductor structure according to the present invention, in which a first groove is formed by dry etching to create a second groove;

[0043] Figure 11 A TEM image showing the formation of a second groove with a U-shaped structure in one embodiment of the semiconductor structure manufacturing method of the present invention.

[0044] Figure 12 A TEM image showing the formation of a U-shaped groove in existing technology;

[0045] Figure 13 This is a schematic diagram of a method for manufacturing a semiconductor structure according to the present invention, in which a second groove is formed by wet etching to create a sigma trench in one embodiment.

[0046] Figure 14 This is a TEM image of a sigma trench obtained in one embodiment of the semiconductor structure manufacturing method of the present invention.

[0047] Figure 15 This is a schematic diagram of a germanium-silicon epitaxial layer formed by germanium-silicon epitaxial growth in one embodiment of the semiconductor structure manufacturing method of the present invention.

[0048] Figure 16 This is a schematic diagram of a method for manufacturing a semiconductor structure according to the present invention, showing the removal of a third sidewall material layer in one embodiment.

[0049] Component designation explanation:

[0050] 100. Substrate; 101. Source / drain region; 102. First trench; 103. Second trench; 104. Sigma trench; 105. Germanium-silicon epitaxial layer; 110. Gate structure; 111. Gate layer; 112. Hard mask layer; 113. Sacrificial protection layer; 120. First sidewall; 121. First sidewall material layer; 122. Second sidewall material layer; 123. Third sidewall material layer. Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0053] In this invention, terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, terms such as "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0054] As described in the background section, PMOS typically employs germanium-silicon epitaxy to grow a compressive stress layer in the source and drain regions. This compressive stress layer applies compressive stress to the PMOS channel, thereby improving its carrier mobility. Currently, the germanium-silicon epitaxy process inevitably damages the hard mask above the gate and on the sidewalls during the etching of the source and drain regions (see...). Figure 1 (The area shown in the dashed circle) leads to a series of problems: ① Premature etching of the hard mask above the gate will cause the sacrificial protective layer above to lose support, resulting in a large number of defects; ② Premature etching of the hard mask above the gate will expose the gate (Poly, amorphous silicon), and subsequent silicon germanium (SiGe) will grow here, creating a source of defects; ③ Subsequent self-alignment (salicide) processes will also form NiSi at the exposed gate, causing device failure; ④ The hard mask above the gate is the polishing stop layer for subsequent ILD CMP, and premature etching will cause polishing to go out of control; ⑤ Loading differences caused by dry etching will accumulate layer by layer, causing the device's electrical parameters to diverge, affecting yield.

[0055] To address the aforementioned issues, this invention provides a method for manufacturing a semiconductor structure and a semiconductor structure manufactured using this method. By adding a wet pre-etching step in the SiGe process to form a first groove of a certain depth in the source and drain regions, the consumption of the hard mask above the gate and the sidewalls by subsequent dry etching can be significantly reduced, thus protecting the hard mask above the gate.

[0056] Please see Figure 2 The method for manufacturing the semiconductor structure of the present invention includes the following steps:

[0057] S1. A substrate 100 is provided, on which a gate structure 110 and a sidewall structure are formed, with the sidewall structure located on both sides of the gate structure 110. Active and drain regions 101 are formed in the substrate 100 on both sides of the gate structure 110 (see...). Figure 4 );

[0058] S2. Perform wet pre-etching on the source / drain region 101 to form the first groove 102 (see...). Figure 9 );

[0059] S3. Dry etching is performed on the first groove 102 to form the second groove 103 (see...). Figure 10 );

[0060] S4. Perform wet etching on the second groove 103 to form a sigma trench 104 (see...). Figure 13 );

[0061] S5. Germanium-silicon epitaxial growth is performed in the sigma trench 104 to form a germanium-silicon epitaxial layer 105 (see...). Figure 15 ).

[0062] The following is combined Figures 3 to 16 The steps in the manufacturing method of the semiconductor structure of the present invention are described in detail.

[0063] Please see Figure 3 In step S1, the substrate 100 provides a process platform for the subsequent formation of semiconductor structures. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate 100 can also be any material suitable for forming semiconductor structures, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), silicon-on-insulator (SOI), or silicon / germanium / silicon stacked substrate.

[0064] An isolation structure (not shown in the figure) is provided within the substrate 100. This isolation structure, such as a field oxide layer or a shallow trench isolation (STI) structure, divides the substrate 100 into multiple active regions. Each active region can form a semiconductor device. In this embodiment, a PMOS semiconductor device is used as an example: an N-well region is formed within the active region, and the source / drain region 101 of the PMOS and the gate structure 110 of the PMOS are formed on the N-well region. The source / drain region 101 is located within the substrate 100 on both sides of the gate structure 110. In other embodiments, a device containing a PMOS, such as a CMOS, can also be formed, in which case a PMOS and an NMOS are formed in two adjacent active regions, respectively.

[0065] The gate structure 110 formed on the substrate 100 includes a gate layer 111, a hard mask layer 112, and a sacrificial protection layer 113. The gate layer 111 is formed above the N-well region and serves as a dummy gate, occupying space for the subsequent formation of the metal gate structure. The gate layer 111 is made of, for example, polysilicon, which is formed using, for example, chemical vapor deposition (CVD). The hard mask layer 112 covers the top of the gate layer 111, protecting it from damage during subsequent etching of the substrate 100 and preventing it from being affected during the subsequent epitaxial growth of the stress layer. The hard mask layer 112 is made of, for example, silicon nitride. The hard mask layer 112 can be formed using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). A sacrificial protection layer 113 covers the top of the hard mask layer 112. The sacrificial protection layer 113 can protect the hard mask layer 112 and prevent it from being prematurely etched during the etching process. The material of the sacrificial protection layer 113 is, for example, silicon dioxide (SiO2), which can be formed by chemical vapor deposition (CVD). In this embodiment, the formation process of the gate structure 110 is exemplified as follows: First, a gate material layer, a hard mask material layer, and a sacrificial material layer are formed sequentially from bottom to top on the surface of the substrate 100. Then, photoresist is spin-coated on the sacrificial material layer. A patterned photoresist layer is formed through exposure and development processes. Using the patterned photoresist layer as a mask, the sacrificial material layer, the hard mask material layer, and the gate material layer are sequentially etched by dry etching, such as plasma etching, to form a gate layer 111, a hard mask layer 112, and a sacrificial protection layer 113 with a stacked structure. In other embodiments, a gate layer 111 may be formed first, followed by the deposition of a hard mask material layer on the gate layer 111, and the hard mask layer 112 may be formed by etching the hard mask material layer. Then, a sacrificial material layer may be deposited on the hard mask layer 112, and the sacrificial protection layer 113 may be formed by etching the sacrificial material layer. The present invention is not limited thereto.

[0066] Furthermore, the gate structure 110 also includes a gate dielectric layer (not shown in the figure). This gate dielectric layer is formed in the N-well region before the gate layer 111 is formed. Its function is to insulate the gate layer 111 from the substrate 100. The material of the gate dielectric layer is, for example, silicon dioxide (SiO2). Silicon dioxide can be formed on the surface of the substrate 100 through a thermal oxidation process, and the gate layer 111 is formed on the gate dielectric layer. In other embodiments, the gate dielectric layer may be formed before the metal gate is formed. The material of the gate dielectric layer may also be a high-dielectric-constant material such as hafnium oxide.

[0067] Please see Figure 3 and Figure 4After forming the gate structure 110, the method further includes forming sidewall structures on both sides of the gate structure 110. The sidewall structures include a first sidewall 120, which can be made of, for example, silicon nitride (SiN). The formation process of the first sidewall 120 is as follows: First, a first sidewall material layer 121 is formed on the substrate 100. The first sidewall material layer 121 covers the top, sidewalls, and source / drain regions 101 on both sides of the gate structure 110. The first sidewall material layer 121 can be formed, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). Then, the first sidewall material layer 121 of the source / drain regions 101 is removed by dry etching, such as plasma etching, leaving the first sidewall material layer 121 on the sidewalls of the gate structure 110 to form the first sidewall 120.

[0068] Please see Figures 5 to 8 The sidewall structure also includes a second sidewall and a third sidewall. The second sidewall is formed outside the first sidewall 120 to protect the first sidewall 120 and prevent it from being prematurely etched in subsequent etching processes. The material of the second sidewall is, for example, silicon dioxide (SiO2). The third sidewall is formed outside the second sidewall to protect both the second and first sidewalls. The material of the third sidewall is, for example, silicon nitride (SiN).

[0069] The formation process of the second and third sidewalls is illustrated below: First, a second sidewall material layer 122 is formed on the substrate 100, covering the top of the gate structure 110, the first sidewall 120, and the source / drain region 101. Then, a third sidewall material layer 123 is formed on the second sidewall material layer 122. Next, the third sidewall material layer 123 and the second sidewall material layer 122 of the source / drain region 101 are etched sequentially to expose the source / drain region 101. The etching process can employ plasma etching in dry etching. That is, the third sidewall material layer 123 of the source / drain region 101 is etched first to expose the second sidewall material layer 122 of the source / drain region 101. During this etching process, the mask layer above and on the sidewalls of the gate layer 111 (the third sidewall material layer 123, and even part of the second sidewall material layer 122) will inevitably be consumed, leading to process variations. Next, the second sidewall material layer 122 of the source / drain region 101 is etched to expose the source / drain region 101. Similarly, this etching process will inevitably consume the mask layer (second sidewall material layer 122, and even the sacrificial protection layer 113 on top of the gate layer 111) and process differences above and on the sidewalls of the gate layer 111. If dry etching is subsequently performed directly on the source / drain region 101, the long etching time and strong physical bombardment will consume a large amount of the mask layer above and on the sidewalls of the gate layer 111, so that during the subsequent wet etching process, the sidewall breaks, causing the hard mask above the gate layer 111 to be etched by the solution and lose its hard mask function.

[0070] Please see Figure 9 Therefore, before dry etching the source / drain region 101, this application first performs step S2 to perform wet pre-etching on the source / drain region 101 to form a first groove 102 in the source / drain region 101. The specific process is as follows: The source / drain region 101 is wet pre-etched using a tetramethylamine hydroxide solution (TMAH). <100> Crystal planes and <111> The etching selectivity of the TMAH on the silicon substrate can reach (40:1) to (70:1), meaning that the TMAH has a high selectivity for silicon etching. <100> The etching rate of the crystal plane is much greater than <111> Because of the crystal plane, when using TMAH solution to pre-etch the silicon substrate, the wet etching of the silicon substrate can be stopped at the crystal plane. <111> The surface is then etched to form a first groove 102 with an inverted triangle at a fixed angle. After the first groove 102 is etched into the inverted triangle, increasing the etching time of TMAH for a short period of time will not continue to etch silicon, thereby increasing the process window. Furthermore, wet etching is less affected by the environment. This step can ensure that patterns in different locations and environments on the wafer remain at the same depth of the first groove 102 stage, thereby offsetting the differences caused by the previous process and making the subsequent germanium-silicon dimensions more uniform.

[0071] Furthermore, the TMAH wet pre-etching time is controlled between 2 and 4 minutes, specifically 2 minutes, 3 minutes, or 4 minutes, etc.

[0072] Please see Figures 10 to 11 Step S3 is executed, where the substrate 100 is further dry-etched based on the first groove 102 to form a second groove 103. Dry etching, for example, employs plasma etching. The isotropic nature of dry etching ensures that the first groove 102 is etched synchronously in all directions, forming a U-shaped second groove 103. Further, the depth of the second groove 103 is 50-55 nm, for example, 50 nm, 52 nm, 54 nm, or 55 nm, etc. Since the wet pre-etching in step S2 has already formed a first groove 102 of a certain depth in the source / drain region 101, continuing dry etching to form a second groove 103 of the same depth significantly reduces the dry etching time, thereby reducing the consumption of the gate layer 111 and sidewalls by dry etching. After this step, the image of the U-shaped second groove 103 formed in the source / drain region under a transmission electron microscope is shown below. Figure 11As shown: In region I of the figure, the sidewalls are undamaged, the surface is smooth, and the top is rounded. This phenomenon indicates that performing wet pre-etching before dry etching can significantly reduce the dry etching time, thereby reducing the wear on the gate layer and sidewalls caused by dry etching. This allows the sidewall structure and the sacrificial protective layer above the gate to completely protect the underlying silicon nitride hard mask. Furthermore, wet pre-etching ensures that patterns in different locations and environments on the wafer remain at the same depth, thus offsetting differences caused by previous processes. Therefore, the depths of the second groove 103 of the U-shaped structure at the wafer center and edge are similar. The U-shaped groove formed by direct dry etching without wet pre-etching is shown in the transmission electron microscope image below. Figure 12 As shown: In region II of the figure, the sidewalls are uneven and the top is pointed. This indicates that without wet pre-etching, direct dry etching will consume the sacrificial protection layer above the sidewall structure and gate layer during the etching process due to the long etching time. As a result, the sacrificial protection layer above the sidewall structure and gate cannot effectively protect the silicon nitride hard mask below. In addition, the dry etching is affected by the pattern environment, which will cause loading differences. Combined with the differences in the previous process accumulation, the U-shaped groove depth at the center and edge of the wafer is significantly different.

[0073] Please see Figures 13 to 14 Next, step S4 is performed, whereby the source / drain regions 101 of the substrate 100 are wet-etched based on the second trench 103 to form a sigma trench 104. Specifically, the wet etching uses the same TMAH solution as the pre-etching solution. The TMAH solution is characterized by... <100> Crystal planes and <111> The etching selectivity for silicon on the crystal plane is as high as 40:1 to 70:1, so the wet etching of silicon can be stopped at... <111> This surface, in turn, forms sigma trenches 104. The sigma trenches 104... <111> The crystal planes are all cross-sections of the four vertices of the dry-etched grooves; the tips of the 104 sigma trenches are located on two sides of one side. <111> At the intersection of surfaces. In other embodiments, ammonia can also be used as the etching solution for the sigma trench 104. After this etching step, the resulting sigma trench 104 is shown in a transmission electron microscope image as follows. Figure 12 As shown, from Figure 12 It can be seen that after the sigma trench 104 is formed, the sidewall structures on both sides of the gate structure 110 are intact, and the hard mask layer 112 above the gate layer 111 does not show any etching damage.

[0074] Furthermore, after the sigma trench 104 etching is completed, a wet cleaning step is also included to remove organic residues, metallic impurities, and particles, ensuring the cleanliness and uniformity of the sigma trench 104 surface, thereby improving device reliability and yield. Wet cleaning, for example, uses a wet cleaning process of SPM (sulfuric acid-hydrogen peroxide mixture, H2SO4 / H2O2) + SC1 (standard cleaning solution 1, NH4OH / H2O2 / H2O) to clean the sigma trench 104.

[0075] Please see Figure 15 Step S5 is executed to form a germanium-silicon epitaxial layer 105 in the sigma trench 104. The specific process is as follows: The wafer structure with the sigma trench 104 formed is moved into the epitaxial chamber, and a silicon source and a germanium source are introduced into the epitaxial chamber to grow germanium-silicon epitaxially until the sigma trench 104 is filled, forming the germanium-silicon epitaxial layer 105. The silicon source is, for example, SiH4 or SiH2Cl2, and the germanium source is, for example, GeH4. Furthermore, during the reaction, auxiliary gases hydrogen (H2) or hydrogen chloride (HCl) can be introduced into the epitaxial chamber. H2 is mainly used to provide a suitable atmosphere and a stable reaction environment, thereby improving the quality and stability of the epitaxial growth; HCl is used to remove impurities and residues generated during the reaction in the sigma trench 104. In this step, since the sidewall structures on both sides of the gate structure 110 are intact and the gate layer 111 is not exposed, the germanium-silicon epitaxial layer will only be formed in the exposed area (within the sigma trench 104) and will not be formed on the gate layer 111, thereby reducing the generation of defects.

[0076] Please see Figure 16 After the germanium-silicon epitaxial layer 105 is formed, an etching process is performed to remove the remaining third sidewall material layer 123. The etching process is, for example, hot phosphoric acid wet etching.

[0077] This invention's semiconductor manufacturing method adds a wet pre-etching step to the SiGe process, forming a first groove in the source / drain region. This significantly reduces the consumption of the hard mask above the gate and sidewalls during subsequent dry etching, protecting the hard mask above the gate. This invention utilizes the high crystal plane selectivity of TMAH (Transient Aperture Heating) for silicon etching, preventing damage to the hard mask above the gate and avoiding side effects on other areas during pre-etching. Furthermore, it ensures that patterns in different locations and environments on the wafer remain at the same depth in the first groove stage. This compensates for differences introduced by previous processes while improving the stability of subsequent dry and wet etching, making it easier to control the consistency of SiGe critical dimensions.

[0078] Please see Figure 15 and Figure 16 The present invention also provides a semiconductor structure, which is manufactured using the manufacturing method described above.

[0079] The aforementioned semiconductor structure includes a substrate 100, a gate structure 110, a sidewall structure, and a germanium-silicon epitaxial layer 105. The substrate 100 is a silicon substrate. In other embodiments, the substrate 100 can also be any material suitable for forming a semiconductor structure, such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), silicon-on-insulator (SOI), or a silicon / germanium / silicon stacked substrate. An isolation structure (not shown in the figure) is provided within the substrate 100 to insulate adjacent devices. This isolation structure can be, for example, a shallow trench isolation (STI) structure or a field oxide layer. An active region is formed between adjacent isolation structures, within which a semiconductor device can be formed. In this application, the semiconductor device is a PMOS device, and an N-well region is formed within the active region. In other embodiments, the semiconductor device may also be a PMOS-containing device, such as a CMOS, where a PMOS device and an NMOS device are formed in adjacent active regions respectively. In this case, an N-well region is formed in the active region corresponding to the PMOS device, and a P-well region is formed in the active region corresponding to the NMOS device. The following only describes the PMOS device.

[0080] A gate structure 110 is formed above the N-well region. The gate structure 110 includes, from bottom to top, a gate layer 111, a hard mask layer 112, and a sacrificial protection layer 113. The gate layer 111 serves as a dummy gate, occupying space for the subsequent formation of the metal gate structure. The material of the gate layer 111 is, for example, polysilicon. The hard mask layer 112 covers the top of the gate layer 111 and protects it from damage during subsequent etching of the substrate 100. The material of the hard mask layer 112 is, for example, silicon nitride. The sacrificial protection layer 113 covers the top of the hard mask layer 112 and can self-consume to protect the hard mask layer 112, preventing it from being consumed during etching. The material of the sacrificial protection layer 113 is, for example, silicon oxide. Furthermore, the gate structure 110 may also include a gate dielectric layer (not shown in the figure), which is formed between the substrate 100 and the gate layer 111, thereby insulating the gate layer 111 from the substrate 100. The material of the gate dielectric layer is, for example, silicon oxide.

[0081] Sidewall structures are formed on both sides of the gate structure 110. The sidewall structures include a first sidewall 120, which is made of, for example, silicon nitride. The sidewall structures may also include a second sidewall, formed outside the first sidewall 120, which is made of, for example, silicon dioxide. Furthermore, the sidewall structures also include a third sidewall, formed outside the second sidewall, which is also made of, for example, silicon nitride. The third sidewall may be partially consumed during subsequent etching. The third sidewall will also be removed in subsequent processes.

[0082] Please see Figures 9 to 11 A source / drain region 101 is formed within the substrate 100 on both sides of the gate structure 110. A germanium-silicon epitaxial layer 105 is formed within the source / drain region 101, and the upper surface of the germanium-silicon epitaxial layer 105 protrudes from the upper surface of the substrate 100. The germanium-silicon epitaxial layer 105 can increase the compressive stress of the PMOS device, thereby increasing the carrier mobility of the channel and improving the performance of the PMOS device. The germanium-silicon epitaxial layer 105 is first etched to form a sigma trench 104 in the source / drain region 101, and then epitaxially grown inside and outside the sigma trench 104 using epitaxial technology. In this application, when etching the sigma trench 104, a first trench 102 is first formed by wet pre-etching, then a second trench 103 is formed by dry etching on the basis of the first trench 102, and then the sigma trench 104 is formed by wet etching on the basis of the second trench 103. Both wet pre-etching and wet etching utilize TMAH solution. The high crystal plane selectivity of TMAH for the silicon substrate allows etching to stop at [the desired point]. <111> On the crystal surface, a first groove 102 with a fixed angle of inverted triangle is formed during pre-etching, and a sigma trench 104 is formed during wet etching. The wet pre-etching step not only reduces the time of subsequent dry etching, thereby reducing dry etching damage, but also ensures that patterns in different locations and environments on the wafer remain at the same depth of the first groove stage, thus offsetting the differences brought about by the previous layer process and making the subsequent germanium-silicon dimensions more uniform.

[0083] In summary, the semiconductor structure manufacturing method provided by this invention, during the etching of sigma trenches in a germanium-silicon process, first utilizes wet pre-etching to form a first trench of a certain depth in the source / drain region, and then performs dry etching and wet etching to form the sigma trench. This method can significantly reduce the consumption of the hard mask above the gate and sidewalls by dry etching, protecting the hard mask above the gate. Furthermore, wet pre-etching does not damage the hard mask above the gate, nor does it cause side effects to other areas. In addition, the high crystal plane selectivity of TMAH for silicon etching ensures that patterns in different locations and environments on the wafer remain at the same depth in the first trench stage. This offsets the differences introduced by the previous layer process and improves the stability of subsequent dry and wet etching, making it easier to control the consistency of SiGe critical dimensions. Therefore, this invention effectively overcomes some practical problems in the prior art, thus having high utilization value and practical significance.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided on which a gate structure and a sidewall structure are formed, the sidewall structure being located on both sides of the gate structure, and active / drain regions are formed in the substrate on both sides of the gate structure. The source / drain region is pre-etched using a tetramethylamine hydroxide solution to form an inverted triangular first groove, wherein the wet pre-etching stops at... <111> On the crystal surface, thus forming a first groove of consistent depth at different locations on the wafer; Dry etching is then performed on the basis of the first inverted triangular groove to form a second U-shaped groove. The dry etching time is shortened due to the presence of the first inverted triangular groove. The second groove is wet-etched to form a sigma trench; Germanium-silicon epitaxial growth is performed in the sigma trench to form a germanium-silicon epitaxial layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The wet pre-etching process for the source and drain regions lasts for 2 to 4 minutes.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first groove is dry etched, including plasma etching of the first groove to form a second groove with a U-shaped structure, the depth of the second groove being 50~55nm.

4. The method for manufacturing a semiconductor structure according to any one of claims 1-3, characterized in that, The second groove is wet-etched, including wet etching the second groove with a tetramethylammonium hydroxide solution, wherein the tetramethylammonium hydroxide solution selectively etches the crystal plane of the substrate to form a sigma trench.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming the gate structure on the substrate includes: A gate material layer is formed on the substrate; A hard mask material layer is formed on the gate material layer; A sacrificial material layer is formed on the hard mask material layer; The sacrificial material layer, the hard mask material layer, and the gate material layer are etched sequentially to form a sacrificial protection layer, a hard mask layer, and a gate layer stacked from top to bottom.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming the sidewall structure on the substrate includes: A first sidewall material layer is formed on the substrate, the first sidewall material layer covering the gate structure and the source / drain regions; The first sidewall material layer of the source / drain region is dry-etched to form the first sidewall.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The step of forming the sidewall structure on the substrate further includes: A second sidewall material layer is formed on the substrate, the second sidewall material layer covering the top of the gate structure, the first sidewall and the source / drain regions; A third sidewall material layer is formed on the second sidewall material layer; The third sidewall material layer and the second sidewall material layer of the source / drain region are etched sequentially to expose the source / drain region, and the second sidewall and the third sidewall are formed sequentially on the outside of the first sidewall.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, After the germanium-silicon epitaxial growth is performed in the sigma trench, the method further includes: wet etching to remove the third sidewall.

9. A semiconductor structure, characterized in that, The semiconductor structure is manufactured using any one of the manufacturing methods described in claims 1-8; the semiconductor structure comprises: Substrate; A gate structure is formed on the substrate; Sidewall structures are formed on both sides of the gate structure; Source and drain regions are formed in the substrate on both sides of the gate structure; Sigma trenches are formed within the source / drain region; A germanium-silicon epitaxial layer is formed within the sigma trench.

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