A semiconductor epitaxial structure, a preparation method thereof and a semiconductor device

Abstract

The application provides a semiconductor epitaxial structure, a preparation method thereof and a semiconductor device. The semiconductor epitaxial structure comprises a substrate, an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer arranged in sequence, the p-type semiconductor layer comprises a first p-type nitride layer, at least one P-type barrier layer is arranged in a direction away from the light-emitting layer, the P-type barrier layer comprises a P-type barrier front layer, a local structure insertion layer and a P-type barrier rear layer arranged in sequence in the direction away from the light-emitting layer; the local structure insertion layer comprises a first microstructure and a second microstructure, a surface of the P-type barrier front layer and the rear layer in contact has a first groove, the first microstructure is arranged in the first groove; a surface of the P-type barrier rear layer and the front layer in contact has a second groove corresponding to the first groove, the second microstructure is arranged in the second groove. A polarization effect can be formed between the first microstructure and the second microstructure due to a band gap difference, thereby forming a two-dimensional hole gas and improving the hole concentration of the first p-type nitride layer.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a semiconductor epitaxial structure and its preparation method, and a semiconductor device. Background Technology

[0002] In recent years, significant progress has been made in the research of nitride-based devices, but many challenges remain. Low-resistivity p-type doping is one of the obstacles hindering the widespread application of nitride materials. Mg is the primary p-type dopant, but the Mg-H passivation effect has become a major factor restricting the development of nitride devices (such as GaN-based devices). This is because the activation efficiency of Mg is typically less than 1%, and especially with increasing Al content, the acceptor ionization energy increases, further complicating the achievement of high carrier concentration and high mobility. Furthermore, since electrons migrate faster than holes, and the concentration of free electrons is higher than that of holes, the distribution of electrons and holes in the emitting layer is easily uneven. Holes tend to concentrate in the emitting layer closer to the p-type layer, while the hole concentration gradually decreases towards the n-type layer, which is detrimental to electron-hole recombination.

[0003] Therefore, improving the doping efficiency and conductivity of p-type nitride materials is of great significance for the application of nitride materials, and there is an urgent need to propose a semiconductor epitaxial structure with a p-type nitride layer with high hole concentration. Summary of the Invention

[0004] To solve all or part of the above-mentioned technical problems, the present invention provides the following technical solutions: One objective of this invention is to provide a semiconductor epitaxial structure comprising an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer sequentially disposed therefrom. The p-type semiconductor layer includes a first p-type nitride layer. The first p-type nitride layer includes at least one p-type barrier layer disposed along a direction away from the light-emitting layer. The p-type barrier layer includes a p-type barrier front layer, a localized structure insertion layer, and a p-type barrier back layer sequentially disposed along a direction away from the light-emitting layer. The localized structure insertion layer includes a first microstructure and a second microstructure sequentially disposed along a direction away from the light-emitting layer. The surface of the p-type barrier front layer in contact with the p-type barrier back layer has a first groove, and the first microstructure is disposed within the first groove. The surface of the p-type barrier back layer in contact with the p-type barrier front layer has a second groove corresponding to the first groove, and the second microstructure is disposed within the second groove.

[0005] This invention incorporates a localized structure insertion layer between the front and rear layers of a P-type barrier. The polarization effect, created by the bandgap difference between the relatively distributed first and second microstructures within this insertion layer, generates a two-dimensional hole gas, thereby increasing the hole concentration in the P-type barrier layer. Compared to conventional polarization, the polarization effect between the first and second microstructures effectively shields the carrier capture by dislocation defects during electrical injection, thus improving the semiconductor's photoelectric stability and aging performance, and reducing the sharp drop in efficiency under high current conditions.

[0006] The semiconductor epitaxial structure provided by this invention can provide high-concentration hole injection, balance the electron injection of the n-type semiconductor layer and the hole injection balance of the p-type semiconductor layer, thereby improving the brightness of the semiconductor epitaxial structure, reducing the operating voltage, reducing the droop effect (i.e., the phenomenon of reduced light efficiency as the current increases) that occurs in the semiconductor epitaxial structure with increasing injection current, and is suitable for high-current operating conditions, meeting the application requirements of high-power epitaxial structures.

[0007] In some embodiments, the first microstructure includes an AlN microstructure, and the second microstructure includes an InN microstructure. The AlN and InN microstructures have a large bandgap difference, which can create a strong polarization effect and increase the hole concentration.

[0008] In some embodiments, the front layer of the P-type barrier is a front layer containing Al nitride of the p-type barrier, and the back layer of the P-type barrier is a back layer containing Al nitride of the p-type barrier.

[0009] In some embodiments, the p-type Al-containing nitride front layer has a first surface and a second surface opposite to each other, the second surface being close to the p-type Al-containing nitride back layer; the molar concentration of Al in the p-type Al-containing nitride front layer decreases along the direction from the first surface to the second surface, and the molar concentration of Al in the p-type Al-containing nitride back layer is uniformly distributed.

[0010] The energy required for charge carriers to cross the nitride barrier is related to the Al content in the nitride material. To obtain a sufficiently high electronic barrier, a sufficient Al content is necessary. By decreasing the Al content in the front layer of the p-type barrier, a high electronic transition barrier can be ensured in the first p-type nitride layer, increasing the confinement of electrons in the emitting layer and reducing the probability of electrons recombinating with holes in the second p-type nitride layer, thus improving hole injection efficiency. On the other hand, because a high nitride barrier, while blocking electrons, also creates a high barrier to holes, a relatively low and sufficient Al content is required to achieve high hole injection in the emitting layer. Decreasing the Al content in the front layer of the p-type barrier ensures a sufficiently high electronic barrier while utilizing the low Al content in the back layer to improve the doping efficiency of the p-type barrier. The relatively low and uniform Al content in the back layer of the p-type barrier can also reduce the incorporation potential of Ga atoms formed after the decomposition of the GaN etching layer in step S6 of the preparation method, reducing lattice distortion in the back layer of the p-type barrier and improving crystal quality. This allows for the achievement of excellent carrier injection performance and improved uniformity of carrier distribution in the luminescent layer.

[0011] In some preferred embodiments, the difference between the Al component concentration at the first surface of the p-type Al-nitride front layer and the Al component concentration at its second surface is greater than 0.1.

[0012] In some preferred embodiments, the molar ratio of Al at the first surface is 0.1 to 0.5, and the molar ratio of Al at the second surface is 0 to 0.1.

[0013] In some embodiments, the first p-type nitride layer has multiple p-type barrier layers. By setting multiple p-type barrier layers, localized structure insertion layers with different depths are formed in the longitudinal direction, increasing the hole distribution concentration in the longitudinal direction, reducing the resistance of the first p-type nitride layer, and enhancing hole transport in the longitudinal direction.

[0014] In some embodiments, the in-plane local dimensions of the first and second microstructures are 200-1000 nm. The in-plane local dimension refers to the dimension in the plane, i.e., in the lateral direction.

[0015] In some embodiments, the thickness of the front layer of the P-type barrier is 10-20 nm, and the thickness of the back layer of the P-type barrier is 5-10 nm.

[0016] In some embodiments, the materials of the P-type barrier front layer and the P-type barrier back layer can be one of GaN, InN, AlN, AlGaN, InGaN, AlInN, and AlInGaN, but are not limited to these.

[0017] In some embodiments, the p-type semiconductor layer further includes a second p-type nitride layer disposed on the side of the first p-type nitride layer away from the light-emitting layer.

[0018] In some embodiments, the thickness of the second p-type nitride layer is 50-150 nm.

[0019] In some embodiments, the material of the second p-type nitride layer can be one of GaN, InN, AlN, AlGaN, InGaN, AlInN, and AlInGaN, but is not limited to this.

[0020] In some embodiments, the thickness of the n-type semiconductor layer is 1-5 μm.

[0021] In some embodiments, the light-emitting layer includes a plurality of light-emitting units arranged sequentially along a direction away from the n-type semiconductor layer.

[0022] In some embodiments, the light-emitting layer includes 2-15 light-emitting units, each light-emitting unit including a quantum well layer of 1-5 nm and a quantum barrier layer of 6-25 nm.

[0023] The second objective of this invention is to provide a method for preparing a semiconductor epitaxial structure, comprising: An n-type semiconductor layer and a light-emitting layer are sequentially grown on a substrate; A p-type semiconductor layer is grown on the light-emitting layer; The p-type semiconductor layer includes a first p-type nitride layer, which includes at least one p-type barrier layer disposed along a direction away from the light-emitting layer. The p-type barrier layer includes a p-type barrier front layer, a localized structure insertion layer, and a p-type barrier back layer disposed sequentially along a direction away from the light-emitting layer. The localized structure insertion layer includes a first microstructure and a second microstructure disposed sequentially along a direction away from the light-emitting layer. The surface of the p-type barrier front layer that contacts the p-type barrier back layer has a first groove, in which the first microstructure is disposed. The surface of the p-type barrier back layer that contacts the p-type barrier front layer has a second groove corresponding to the first groove, in which the second microstructure is disposed.

[0024] In some embodiments, growing a p-type semiconductor layer on the light-emitting layer includes: S1. Under the condition of introducing an In source active agent, a P-type barrier front layer is grown on the light-emitting layer; S2. Under inert atmosphere conditions, an Al deposition layer is formed on the front layer of the P-type barrier; S3. Under inert atmosphere conditions, a Ga deposition layer is formed on the Al deposition layer; S4. Under inert atmosphere conditions, the structure obtained in step S3 is subjected to a first thermal annealing treatment to allow In in the front layer of the P-type barrier to diffuse to the surface of the front layer of the P-type barrier and the Al deposition layer to form the second microstructure, and to allow Al in the Al deposition layer to diffuse to the interior of the front layer of the P-type barrier to form the first microstructure. S5. Under reducing atmosphere conditions, a nitrogen source is introduced to perform N thermal surface treatment on the structure obtained in S4, so that the Ga deposited layer becomes a GaN layer. S6. Under reducing atmosphere conditions, the structure obtained in S5 is subjected to a second thermal annealing treatment to decompose the GaN layer into Ga dangling bonds. S7. Grow a Ga-containing P-type barrier back layer on the structure obtained in S6, thereby forming the P-type barrier layer.

[0025] The method provided by this invention can form a localized structure insertion layer between a P-type barrier front layer and a P-type barrier back layer, consisting of relatively distributed AlN and InN microstructures. Specifically, the In-N bond energy in the P-type barrier front layer grown under In-source activator conditions is relatively weak, thus forming localized In-N bond states. During the first thermal annealing process, the locally distributed In in the P-type barrier front layer precipitates and diffuses to the surface of the P-type barrier front layer to form InN microstructures. Furthermore, Al in the Al deposition layer diffuses into the interior of the P-type barrier front layer during the first thermal annealing process to form AlN microstructures. The Ga deposition layer can protect the diffusion of the Al deposition layer, allowing it to diffuse uniformly into the interior of the P-type barrier front layer. The N thermal surface treatment in step S5 nitrides the Ga deposition layer to form GaN, and then the second thermal annealing process in S6 fully etches and decomposes the GaN to form Ga dangling bonds. These Ga dangling bonds are incorporated into the surface of the P-type barrier back layer during the growth of the P-type barrier back layer in step S7. The Al and Ga deposits diffuse and decompose sufficiently, resulting in a final structure that does not contain either Al or Ga deposits.

[0026] In some embodiments, the P-type barrier front layer includes a first barrier sub-layer and a second barrier sub-layer, and step S1 specifically includes: S11. The In source active agent is introduced at a first flow rate to grow the first barrier front layer on the light-emitting layer; S12. The In source active agent is introduced at a second flow rate to grow the second barrier front layer on the first barrier front layer, thereby forming the P-type barrier front layer. Wherein, the first flow rate is less than the second flow rate.

[0027] Firstly, using a relatively low flow rate of In source activator in the first barrier layer ensures sufficient In source activator supply while preventing lattice stress distortion caused by the incorporation of In source activator in the first barrier layer, which would lead to increased defects and the formation of defect light absorption and leakage channels. Secondly, the first barrier layer provides a stress-relieving growth template for the second barrier layer, improving the incorporation of In source activator in the second barrier layer and thus providing more uniformly distributed local diffusion centers. Simultaneously, the relatively low first flow rate avoids large lattice distortion caused by the introduction of high flow rate In source activator in the second barrier layer, preventing uniform composition distribution, improving dopant diffusion uniformity, and enhancing carrier expansion capability within the second barrier layer.

[0028] In some preferred embodiments, the ratio of the first flow rate to the second flow rate is less than 1:3.

[0029] In some preferred embodiments, the first flow rate is 100-500 sccm, and the second flow rate is 1000-2000 sccm.

[0030] In some embodiments, the In-source surfactant can be any In-source surfactant known in the art, such as one or more combinations of trimethylindium (TMIn), triethylindium, and dimethylethylindium, but is not limited thereto.

[0031] In some embodiments, growing the P-type barrier front layer includes: introducing an In-source activator at a temperature of 700-800°C and a pressure of 300-600 torr to grow a layer with a thickness of 10-20 nm and a Mg doping concentration of 2 × 10⁻⁶. 19 -2×10 20 cm -3 The front layer of the P-type barrier.

[0032] In some embodiments, depositing the Al deposition layer includes: performing an Al thermal surface treatment for 20-180 seconds by introducing an Al source under conditions of 750-850°C, 100-300 torr, and an inert atmosphere. The Al source can be any one or a combination of Al sources known in the art, such as trimethylaluminum (TMAl), TEAl, etc.

[0033] In some embodiments, depositing the Ga deposition layer includes: performing Ga thermal surface treatment for 10-120 seconds by introducing a Ga source under conditions of 750-850°C, 100-300 torr pressure, and an inert atmosphere. The Ga source can be any one or a combination of Ga sources known in the art, such as trimethylgallium (TMG), TEG, etc.

[0034] In some embodiments, the temperature of the first thermal annealing treatment is 800-900°C, the pressure is 100-300 torr, and the time is 20-100s. If the temperature of the first thermal annealing treatment is too low, the precipitation ability of In atoms in the p-type barrier layer will be reduced, thus making it impossible to form a uniformly distributed diffusion and difficult to form a diffusion microstructure. If the temperature is too high, it will cause the Al deposition layer to diffuse to the surface of the Ga deposition layer, which will also make it difficult to form a diffusion microstructure.

[0035] In some embodiments, the N-thermal surface treatment is performed at a temperature of 850-950°C, a pressure of 100-300 torr, and a time of 40-300 seconds.

[0036] In some embodiments, the temperature of the second thermal annealing treatment is 950-1050°C, the pressure is 300-600 torr, and the time is 30-90s.

[0037] In some embodiments, growing the P-type barrier back layer includes: growing a layer with a thickness of 5-10 nm and a Mg doping concentration of 2×10⁻⁶ under conditions of a temperature of 950-1050°C and a pressure of 100-300 torr. 19 -2×10 20 cm -3 The P-type barrier back layer. Growing the P-type barrier back layer at a relatively high temperature can yield a high-quality P-type barrier back layer, shielding the extension of surface defects in the P-type barrier front layer and improving the leakage current performance of the epitaxial structure.

[0038] In some embodiments, steps S1 to S7 are repeated multiple times to form a first p-type nitride layer having multiple p-type barrier layers.

[0039] During the periodic cycle, localized structure insertion layers with different depths are formed in the thickness direction, which increases the hole concentration in the longitudinal distribution, increases the hole concentration in the front layer of the P-type barrier, reduces the resistance of the front layer of the P-type barrier, and enhances the transmission of holes in the thickness direction.

[0040] In some preferred embodiments, steps S1 to S7 are repeated 2 to 8 times.

[0041] In some embodiments, growing the n-type semiconductor layer includes: growing a layer with a thickness of 1-5 μm and a Si doping concentration of 1×10⁻⁶ under conditions of a temperature of 1050-1250°C and a pressure of 100-300 torr. 18 -1×10 19 cm -3 n-type semiconductor layer.

[0042] In some embodiments, the light-emitting layer includes a plurality of light-emitting units arranged sequentially along a direction away from the n-type semiconductor layer, and the growth of the light-emitting units includes: Quantum well layers with a thickness of 1-5 nm are grown under conditions of temperature 650-850℃ and pressure 150-350 torr. A quantum barrier layer with a thickness of 6-25 nm is grown on the quantum well layer under conditions of temperature of 700-950℃ and pressure of 150-350 torr.

[0043] In some embodiments, the preparation method further includes growing a second p-type nitride layer on the side of the first p-type nitride layer away from the light-emitting layer.

[0044] In some embodiments, the growth of the second p-type nitride layer includes: growing a thickness of 50-150 nm and a Mg doping concentration of 1×10⁻⁶ under conditions of a temperature of 950-1050°C and a pressure of 200-600 torr. 19 -1×10 20 cm -3 The second p-type nitride layer.

[0045] A third objective of this invention is to provide a semiconductor epitaxial structure, which is prepared by the method described above.

[0046] A fourth objective of this invention is to provide a semiconductor device comprising any of the semiconductor epitaxial structures described in any one of the claims.

[0047] Compared with the prior art, the present invention has at least the following beneficial effects: This invention forms a localized structure insertion layer with a relatively distributed first microstructure and a second microstructure in a p-type barrier layer. By utilizing the difference in band gap between the first and second microstructures, a polarization effect is formed, thereby creating a two-dimensional hole gas and increasing the hole concentration in the p-type barrier layer. Compared with conventional polarization, the polarization effect between the first and second microstructures can effectively shield the capture of carriers by dislocation defects during electrical injection, thereby improving the photoelectric stability and aging performance of the semiconductor epitaxial structure and reducing the sharp drop in efficiency under high current conditions.

[0048] The first microstructure includes an AlN microstructure, and the second microstructure includes an InN microstructure. The large band gap difference between the AlN and InN microstructures can create a strong polarization effect, significantly increasing the hole concentration.

[0049] The semiconductor epitaxial structure provided by this invention has a high concentration of hole injection, which can balance the electron injection of the n-type semiconductor layer and the hole injection of the p-type semiconductor layer, improve the brightness of the semiconductor epitaxial structure, reduce the operating voltage, and reduce the droop effect that occurs in the semiconductor epitaxial structure with increasing injection current. The semiconductor epitaxial structure provided by this invention is suitable for high-current operating conditions, meeting the current application requirements for high-power epitaxial wafers. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the semiconductor epitaxial structure provided in one embodiment of this application; Figure 2 This is another schematic diagram of the semiconductor epitaxial structure provided in one embodiment of this application; Figure 3 This is another schematic diagram of a semiconductor epitaxial structure provided in one embodiment of this application; 100 - Substrate, 200 - n-type semiconductor layer, 300 - Light-emitting layer, 401 - P-type barrier layer, 4011 - P-type barrier front layer, 4012 - P-type barrier back layer, 4013 - First microstructure, 4014 - Second microstructure, 402 - Second p-type nitride layer. Detailed Implementation

[0052] The technical solutions of the present invention will be described in detail below with reference to specific embodiments, so that those skilled in the art can better understand and implement the technical solutions of the present invention. The specific functional details disclosed herein should not be construed as limiting, but are merely intended to form the basis of the claims and to teach those skilled in the art to employ the representative basis of the invention in different ways in any suitable detailed embodiment.

[0053] Please see Figure 1 , Figure 1 This is a schematic diagram of the semiconductor epitaxial structure provided by the present invention. The semiconductor epitaxial structure includes a substrate 100, an n-type semiconductor layer 200, a light-emitting layer 300, and a p-type semiconductor layer disposed sequentially.

[0054] The p-type semiconductor layer includes a first p-type nitride layer; the first p-type nitride layer includes at least one p-type barrier layer 401 disposed in a direction away from the light-emitting layer 300, the p-type barrier layer 401 includes a p-type barrier front layer 4011, a local structure insertion layer and a p-type barrier back layer 4012 disposed sequentially in a direction away from the light-emitting layer 300; the local structure insertion layer includes a first microstructure 4013 and a second microstructure 4014 disposed sequentially in a direction away from the light-emitting layer 300, the surface of the p-type barrier front layer 4011 and the p-type barrier back layer 4012 having a first groove, the first microstructure 4013 being disposed in the first groove; the surface of the p-type barrier back layer 4012 and the p-type barrier front layer 4011 having a second groove corresponding to the first groove, the second microstructure 4014 being disposed in the second groove.

[0055] By introducing a localized structure insertion layer into the P-type barrier layer, a two-dimensional hole gas is formed by utilizing the polarization effect between the relatively distributed first and second microstructures, thereby increasing the hole concentration. Compared to conventional polarization, the localized state structure with polarization effect can effectively shield the capture of charge carriers by dislocation defects during electrical injection, improve photoelectric stability and aging performance, and reduce the sharp drop in efficiency of epitaxial structures under high current conditions.

[0056] In one embodiment, the first microstructure includes an AlN microstructure, and the second microstructure includes an InN microstructure.

[0057] In one embodiment, the p-type barrier front layer is a p-type Al-containing nitride front layer, and the p-type barrier back layer is a p-type Al-containing nitride back layer. The p-type Al-containing nitride front layer has opposing first and second surfaces, with the second surface close to the p-type Al-containing nitride back layer; the molar concentration of Al in the p-type Al-containing nitride front layer decreases along the direction from the first surface to the second surface, and the molar concentration of Al in the p-type Al-containing nitride back layer is uniformly distributed.

[0058] By reducing the Al composition in front of the P-type barrier, excellent carrier injection performance can be obtained, and the uniformity of carrier distribution in the emitting layer can be improved.

[0059] Please see Figure 2 In another embodiment, the first p-type nitride layer includes a plurality of p-type barrier layers 401. This forms a localized structure insertion layer with different depths distributed along the thickness direction, increasing the hole concentration in the longitudinally distributed layer, increasing the hole concentration in the front layer of the p-type barrier, reducing the resistance of the front layer of the p-type barrier, and enhancing hole transport in the thickness direction.

[0060] Please see Figure 3 In another embodiment, the p-type semiconductor layer further includes a second p-type nitride layer 402 disposed on the side of the first p-type nitride layer away from the light-emitting layer 300.

[0061] The present invention also provides a method for preparing a semiconductor epitaxial structure, the method comprising: (1) An n-type semiconductor layer and a light-emitting layer are grown sequentially on the substrate.

[0062] The substrate serves as the support for the growth of the semiconductor epitaxial structure, while the n-type semiconductor layer is the injection layer for charge carriers (electrons) in the light-emitting layer.

[0063] The method for growing an n-type semiconductor layer can be as follows: Under conditions of 1050-1250℃ and 100-300 torr, a thickness of 1-5 μm and a Si doping concentration of 1×10⁻⁶ can be grown. 18 -1×10 19 cm -3 n-type semiconductor layer.

[0064] The light-emitting layer serves as the active region of the epitaxial structure, where charge carriers recombine to emit light. The light-emitting layer comprises multiple light-emitting units arranged sequentially along a direction away from the n-type semiconductor layer. The growth of these light-emitting units includes: a1: A quantum well layer with a thickness of 1-5 nm is grown under conditions of temperature of 650-850℃ and pressure of 150-350 torr; a2: A quantum barrier layer with a thickness of 6-25 nm is grown on a quantum well layer under conditions of temperature of 700-950℃ and pressure of 150-350 torr.

[0065] (2) Growing a p-type semiconductor layer on the light-emitting layer, including the following steps S1~S7: S1. Under the condition of introducing an In source active agent, a P-type barrier front layer is grown on the light-emitting layer.

[0066] In one embodiment, growing the p-type barrier front layer includes: introducing an In source activator at a temperature of 700-800°C and a pressure of 300-600 torr to grow a layer with a thickness of 10-20 nm and a Mg doping concentration of 2 × 10⁻⁶. 19 -2×10 20 cm -3 The front layer of the P-type barrier.

[0067] Growing a P-type barrier front layer at a relatively low growth temperature (i.e., 700-800℃) can promote the formation of localized In distribution within the P-type barrier front layer.

[0068] In another embodiment, the P-type barrier front layer includes a first barrier sub-front layer and a second barrier sub-front layer, and step S1 specifically includes: S11. In source active agent is introduced at a first flow rate to grow the first barrier front layer on the light-emitting layer.

[0069] Under conditions of 700-800℃ and 300-600 torr, an In-source activator with a flow rate of 100-500 sccm is introduced to grow a thickness of 2-5 nm and a Mg doping concentration of 2×10⁻⁶. 19 -2×10 20 cm -3 The first stronghold of the front layer.

[0070] The first barrier front layer formed by introducing the In source surfactant at a relatively low flow rate can serve as a growth template, improving the uniformity of the In local state distribution in the second barrier front layer.

[0071] S12. In-source active agent is introduced at a second flow rate to grow a second barrier front layer on the first barrier front layer, thereby forming a P-type barrier front layer.

[0072] Under conditions of 700-800℃ and 300-600 torr, an In-source activator with a flow rate of 1000-2000 sccm is introduced to grow a thickness of 2-5 nm and a Mg doping concentration of 2×10⁻⁶. 19 -2×10 20 cm -3 The second barrier in front layer.

[0073] By introducing an In source activator at a relatively high flow rate to form a localized In state distribution, the uniformity of the localized In state distribution is improved based on the first barrier layer as a growth template.

[0074] S2. Under inert atmosphere conditions, an Al deposition layer is formed on the front layer of the P-type barrier.

[0075] In one embodiment, the method for depositing an Al deposition layer includes: introducing an Al source for Al thermal surface treatment for 20-180 seconds under conditions of a temperature of 750-850°C, a pressure of 100-300 torr, and an inert atmosphere.

[0076] S3. Under inert atmosphere conditions, a Ga deposition layer is formed on the Al deposition layer.

[0077] In one embodiment, the method for depositing a Ga deposition layer includes: introducing a Ga source to perform Ga thermal surface treatment for 10-120 seconds under conditions of a temperature of 750-850°C, a pressure of 100-300 torr, and an inert atmosphere.

[0078] S4. Under inert atmosphere conditions, the structure obtained in step S3 is subjected to a first thermal annealing treatment.

[0079] The first thermal annealing process causes In in the P-type barrier front layer to diffuse to the surface of the P-type barrier front layer in contact with the Al deposition layer, forming a second microstructure (i.e., InN microstructure), and causes Al in the Al deposition layer to diffuse into the interior of the P-type barrier front layer, forming a first microstructure (i.e., AlN microstructure).

[0080] The Ga deposit layer provides protection for the diffusion of the Al deposit layer, ensuring that the Al deposit layer diffuses uniformly into the front layer of the P-type barrier.

[0081] In one embodiment, a first thermal annealing treatment is performed for 20-100 seconds in an inert gas atmosphere at a temperature of 800-900°C and a pressure of 100-300 torr.

[0082] S5. Under reducing atmosphere conditions, nitrogen source is introduced to perform N-thermal surface treatment on the structure obtained in S4.

[0083] During the N-thermal surface treatment process, the Ga deposited layer becomes a GaN layer.

[0084] In one embodiment, N-thermal surface treatment is performed for 40-300 seconds in a reducing gas atmosphere at a temperature of 850-950°C and a pressure of 100-300 torr.

[0085] S6. Under reducing atmosphere conditions, the structure obtained in S5 is subjected to a second thermal annealing treatment.

[0086] During the second thermal annealing process, the GaN layer is decomposed into Ga dangling bonds.

[0087] In one embodiment, a second thermal annealing treatment is performed for 30-90 seconds in a reducing gas atmosphere at a temperature of 950-1050°C and a pressure of 300-600 torr.

[0088] S7. Grow a Ga-containing P-type barrier back layer on the structure obtained in S6, thereby forming a P-type barrier layer.

[0089] During the growth of the P-type barrier back layer, the Ga dangling bonds formed in step S6 form Ga incorporation on the surface of the P-type barrier layer during the growth process.

[0090] In one embodiment, growing the p-type barrier back layer includes: growing a layer with a thickness of 5-10 nm and a Mg doping concentration of 2 × 10⁻⁶ under conditions of a temperature of 950-1050 °C and a pressure of 100-300 torr. 19 -2×10 20 cm -3 The back layer of the P-type barrier.

[0091] Growing a P-type barrier back layer under relatively high temperature conditions (i.e., 950-1050℃) can yield a high-quality nitride barrier back layer, shielding the extension of surface defects in the P-type barrier front layer and improving the leakage current performance of the epitaxial structure.

[0092] In another embodiment, growing a p-type semiconductor layer on the light-emitting layer further includes growing a second p-type nitride layer on the side of the first p-type nitride layer away from the light-emitting layer.

[0093] Furthermore, the growth of the second p-type nitride layer can be achieved under the following conditions: a temperature of 950-1050℃, a pressure of 200-600 torr, a growth thickness of 50-150 nm, and a Mg doping concentration of 1×10⁻⁶. 19 -1×10 20 cm -3 The second p-type nitride layer.

[0094] The present invention also provides a semiconductor device comprising the above-described semiconductor epitaxial structure.

[0095] Example 1 Example 1 provides a semiconductor epitaxial structure, including a substrate, an n-type GaN layer, a light-emitting layer and a p-type semiconductor layer disposed sequentially, wherein the p-type semiconductor layer includes a first p-type nitride layer and a second nitride layer disposed in a direction away from the light-emitting layer; the first nitride layer includes two p-type AlGaN barrier layers, and the second nitride layer is a p-type GaN layer.

[0096] Each p-type AlGaN barrier layer includes a p-type AlGaN barrier front layer, a local structure insertion layer, and a p-type AlGaN barrier back layer arranged sequentially in the direction away from the light-emitting layer; the local structure insertion layer includes AlN microstructures and InN microstructures arranged sequentially in the direction away from the light-emitting layer.

[0097] Furthermore, the surface in contact between the p-type AlGaN barrier front layer and the p-type AlGaN barrier back layer has a first groove, and the AlN microstructure 403 is disposed in the first groove; the surface in contact between the p-type barrier back layer and the p-type barrier front layer has a second groove corresponding to the first groove, and the InN microstructure is disposed in the second groove.

[0098] Example 1 also provides a method for preparing the above-mentioned semiconductor epitaxial structure, specifically including the following steps: (1) Provide a 4-inch sapphire substrate as a support for subsequent film growth; place the sapphire substrate in the growth chamber of a metal-organic chemical vapor deposition (MOCVD) system.

[0099] (2) Under the conditions of temperature of 1150℃ and pressure of 200 torr, a growth thickness of 2μm and a Si doping concentration of 5×10⁻⁶ were achieved. 18 cm -3 An n-type semiconductor layer made of GaN (denoted as an n-type GaN layer).

[0100] (3) Growing a light-emitting layer on an n-type GaN layer, including the following steps: S31: A quantum well layer (denoted as InGaN quantum well layer) with a thickness of 2nm is grown on an n-type GaN layer under the conditions of 750℃ and 200 torr.

[0101] S32: Raise the temperature to 800℃ and grow a quantum barrier layer (denoted as GaN quantum barrier layer) with GaN material and a thickness of 8nm on the InGaN quantum well layer.

[0102] S33: Repeat S31-S32 8 times to form a light-emitting layer with 8 cycles.

[0103] (4) Growing a p-type barrier front layer of AlGaN on the light-emitting layer (denoted as p-type AlGaN barrier front layer), including the following steps: S41: Under conditions of 750℃ and 400 torr, TMIn is introduced at a flow rate of 300 sccm, and a thickness of 3 nm and a Mg doping concentration of 8 × 10⁻⁶ are grown under the action of TMIn. 19 cm -3 The first stronghold of the front layer.

[0104] S42: Increase the flow rate of TMIn to 1500 sccm, grow a thickness of 3 nm, and set the Mg doping concentration to 8 × 10⁻⁶. 19 cm -3 The second barrier layer is used to obtain the p-type AIGaN barrier layer.

[0105] (5) Under the conditions of 800℃ and 200 torr, TMAI with a flow rate of 300 sccm was introduced into the N2 atmosphere to perform Al thermal surface treatment for 100s, so as to form an Al deposition layer on the front layer of p-type AlGaN barrier.

[0106] (6) Under the conditions of 800℃ and 200 torr, TMG with a flow rate of 500 sccm was introduced into the N2 atmosphere to perform Ga thermal surface treatment for 100s in order to form a Ga deposition layer on the Al deposition layer.

[0107] (7) Under the conditions of 850℃ and 200 torr, the first heat annealing treatment was carried out in N2 atmosphere for 60s.

[0108] During the first thermal annealing process, In in the p-type AlGaN barrier front layer diffuses to the surface of the p-type AlGaN barrier front layer to form InN microstructures, and under the protection of the Ga deposition layer, Al in the Al deposition layer diffuses to the interior of the p-type AlGaN barrier front layer to form AlN microstructures.

[0109] (8) Under the conditions of 900℃ and 200 torr, N hot surface treatment was performed in H2 atmosphere for 100s, and the Ga deposited layer was nitrided into GaN layer.

[0110] (9) Under the conditions of 980℃ and 400 torr, a second heat annealing treatment was carried out in H2 atmosphere for 60s.

[0111] During the second thermal annealing process, the GaN layer is fully etched and completely decomposed, forming Ga dangling bonds.

[0112] (10) Under the conditions of a temperature of 980℃ and a pressure of 200 torr, a growth thickness of 6 nm and a Mg doping concentration of 8 × 10⁻⁶ were achieved. 19 cm -3 The p-type AIGaN barrier layer is formed by the back layer of the p-type AIGaN barrier layer.

[0113] During the growth of the p-type AlGaN barrier back layer, the Ga dangling bonds formed in step (9) form Ga incorporation on the surface of the p-type AlGaN barrier back layer.

[0114] (11) Repeat steps (4)-(10) twice to form a first p-type nitride layer consisting of two p-type AIGaN barrier layers.

[0115] During the periodic repetition process, InN and AlN microstructures with different depths are formed in the thickness direction, thereby increasing the hole concentration in the longitudinal direction, reducing the resistance of the front layer of the p-type nitride barrier, and enhancing the transport of holes in the longitudinal direction.

[0116] (12) Under the conditions of a temperature of 980℃ and a pressure of 400 torr, a growth thickness of 100 nm and a Mg doping concentration of 5 × 10⁻⁶ were achieved. 19 cm -3 The material is the second nitride layer of GaN (denoted as p-type GaN layer), thus forming a semiconductor epitaxial structure.

[0117] Example 2 Example 2 provides a semiconductor epitaxial structure, such as Figure 2As shown, the only difference between the semiconductor epitaxial structure of Example 2 and Example 1 is that the first p-type nitride layer in the semiconductor epitaxial structure of Example 2 is composed of three p-type AlGaN barrier layers. The rest is the same as in Example 1, and will not be described again here.

[0118] The difference between the semiconductor epitaxial structure preparation method in Example 2 and that in Example 1 is that steps (4) to (10) are repeated three times.

[0119] Example 3 Example 3 provides a method for preparing a semiconductor epitaxial structure, specifically including the following steps: (1) Provide a 4-inch sapphire substrate as a support for subsequent film growth; place the sapphire substrate in the growth chamber of the MOCVD system.

[0120] (2) Under the conditions of a temperature of 1050℃ and a pressure of 100 torr, a growth thickness of 1μm and a Si doping concentration of 1×10⁻⁶ were achieved. 18 cm -3 An n-type semiconductor layer made of GaN (denoted as an n-type GaN layer).

[0121] (3) Growing a light-emitting layer on an n-type GaN layer, including the following steps: S31: A quantum well layer (denoted as InGaN quantum well layer) with a thickness of 5 nm is grown on an n-type GaN layer under the conditions of 650℃ and 150 torr.

[0122] S32: Raise the temperature to 700℃ to grow a quantum barrier layer (denoted as GaN quantum barrier layer) with GaN material and a thickness of 25nm on the InGaN quantum well layer.

[0123] S33: Repeat S31-S32 twice to form a light-emitting layer with two cycles.

[0124] (4) Growing a p-type barrier front layer of AlGaN on the light-emitting layer (denoted as p-type AlGaN barrier front layer), including the following steps: S41: Under conditions of 700℃ and 300 torr, TMIn is introduced at a flow rate of 100 sccm, and a thickness of 2 nm and a Mg doping concentration of 2 × 10⁻⁶ are grown under the action of TMIn. 19 cm -3 The first stronghold of the front layer.

[0125] S42: Increase the TMIn flow rate to 1000 sccm, grow a thickness of 2 nm, and set the Mg doping concentration to 2 × 10⁻⁶. 19 cm -3The second barrier layer is used to obtain the p-type AIGaN barrier layer.

[0126] (5) Under the conditions of 750℃ and 100 torr, TMAI with a flow rate of 100 sccm was introduced in N2 atmosphere to perform Al thermal surface treatment for 20s, so as to form an Al deposition layer on the front layer of p-type AlGaN barrier.

[0127] (6) Under the conditions of 750℃ and 100 torr, in a N2 atmosphere, TMG with a flow rate of 200 sccm is introduced to perform Ga thermal surface treatment for 10s to form a Ga deposition layer on the Al deposition layer.

[0128] (7) Under the conditions of 800℃ and 100 torr, the first heat annealing treatment was carried out in N2 atmosphere for 20s.

[0129] During the first thermal annealing process, In, which is locally distributed in the p-type AlGaN barrier front layer, diffuses to the surface of the front layer to form a locally distributed InN microstructure. Under the protection of the Ga deposition layer, Al in the Al deposition layer diffuses into the interior of the p-type AlGaN barrier front layer to form a locally distributed AlN microstructure.

[0130] (8) Under the conditions of 850℃ and 100 torr, the Ga deposited layer was nitrided into a GaN layer by N hot surface treatment in H2 atmosphere for 40s.

[0131] (9) Under the conditions of 950℃ and 300 torr, a second heat annealing treatment was carried out in H2 atmosphere for 30s.

[0132] During the second thermal annealing process, the GaN layer is fully etched and decomposed to form Ga dangling bonds.

[0133] (10) Under the conditions of a temperature of 950℃ and a pressure of 100 torr, a growth thickness of 5 nm and a Mg doping concentration of 2×10⁻⁶ were achieved. 19 cm -3 The p-type AIGaN barrier layer is formed by the back layer of the p-type AIGaN barrier layer.

[0134] During the growth of the p-type AlGaN barrier back layer, the Ga dangling bonds formed in step (9) form Ga incorporation on the surface of the p-type AlGaN barrier back layer.

[0135] (11) Repeat steps (4) to (10) a total of 8 times to form the first p-type nitride layer consisting of 8 p-type AIGaN barrier layers.

[0136] During the periodic repetition process, InN and AlN microstructures with different depths are formed in the thickness direction, thereby increasing the hole concentration in the longitudinal direction, reducing the resistance of the front layer of the p-type nitride barrier, and enhancing the transport of holes in the longitudinal direction.

[0137] (12) Under the conditions of 950℃ and 200 torr, a growth thickness of 50 nm and a Mg doping concentration of 1×10⁻⁶ were achieved. 19 cm -3 A second p-type nitride layer made of GaN, denoted as (p-type GaN layer), is formed to create a semiconductor epitaxial structure.

[0138] Example 4 The semiconductor epitaxial structure provided in Example 4 is basically the same as that in Example 1, and its preparation method specifically includes the following steps: (1) Provide a 4-inch sapphire substrate as a support for subsequent film growth, and place the sapphire substrate in the growth chamber of the MOCVD system.

[0139] (2) Under the conditions of a temperature of 1250℃ and a pressure of 300 torr, a growth thickness of 5μm and a Si doping concentration of 1×10⁻⁶ were achieved. 19 cm -3 An n-type semiconductor layer made of GaN (denoted as an n-type GaN layer).

[0140] (3) Growing a light-emitting layer on an n-type GaN layer, including the following steps: S31: A quantum well layer of InGaN material with a thickness of 1 nm is grown on an n-type GaN layer under the conditions of temperature of 850℃ and pressure of 350 torr (denoted as InGaN quantum well layer).

[0141] S32: Raise the temperature to 950℃ to grow a GaN quantum barrier layer (denoted as GaN quantum barrier layer) with a thickness of 6nm on the InGaN quantum well layer.

[0142] S33: Repeat S31-S32 15 times to form a light-emitting layer with 15 cycles.

[0143] (4) Growing a p-type barrier front layer of AlGaN on the light-emitting layer (denoted as p-type AlGaN barrier front layer), including the following steps: S41: Under conditions of 800℃ and 600 torr, TMIn is introduced at a flow rate of 500 sccm, and a thickness of 5 nm and a Mg doping concentration of 2 × 10⁻⁶ are grown under the action of TMIn. 20 cm -3 The first stronghold of the front layer.

[0144] S42: Increase the flow rate of TMIn to 2000 sccm, grow a thickness of 5 nm, and set the Mg doping concentration to 2 × 10⁻⁶. 20 cm -3 The second barrier layer is used to obtain the p-type AIGaN barrier layer.

[0145] (5) Under the conditions of 850℃ and 300 torr, TMAI with a flow rate of 500 sccm was introduced into the N2 atmosphere to perform Al thermal surface treatment for 180s, so as to form an Al deposition layer on the front layer of p-type AlGaN barrier.

[0146] (6) Under the conditions of 850℃ and 300 torr, TMG with a flow rate of 800 sccm was introduced into the N2 atmosphere to perform Ga thermal surface treatment for 120s in order to form a Ga deposition layer on the Al deposition layer.

[0147] (7) Under the conditions of 900℃ and 300 torr, the first heat annealing treatment was carried out in N2 atmosphere for 100s.

[0148] During the first thermal annealing process, In in the p-type AlGaN barrier front layer diffuses to the surface of the p-type AlGaN barrier front layer to form InN microstructures, and under the protection of the Ga deposition layer, Al in the Al deposition layer diffuses to the interior of the p-type AlGaN barrier front layer to form AlN microstructures.

[0149] (8) Under the conditions of 950℃ and 300 torr, the Ga deposited layer was nitrided into a GaN layer by N hot surface treatment in H2 for 300s.

[0150] (9) Under the conditions of 1050℃ and 600 torr, a second heat annealing treatment was carried out in H2 for 90s.

[0151] During the second thermal annealing process, the GaN layer is fully etched and decomposed to form Ga dangling bonds.

[0152] (10) Under the conditions of a temperature of 1050℃ and a pressure of 300 torr, a growth thickness of 10 nm and a Mg doping concentration of 2×10⁻⁶ were achieved. 20 cm -3 The p-type AIGaN barrier layer is formed by the back layer of the p-type AIGaN barrier layer.

[0153] During the growth of the p-type AlGaN barrier back layer, the Ga dangling bonds formed in step (9) form Ga incorporation on the surface of the p-type AlGaN barrier back layer.

[0154] (11) Repeat steps (4)-(10) twice to form a first p-type nitride layer with two p-type AIGaN barrier layers.

[0155] During the periodic repetition process, InN and AlN microstructures with different depths are formed in the thickness direction, thereby increasing the hole concentration in the longitudinal direction, reducing the resistance of the front layer of the p-type nitride barrier, and enhancing the transport of holes in the longitudinal direction.

[0156] (11) Under the conditions of 1050℃ and 600 torr, a growth thickness of 150 nm and a Mg doping concentration of 1×10⁻⁶ were achieved. 20 cm -3 A second p-type nitride layer (denoted as p-type GaN layer) made of GaN is formed, thereby creating a semiconductor epitaxial structure.

[0157] Example 5 Example 5 provides a semiconductor epitaxial structure, differing from Example 1 only in that the molar concentration of Al in the p-type AlGaN barrier front layer of Example 5 exhibits a gradient distribution characteristic. Specifically, the p-type AlGaN barrier front layer has opposing first and second surfaces, with the second surface closer to the p-type AlGaN barrier back layer. Furthermore, the molar concentration of Al in the p-type AlGaN barrier front layer decreases along the direction from the first surface to the second surface, while the molar concentration of Al in the p-type AlGaN back layer is uniformly distributed. The molar proportion of Al in the p-type AlGaN on the first surface is 0.5, and the molar proportion of Al in the p-type AlGaN on the second surface is 0.1. The rest is the same as the epitaxial structure in Example 1, and will not be repeated here.

[0158] The method for preparing the semiconductor epitaxial structure in Example 5 is basically the same as that in Example 1, except that during the growth of the p-type AlGaN barrier layer, the flow rate of the TMAl source is controlled to decrease from 120 sccm to 20 sccm, so that the molar ratio of Al in the AlGaN in the p-type AlGaN barrier layer decreases.

[0159] Example 6 The semiconductor epitaxial structure and its preparation method provided in Example 6 are basically the same as those in Example 1, except that in step (4) of Example 6, TMI is introduced at a constant flow rate. Step (4) is as follows: Under conditions of 750℃ and 400 torr, TMIn was introduced at a flow rate of 1500 sccm to grow a thickness of 6 nm with a Mg doping concentration of 8 × 10⁻⁶. 19 cm -3 p-type AIGaN barrier front layer.

[0160] The remaining steps are the same as in Example 1, and will not be repeated here.

[0161] Comparing Examples 1 and 6, it was found that although Example 6 was able to form AlN and InN microstructures, directly introducing TMIn at a high flow rate would cause lattice distortion in the front layer of the p-type AlGaN barrier, resulting in uneven component distribution, which is not conducive to the formation of uniformly distributed local diffusion centers.

[0162] Example 7 The semiconductor epitaxial structure and its preparation method provided in Example 7 are basically the same as those in Example 1, except that in step (4) of Example 7, TMI is introduced at a constant flow rate. Step (4) is as follows: Under conditions of 750℃ and 400 torr, TMIn was introduced at a flow rate of 300 sccm to grow a thickness of 6 nm with a Mg doping concentration of 8 × 10⁻⁶. 19 cm -3 p-type AIGaN barrier front layer.

[0163] The remaining steps are the same as in Example 1, and will not be repeated here.

[0164] Comparing Examples 1 and 7, it was found that although Example 7 was able to form AlN and InN microstructures, the constant low flow rate of TMIn was not conducive to the formation of uniformly distributed local diffusion centers in the front layer of the p-type AlGaN barrier.

[0165] Comparative Example 1 Comparative Example 1 provides a semiconductor epitaxial structure without AlN and InN microstructures. Its fabrication method involves growing a p-type AlGaN barrier layer using conventional methods, as detailed below: Under conditions of 750℃ and 400 torr, a Mg doping concentration of 8×10⁻⁶ was grown. 19 cm -3 The material is a p-type AlGaN barrier layer, and the thickness of the p-type AlGaN barrier layer is the same as the total thickness of the first p-type nitride layer in Example 1.

[0166] The remaining steps are the same as in Example 1, and will not be repeated here.

[0167] Comparative Example 2 The only difference between Comparative Example 2 and Example 1 is that no Ga deposition layer is formed during the preparation process, i.e., step 6 in Example 1 is not performed. The rest is the same as in Example 1, and will not be repeated here.

[0168] Without a Ga deposition layer, the Al deposition layer lacks Ga protection. During the first thermal annealing process, the migration activity of Al atoms is poor. After the first thermal annealing process, the Al deposition layer tends to form an aggregated microsphere structure of Al metal atoms, making it difficult to diffuse and form an AlN microstructure.

[0169] Comparative Example 3 The preparation methods of Comparative Example 3 and Example 1 are basically the same. The only difference is that in step (7) of Comparative Example 3, the temperature of the first heat annealing treatment is 780°C. The rest are the same as in Example 1, and will not be repeated here.

[0170] It was found that when the temperature of the first thermal annealing treatment is too low, the precipitation ability of In atoms in the front layer of the p-type AlGaN barrier is reduced, thus making it impossible to form a uniformly distributed diffusion, which is not conducive to the formation of diffusion microstructures.

[0171] Comparative Example 4 The preparation methods of Comparative Example 4 and Example 1 are basically the same. The only difference is that in step (7) of Comparative Example 4, the temperature of the first heat annealing treatment is 920°C. The rest are the same as those of Example 1, and will not be repeated here.

[0172] It was found that when the temperature of the first annealing treatment is too high, it will cause the Al deposited layer to diffuse to the surface of the Ga deposited layer, which is not conducive to the formation of diffused microstructures.

[0173] The semiconductor epitaxial structures from the above embodiments and comparative examples were fabricated into chips using the same process and tested. LED optoelectronic performance testers were used to test them, including luminous intensity (Lop / mW) and voltage (VF / V) under 2mA current injection, luminous intensity decay (droop / %) under 1000mA current injection, and ESD yield and leakage current (IR) performance under reverse breakdown voltage of 2000V and reverse voltage of 7V. The test structures are shown in Table 1.

[0174] Table 1. Relevant performance of chips obtained from the epitaxial structures in the embodiments and comparative examples of this invention. Example 1 2.84 13.7 99.8 99.9 35.1 Example 2 2.85 14.5 99.9 99.9 35.4 Example 3 2.84 15.9 99.8 99.8 35.5 Example 4 2.85 13.9 98.7 99.2 35.4 Example 5 2.84 15.3 100 99.7 32.3 Example 6 2.88 11.8 92.5 91.2 40.2 Example 7 2.91 12.2 93.1 92.6 39.6 Comparative Example 1 2.93 10.1 93.1 94.6 42.2 Comparative Example 2 2.82 10.4 94.1 93.6 41.5 Comparative Example 3 2.89 11.2 92.1 94.6 40.6 Comparative Example 4 2.92 10.7 93.1 92.6 39.6 As shown in the table above, Examples 1-5 exhibit lower voltage, higher brightness, higher ESD and IR yield performance, and lower droop performance. This indicates that the epitaxial structure of the present invention has a higher concentration of hole injection, which can balance the electron and hole injection balance of the n-type semiconductor layer and the p-type semiconductor layer, improve the brightness of the semiconductor epitaxial structure, reduce the operating voltage, and reduce the droop effect that occurs in the epitaxial structure with increasing injection current. Compared with Example 1, Example 5 has lower voltage, higher brightness, and lower droop performance. This is because Example 5 obtains excellent carrier injection performance by decreasing the Al composition, thereby improving the uniformity of carrier distribution in the light-emitting layer.

[0175] All aspects, embodiments, features, and examples of this invention are to be regarded as illustrative in all respects and are not intended to limit the invention, the scope of which is defined only by the claims. Other embodiments, modifications, and uses will become apparent to those skilled in the art without departing from the spirit and scope of the invention as claimed.

[0176] In addition, the inventors of this case also conducted experiments with other raw materials, process operations, and process conditions described in this specification, referring to the aforementioned embodiments, and obtained relatively ideal results in all cases.

[0177] Although the invention has been described with reference to illustrative embodiments, those skilled in the art will understand that various other changes, omissions, and / or additions can be made without departing from the spirit and scope of the invention, and that elements of the embodiments can be substituted with substantially equivalents. Furthermore, many modifications can be made without departing from the scope of the invention to adapt particular situations or materials to the teachings of the invention. Therefore, this invention is not intended to be limited to the specific embodiments disclosed for carrying out the invention, but rather is intended to encompass all embodiments falling within the scope of the appended claims. Moreover, unless specifically stated otherwise, any use of the terms first, second, etc., does not indicate any order or importance, but is used to distinguish one element from another.

Claims

1. A semiconductor epitaxial structure, comprising a substrate, an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer sequentially disposed therefrom, wherein the p-type semiconductor layer includes a first p-type nitride layer, characterized in that, The first p-type nitride layer includes at least one p-type barrier layer disposed in a direction away from the light-emitting layer. The p-type barrier layer includes a p-type barrier front layer, a localized structure insertion layer, and a p-type barrier back layer disposed sequentially in a direction away from the light-emitting layer. The localized structure insertion layer includes a first microstructure and a second microstructure disposed sequentially in a direction away from the light-emitting layer. The first microstructure includes an AlN microstructure, and the second microstructure includes an InN microstructure. The AlN microstructure and the InN microstructure have a band gap difference. The surface of the p-type barrier front layer in contact with the p-type barrier back layer has a first groove, in which the first microstructure is disposed. The surface of the p-type barrier back layer in contact with the p-type barrier front layer has a second groove corresponding to the first groove, in which the second microstructure is disposed.

2. The semiconductor epitaxial structure according to claim 1, characterized in that, The front layer of the P-type barrier is a p-type Al-nitride-containing front layer, and the back layer of the P-type barrier is a p-type Al-nitride-containing back layer.

3. The semiconductor epitaxial structure according to claim 2, characterized in that, The p-type Al-containing nitride front layer has a first surface and a second surface opposite to each other, the second surface being close to the p-type Al-containing nitride back layer; the molar concentration of Al in the p-type Al-containing nitride front layer decreases along the direction from the first surface to the second surface, and the molar concentration of Al in the p-type Al-containing nitride back layer is uniformly distributed.

4. The semiconductor epitaxial structure according to claim 1, characterized in that, The in-plane local size of the first and second microstructures is 200-1000 nm.

5. The semiconductor epitaxial structure according to claim 1, characterized in that, The p-type semiconductor layer further includes a second p-type nitride layer disposed on the side of the first p-type nitride layer away from the light-emitting layer.

6. A method for preparing a semiconductor epitaxial structure, characterized in that, include: An n-type semiconductor layer and a light-emitting layer are sequentially grown on a substrate; A p-type semiconductor layer is grown on the light-emitting layer; The p-type semiconductor layer includes a first p-type nitride layer, which includes at least one p-type barrier layer disposed along a direction away from the light-emitting layer. The p-type barrier layer includes a p-type barrier front layer, a localized structure insertion layer, and a p-type barrier back layer disposed sequentially along a direction away from the light-emitting layer. The localized structure insertion layer includes a first microstructure and a second microstructure disposed sequentially along a direction away from the light-emitting layer. The first microstructure includes an AlN microstructure, and the second microstructure includes an InN microstructure. The AlN microstructure and the InN microstructure have a bandgap difference. The surface of the p-type barrier front layer that contacts the p-type barrier back layer has a first groove, in which the first microstructure is disposed. The surface of the p-type barrier back layer that contacts the p-type barrier front layer has a second groove corresponding to the first groove, in which the second microstructure is disposed.

7. The preparation method according to claim 6, characterized in that, The growth of the p-type semiconductor layer on the light-emitting layer includes: S1. Under the condition of introducing an In source active agent, a P-type barrier front layer is grown on the light-emitting layer; S2. Under inert atmosphere conditions, an Al deposition layer is formed on the front layer of the P-type barrier; S3. Under inert atmosphere conditions, a Ga deposition layer is formed on the Al deposition layer; S4. Under inert atmosphere conditions, the structure obtained in step S3 is subjected to a first thermal annealing treatment to allow In in the front layer of the P-type barrier to diffuse to the surface of the front layer of the P-type barrier and the Al deposition layer to form the second microstructure, and to allow Al in the Al deposition layer to diffuse to the interior of the front layer of the P-type barrier to form the first microstructure. S5. Under reducing atmosphere conditions, a nitrogen source is introduced to perform N thermal surface treatment on the structure obtained in S4, so that the Ga deposited layer becomes a GaN layer. S6. Under reducing atmosphere conditions, the structure obtained in S5 is subjected to a second thermal annealing treatment to decompose the GaN layer into Ga dangling bonds. S7. Grow a Ga-containing P-type barrier back layer on the structure obtained in S6, thereby forming the P-type barrier layer.

8. The preparation method according to claim 7, characterized in that, The P-type barrier front layer includes a first barrier sub-layer and a second barrier sub-layer. Step S1 specifically includes: S11. The In source active agent is introduced at a first flow rate to grow the first barrier front layer on the light-emitting layer; S12. The In source active agent is introduced at a second flow rate to grow the second barrier front layer on the first barrier front layer, thereby forming the P-type barrier front layer. Wherein, the first flow rate is less than the second flow rate.

9. The preparation method according to claim 8, characterized in that, The ratio of the first flow rate to the second flow rate is less than 1:

3.

10. The preparation method according to claim 8, characterized in that, The first flow rate is 100-500 sccm, and the second flow rate is 1000-2000 sccm.

11. The preparation method according to claim 7, characterized in that, The growth of the P-type barrier front layer includes: introducing an In-source activator at a temperature of 700-800℃ and a pressure of 300-600 torr to grow a thickness of 10-20 nm and a Mg doping concentration of 2×10⁻⁶. 19 -2×10 20 cm -3 The front layer of the P-type barrier.

12. The preparation method according to claim 7, characterized in that, The deposition of the Al deposit layer includes: introducing an Al source for Al thermal surface treatment for 20-180 seconds under conditions of temperature of 750-850℃, pressure of 100-300 torr and inert atmosphere.

13. The preparation method according to claim 7, characterized in that, The deposition of the Ga deposit layer includes: introducing a Ga source for Ga thermal surface treatment for 10-120 seconds under conditions of temperature of 750-850℃, pressure of 100-300 torr and inert atmosphere.

14. The preparation method according to claim 7, characterized in that, The temperature of the first heat annealing treatment is 800-900℃, the pressure is 100-300 torr, and the time is 20-100s.

15. The preparation method according to claim 7, characterized in that, The N-thermal surface treatment is performed at a temperature of 850-950℃, a pressure of 100-300 torr, and a time of 40-300s.

16. The preparation method according to claim 7, characterized in that, The second heat annealing treatment is performed at a temperature of 950-1050℃, a pressure of 300-600 torr, and a time of 30-90s.

17. The preparation method according to claim 7, characterized in that, The growth of the p-type barrier back layer includes: growing a thickness of 5-10 nm and a Mg doping concentration of 2 × 10⁻⁶ under conditions of temperature 950-1050℃ and pressure 100-300 torr. 19 -2×10 20 cm -3 The back layer of the P-type barrier.

18. The preparation method according to claim 7, characterized in that, Steps S1 to S7 are repeated multiple times.

19. The preparation method according to claim 6, characterized in that, The growth of the n-type semiconductor layer includes: growing a thickness of 1-5 μm and a Si doping concentration of 1×10⁻⁶ under conditions of a temperature of 1050-1250℃ and a pressure of 100-300 torr. 18 -1×10 19 cm -3 n-type semiconductor layer.

20. The preparation method according to claim 6, characterized in that, The light-emitting layer includes a plurality of light-emitting units arranged sequentially along a direction away from the n-type semiconductor layer. The growth of the light-emitting units includes: growing a quantum well layer with a thickness of 1-5 nm under conditions of temperature of 650-850℃ and pressure of 150-350 torr; and growing a quantum barrier layer with a thickness of 6-25 nm on the quantum well layer under conditions of temperature of 700-950℃ and pressure of 150-350 torr.

21. The preparation method according to claim 6, characterized in that, The preparation method further includes growing a second p-type nitride layer on the side of the first p-type nitride layer away from the light-emitting layer.

22. The preparation method according to claim 21, characterized in that, The growth of the second p-type nitride layer includes: growing a thickness of 50-150 nm and a Mg doping concentration of 1×10⁻⁶ under conditions of temperature 950-1050℃, pressure 200-600 torr. 19 -1×10 20 cm -3 The second p-type nitride layer.

23. A semiconductor epitaxial structure, characterized in that: It is prepared by the method described in any one of claims 6-22.

24. A semiconductor device, characterized in that, Includes the semiconductor epitaxial structure as described in any one of claims 1-5 and 23.

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