Chip manufacturing method and chip

Abstract

The application discloses a chip preparation method and a chip. The chip preparation method comprises the following steps: sequentially forming a first conductor layer and a first insulating layer on a semiconductor layer; forming a bridge pier structure on the first insulating layer; forming a sacrificial layer between the bridge pier structures; sequentially forming a third insulating layer and a bridge structure on the bridge pier structure; and removing the sacrificial layer to form an air bridge structure; wherein the sacrificial layer is a BARC layer or an amorphous carbon layer. The chip preparation method of the embodiment adopts the BARC layer or the amorphous carbon layer as the sacrificial layer, and the BARC layer or the amorphous carbon layer does not affect the structure of the chip structure in the removal process, prevents over-etching of the chip structure, and effectively removes the noise interference source.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for fabricating a chip and the chip itself. Background Technology

[0002] An air bridge is a three-dimensional bridge structure named for the air or vacuum medium between it and the circuit. Air bridges are used to bridge planar circuits.

[0003] In traditional processes, an insulating dielectric layer (such as a SiO2 layer) is used as the isolation medium for air bridges, and this isolation medium is removed in the final structure to form the air bridge. However, the removal of the isolation medium can lead to over-etching, which can damage the circuit structure. If the isolation medium is not removed, it becomes a significant source of noise, introducing interference factors for subsequent circuit testing and verification. Summary of the Invention

[0004] In view of the above problems, the purpose of this application is to provide a chip fabrication method and chip, which uses a BARC layer or an amorphous carbon layer as a sacrificial layer to prevent over-etching of the chip and effectively remove noise interference sources.

[0005] According to one aspect of the present invention, a method for fabricating a chip is provided, comprising: sequentially forming a first conductor layer and a first insulating layer on a semiconductor layer; forming a pier structure on the first insulating layer; forming a sacrificial layer between the pier structures; sequentially forming a third insulating layer and a bridge structure on the pier structures; and removing the sacrificial layer to form an air bridge structure; wherein the sacrificial layer is a BARC layer or an amorphous carbon layer.

[0006] Optionally, the sacrificial layer is a BARC layer, and the method for removing the sacrificial layer includes: ashing the sacrificial layer and removing the residue of the sacrificial layer by wet etching.

[0007] Optionally, the sacrificial layer is an amorphous carbon layer, and the method for removing the sacrificial layer includes: oxidizing the amorphous carbon layer to form carbon dioxide, thereby eliminating the amorphous carbon.

[0008] Optionally, the method of forming the pier structure includes: forming a patterned resist mask layer having an inverted trapezoidal opening; forming a second conductor layer including a first portion covering the resist mask layer and a second portion filling the opening; removing the first portion of the second conductor layer; and removing the resist mask layer, leaving the second portion of the second conductor layer to form the pier structure; wherein the second conductor layer is formed using a vapor deposition process.

[0009] Optionally, a brush can be used to remove the first portion of the second conductor layer.

[0010] Optionally, before forming the first conductor layer, the method further includes forming a protective layer on the semiconductor layer, wherein the first conductor layer is located on the protective layer.

[0011] Optionally, before forming the first insulating layer, the step of removing the natural oxide layer on the surface of the first conductor layer is included.

[0012] Optionally, the step of forming a sacrificial layer between the pier structures includes: forming a sacrificial layer covering the surface of the pier structures and located between the pier structures; removing the sacrificial layer covering the surface of the pier structures, while retaining the sacrificial layer located between the pier structures, with the top of the remaining sacrificial layer flush with the top of the pier structures.

[0013] Optionally, the third insulating layer covers the top of the pier structure and the top of the sacrificial layer.

[0014] According to another aspect of the present invention, a chip formed by the above-described preparation method is provided, wherein a first conductor layer, a first insulating layer, and a bridge structure form a first chip structure, and a bridge structure, a third insulating layer, and a bridge structure form a second chip structure.

[0015] The unexpected technical effect of this application is: The chip fabrication method in this embodiment uses a BARC layer or an amorphous carbon layer as a sacrificial layer. The removal of the BARC layer or the amorphous carbon layer will not affect the structure of the chip, preventing over-etching of the chip structure and effectively removing noise interference sources.

[0016] In a preferred embodiment, the sacrificial layer is a BARC layer. Most of the BARC layer is removed by ashing, and the residue of the sacrificial layer is removed by wet etching. Since the wet etching time is short, it does not affect the semiconductor layer or the chip structure (e.g., the first conductor layer on the sidewalls of the sacrificial layer, the pier structure 106a, and the bridge structure 110a on top of the sacrificial layer). Furthermore, a protective layer covers the semiconductor layer, and the exposed protective layer is covered by a first insulating layer, thus protecting the semiconductor layer. Similarly, the sidewalls of the first conductor layer are covered by a first insulating layer 105, the sidewalls of the pier structure 106a are covered by a second insulating layer 107, and the lower part of the bridge structure 110a is covered by a third insulating layer 109. The first insulating layer 105, the second insulating layer 107, and the third insulating layer 109 respectively protect the first conductor layer 103, the pier structure 106a, and the bridge structure 110a.

[0017] In a preferred embodiment, the sacrificial layer is amorphous carbon. The sacrificial layer is removed by oxidizing the amorphous carbon without affecting the semiconductor layer and the chip structure (e.g., the first conductor layer on the sidewall of the sacrificial layer, the pier structure 106a, and the bridge structure 110a on top of the sacrificial layer).

[0018] In a preferred embodiment, during the formation of the bridge pier, a resist mask layer with an inverted trapezoidal opening is first formed. The inverted trapezoidal opening prevents the second conductor layer falling into it from contacting the sidewall of the inverted trapezoidal opening, so that the second conductor layer falling into the inverted trapezoidal opening will not be affected during the subsequent removal of the resist mask layer.

[0019] In a preferred embodiment, a brush is used to remove the second conductor layer covering the resist mask layer to prevent the collapse of the second conductor layer from affecting the second conductor layer falling into the inverted trapezoidal opening.

[0020] In a preferred embodiment, a vapor deposition process is used to form the second semiconductor layer to prevent damage to the second resist mask layer PR2 during the deposition process to form the second conductor layer 106, thereby preventing defects from forming on the surface of the second resist mask layer PR2.

[0021] In a preferred embodiment, before forming the first insulating layer, the natural oxide layer formed by oxidation on the surface of the first conductor layer 103 is removed. Compared with the metal oxide layer formed by natural oxidation, the first insulating layer 105 formed by deposition process has better density to ensure the quality of the first insulating layer 105, thereby ensuring that it will not affect the reliability and quality of the subsequent chip structure formation.

[0022] In a preferred embodiment, the third insulating layer 109 covers the top of the pier structure 106a and the top of the sacrificial layer 108. The third insulating layer 109 above the pier structure 106a is used for the subsequent formation of the second chip structure, while the third insulating layer 109 on top of the sacrificial layer 108 protects the sacrificial layer 108 and supports the subsequently formed third conductor layer 110, preventing defects, dents, collapses, or other adverse effects from forming on the top of the sacrificial layer 108 due to its relatively soft texture during the formation of the third conductor layer 110. Attached Figure Description

[0023] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which: Figure 1 A flowchart illustrating a chip manufacturing method provided in an embodiment of this application is shown; Figures 2a to 2m Cross-sectional views of various stages in the manufacturing process of the semiconductor device according to an embodiment of this application are shown, wherein: Figure 2a A schematic diagram showing a protective layer and a first conductor layer sequentially formed on the surface of a semiconductor layer is shown. Figure 2b A schematic diagram showing the formation of a hard mask layer and a first resist mask layer on the surface of a first conductor layer is shown; Figure 2c A schematic diagram of the patterned first conductor layer is shown; Figure 2d A schematic diagram of the formation of the first insulating layer is shown; Figure 2e A schematic diagram showing the formation of a patterned second resist mask layer is shown; Figure 2f A schematic diagram of the formation of the second conductor layer is shown; Figure 2g A schematic diagram of the bridge pier structure is shown; Figure 2h A schematic diagram showing the formation of a sacrificial layer between the bridge pier structures is shown; Figure 2i A schematic diagram showing the removal of the sacrificial layer at the top of the bridge pier structure is shown; Figure 2j A schematic diagram of the formation of the third insulating layer is shown; Figure 2k A schematic diagram of the formation of the third conductor layer is shown; Figure 2l A schematic diagram of etching the third conductor layer to form a bridge structure is shown; Figure 2m A schematic diagram showing the formation of an air bridge structure by removing the sacrificial layer is shown; Explanation of reference numerals in the attached figures: 101-Semiconductor layer; 102-Protective layer; 103-First conductor layer; 104-Hard mask layer; 105-First insulating layer; 106-Second conductor layer; 106a-Bridge pier structure; 107-Second insulating layer; 108-Sacrificial layer; 109-Third insulating layer; 110-Third conductor layer; 110a-Bridge structure; 111-Fourth insulating layer; PR1-First resist mask layer; PR2-Second resist mask layer; PR2a-Opening; PR3-Third resist mask layer. Detailed Implementation

[0024] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0025] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0026] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0027] This application may be presented in various forms, some of which will be described below.

[0028] Figure 1 A flowchart illustrating a chip manufacturing method according to an embodiment of this application is shown, with reference to... Figure 1 The manufacturing method includes: S110: A first conductor layer and a first insulating layer are sequentially formed on the semiconductor layer; S120: A bridge pier structure is formed on the first insulating layer; S130: A sacrificial layer is formed between the pier structures; S140: A third insulating layer and a bridge structure are sequentially formed on the pier structure; S150: Remove the sacrificial layer to form an air bridge structure; The sacrificial layer is either a BARC layer or an amorphous carbon layer.

[0029] Figures 2a to 2m Cross-sectional views of various stages in the manufacturing process of the semiconductor device according to embodiments of this application are shown below. Figure 1 as well as Figures 2a to 2m The manufacturing method of the semiconductor device according to the embodiments of this application will be described.

[0030] In step S110, a first conductor layer and a first insulating layer are sequentially formed on the semiconductor layer, see reference. Figures 2a to 2d .

[0031] Specifically, such as Figure 2a As shown, a protective layer 102 and a first conductor layer 103 are sequentially formed on the surface of the semiconductor layer 101.

[0032] In this step, a protective layer 102 is formed on the surface of the semiconductor layer 101, for example, using a deposition process or an oxidation process. Next, a first conductor layer 103 is formed on the protective layer 102, for example, using a deposition process. In one embodiment, the semiconductor layer 101 is a silicon layer, the protective layer 102 is, for example, a silicon oxide (SiO2) layer, and the first conductor layer 103 is, for example, an aluminum layer.

[0033] like Figure 2b As shown, a hard mask layer 104 and a patterned first resist mask layer PR1 are formed on the first conductor layer 103.

[0034] In this step, a hard mask layer 104 and a first resist mask layer PR1 are formed on the first conductor layer 103, and the first resist mask layer PR1 is patterned using a photolithography process. The hard mask layer 104 is, for example, a DARC layer (Dielectric Anti-Reflective Coating).

[0035] like Figure 2c As shown, the first conductor layer 103 is patterned.

[0036] In this step, the hard mask layer 104 and the first conductor layer 103 are etched via a patterned first resist mask layer PR1 to transfer the pattern of the first resist mask layer PR1 into the hard mask layer 104 and the first conductor layer 103. During the etching of the first conductor layer 103, a protective layer 102 serves as a stop layer for etching, and openings in the first conductor layer 103 expose the surface of the protective layer 102. After patterning the first conductor layer 103, the first resist mask layer PR1 and the hard mask layer 104 are removed.

[0037] like Figure 2d As shown, a first insulating layer 105 is formed.

[0038] It is worth noting that the surface of the first conductor layer 103 may be oxidized in air to form a native oxide layer. In this step, the native oxide layer formed by oxidation on the surface of the first conductor layer 103 (e.g., Al2O3 formed on the surface of the first conductor layer 103) is first removed, and then a deposition process is used to form the first insulating layer 105. Compared with the metal oxide layer formed by natural oxidation, the first insulating layer 105 formed by the deposition process has better density, ensuring the quality of the first insulating layer 105, and thus ensuring that it will not affect the reliability and quality of the subsequent chip structure formation. The first insulating layer 105 conformally covers the surface of the first conductor layer 103, the sidewalls of the openings in the first conductor layer 103, and the surface of the protective layer 102 exposed by the openings in the first conductor layer 103.

[0039] In step S120, a pier structure is formed on the first insulating layer, see reference. Figures 2e to 2g .

[0040] like Figure 2e As shown, a patterned second resist mask layer PR2 is formed.

[0041] In this step, a second resist mask layer PR2 is first formed, located above the first conductor layer 103 and filling the openings in the first conductor layer 103. Next, the second resist mask layer PR2 is patterned using photolithography to form an opening PR2a. Specifically, the second resist mask layer PR2 is developed in an inverted trapezoidal pattern to form the inverted trapezoidal opening PR2a, meaning the sidewalls of the opening PR2a are inclined, and the top dimension of the opening PR2a is smaller than its bottom dimension.

[0042] Next, the second resist mask layer PR2 is baked at high temperature to harden it, giving it sufficient hardness to support the subsequently formed second conductor layer 106.

[0043] like Figure 2f As shown, a second conductor layer 106 is formed.

[0044] In this step, for example, a vapor deposition process is used to form a second conductor layer 106. The second conductor layer 106 includes a first portion that fills the opening PR2a of the second resist mask layer PR2 and a second portion that covers the second resist mask layer PR2. Since the deposition process can damage the second resist mask layer PR2 and create defects on its surface, this embodiment uses a vapor deposition process to form the second conductor layer 106.

[0045] Furthermore, since the opening PR2a is inverted trapezoidal, a gap is formed between the first part of the second conductor layer 106 and the sidewall of the opening PR2a to prevent the first part of the second conductor layer 106 from being affected during the subsequent removal of the second resist mask layer PR2.

[0046] like Figure 2g As shown, this forms the pier structure 106a.

[0047] In this step, the second part of the second conductor layer 106 is removed, while the first part of the second conductor layer 106 is retained. The retained first part is the pier structure 106a, which is located above the first conductor layer 103 and exposes the opening of the first conductor layer 103.

[0048] Furthermore, a brush is used to remove the second portion of the second conductor layer 106. There is a height difference between the first and second portions formed in this application. Removing the second portion of the second conductor layer 106 using CMP (Chemical Mechanical Polishing) and etch-back processes would cause the second portion to collapse and collide with the top of the first portion. In this embodiment, a brush is used to remove the second portion of the second conductor layer 106 to ensure that the first portion remains unaffected.

[0049] Next, the second resist mask layer PR2 is removed, while the first portion of the opening PR2a in the second resist mask layer PR2 is retained, forming the pier structure 106a. In this embodiment, for example, an ashing process is used to remove the second resist mask layer PR2. It is worth noting that during the removal of the second resist mask layer PR2, the top and sidewalls of the pier structure 106a are oxidized to form the second insulating layer 107.

[0050] In step S130, a sacrificial layer 108 is formed between the pier structures, see reference. Figures 2h to 2i .

[0051] In this step, the formed sacrificial layer 108 covers the top and sidewalls of the pier structure 106a to secure the pier structure 106a. The sacrificial layer 108 also fills the voids between the pier structures 106a to serve as support for the subsequent formation of the bridge structure. The sacrificial layer 108 is, for example, BARC (Bottom Anti-Reflective Coating) or amorphous carbon.

[0052] like Figure 2i As shown, the sacrificial layer 108 on top of the pier structure 106a is removed to expose the top of the pier structure 106a.

[0053] In this step, the sacrificial layer 108 is etched back to remove the sacrificial layer 108 on top of the pier structure 106a. At the same time, the second insulating layer 107 on top of the pier structure 106a is also removed. The top of the remaining sacrificial layer 108 is flush with the top of the pier structure 106a.

[0054] In step S140, a third insulating layer 109 and a bridge structure 110a are sequentially formed on the pier structure 106a, as shown in references 2j to 2p. Figure 2l .

[0055] like Figure 2j As shown, a third insulating layer 109 is formed.

[0056] In this step, for example, a deposition process is used to form a third insulating layer 109, which covers the top of the pier structure 106a and the top of the sacrificial layer 108. The third insulating layer 109 above the pier structure 106a is used for the subsequent formation of the second chip structure, while the third insulating layer 109 on top of the sacrificial layer 108 protects the sacrificial layer 108 and supports the subsequently formed third conductor layer 110, preventing defects, depressions, collapses, or other adverse effects from forming on the top of the sacrificial layer 108 due to its relatively soft texture during the formation of the third conductor layer 110.

[0057] like Figure 2k As shown, a third conductor layer 110 is formed.

[0058] In this step, for example, a vapor deposition process is used to form a third conductor layer 110 on the third insulating layer 109. The vapor deposition process allows the third conductor layer 110 to be uniformly attached to the third insulating layer 109 and further reduces the damage of the third conductor layer 110 to the support surface formed by the third insulating layer 109.

[0059] like Figure 2l As shown, the third conductor layer 110 is etched to form the bridge structure 110a.

[0060] In this step, a third resist mask layer PR3 is formed on the third conductor layer 110, the third resist mask layer PR3 is patterned using a photolithography process, and the third conductor layer 110 is etched through the patterned third resist mask layer PR3 to form the bridge structure 110a. Simultaneously with the etching of the third conductor layer 110, the openings of the third resist mask layer PR3 that expose the third insulating layer 109 are also etched away.

[0061] After the bridge structure 110a is formed, the third resist mask layer PR3 is removed. During the removal of the third resist mask layer PR3, the top and sidewalls of the bridge structure 110a are oxidized to form the fourth insulating layer 111.

[0062] In step S150, the sacrificial layer 108 is removed to form an air bridge structure, such as... Figure 2m As shown.

[0063] When the sacrificial layer 108 is a BARC, it is first ashed, and then wet etching is used to remove the residue from the sacrificial layer 108, forming an air bridge structure for the dual-chip structure. When the sacrificial layer 108 is amorphous carbon, it is oxidized by passing oxygen through it. The amorphous carbon is oxidized to form carbon dioxide (CO2) to eliminate the amorphous carbon. At the same time, a fourth insulating layer 111 is formed on the exposed surface of the third conductor layer 110 in a high-concentration oxygen environment to protect the third conductor layer 110 and prevent corrosion from different external working environments due to the suspension of the third conductor layer 110. This prevents the reliability and lifespan of the dual-chip structure from being affected by the gradual damage to the third conductor layer 110.

[0064] exist Figure 2m The structure shown is a dual-chip structure, wherein the first conductor layer 103, the first insulating layer 105 and the pier structure 106a (second conductor layer 106) form the first chip structure, and the pier structure 106a (second conductor layer 106), the third insulating layer 109 and the bridge structure 110a (third conductor layer 110) form the second chip structure.

[0065] The unexpected technical effect of this application is: The chip fabrication method in this embodiment uses a BARC layer or an amorphous carbon layer as a sacrificial layer. The removal of the BARC layer or the amorphous carbon layer will not affect the structure of the chip, preventing over-etching of the chip structure and effectively removing noise interference sources.

[0066] In a preferred embodiment, the sacrificial layer is a BARC layer. Most of the BARC layer is removed by ashing, and the residue of the sacrificial layer is removed by wet etching. Since the wet etching time is short, it does not affect the semiconductor layer or the chip structure (e.g., the first conductor layer on the sidewalls of the sacrificial layer, the pier structure 106a, and the bridge structure 110a on top of the sacrificial layer). Furthermore, a protective layer covers the semiconductor layer, and the exposed protective layer is covered by a first insulating layer, thus protecting the semiconductor layer. Similarly, the sidewalls of the first conductor layer are covered by a first insulating layer 105, the sidewalls of the pier structure 106a are covered by a second insulating layer 107, and the lower part of the bridge structure 110a is covered by a third insulating layer 109. The first insulating layer 105, the second insulating layer 107, and the third insulating layer 109 respectively protect the first conductor layer 103, the pier structure 106a, and the bridge structure 110a.

[0067] In a preferred embodiment, the sacrificial layer is amorphous carbon. The sacrificial layer is removed by oxidizing the amorphous carbon without affecting the semiconductor layer and the chip structure (e.g., the first conductor layer on the sidewall of the sacrificial layer, the pier structure 106a, and the bridge structure 110a on top of the sacrificial layer).

[0068] In a preferred embodiment, during the formation of the bridge pier, a resist mask layer with an inverted trapezoidal opening is first formed. The inverted trapezoidal opening prevents the second conductor layer falling into it from contacting the sidewall of the inverted trapezoidal opening, so that the second conductor layer falling into the inverted trapezoidal opening will not be affected during the subsequent removal of the resist mask layer.

[0069] In a preferred embodiment, a brush is used to remove the second conductor layer covering the resist mask layer to prevent the collapse of the second conductor layer from affecting the second conductor layer falling into the inverted trapezoidal opening.

[0070] In a preferred embodiment, a vapor deposition process is used to form the second semiconductor layer to prevent damage to the second resist mask layer PR2 during the deposition process to form the second conductor layer 106, thereby preventing defects from forming on the surface of the second resist mask layer PR2.

[0071] In a preferred embodiment, before forming the first insulating layer, the natural oxide layer formed by oxidation on the surface of the first conductor layer 103 is removed. Compared with the metal oxide layer formed by natural oxidation, the first insulating layer 105 formed by deposition process has better density to ensure the quality of the first insulating layer 105, thereby ensuring that it will not affect the reliability and quality of the subsequent chip structure formation.

[0072] In a preferred embodiment, the third insulating layer 109 covers the top of the pier structure 106a and the top of the sacrificial layer 108. The third insulating layer 109 above the pier structure 106a is used for the subsequent formation of the second chip structure, while the third insulating layer 109 on top of the sacrificial layer 108 protects the sacrificial layer 108 and supports the subsequently formed third conductor layer 110, preventing defects, dents, collapses, or other adverse effects from forming on the top of the sacrificial layer 108 due to its relatively soft texture during the formation of the third conductor layer 110.

[0073] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for fabricating a chip, comprising: A patterned first conductor layer is formed on the semiconductor layer; A first insulating layer is formed, which conformally covers the surface of the first conductor layer, the sidewalls of the openings in the first conductor layer, and the surface of the semiconductor layer exposed by the openings in the first conductor layer. A pier structure is formed on the first insulating layer; A sacrificial layer is formed between the bridge pier structures; A third insulating layer is formed on the pier structure, the third insulating layer covering the top of the pier structure and the top of the sacrificial layer; A bridge structure is formed on the third insulating layer; as well as Remove the sacrificial layer to form an air bridge structure; The sacrificial layer is either a BARC layer or an amorphous carbon layer. The method for forming the bridge pier structure includes: A patterned resist mask layer is formed, the patterned resist mask layer having inverted trapezoidal openings; A second conductor layer is formed, the second conductor layer comprising a first portion covering the resist mask layer and a second portion filling the opening, the first portion and the second portion having a height difference, the first portion forming a gap with the sidewall of the opening; Use a brush to remove the higher first part; After removing the resist mask layer, the lower second portion is retained to form the pier structure.

2. The chip fabrication method according to claim 1, wherein, The sacrificial layer is a BARC layer. The method for removing the sacrificial layer includes: ashing the sacrificial layer and removing the residue of the sacrificial layer by wet etching.

3. The chip fabrication method according to claim 1, wherein, The sacrificial layer is an amorphous carbon layer. The method for removing the sacrificial layer includes: oxidizing the amorphous carbon layer to form carbon dioxide, thereby eliminating the amorphous carbon.

4. The chip fabrication method according to claim 1, wherein, The method for forming the second conductor layer includes: forming the second conductor layer using a vapor deposition process.

5. The method for fabricating a chip according to claim 1, wherein, Before forming the first conductor layer, the process further includes forming a protective layer on the semiconductor layer, wherein the first conductor layer is located on the protective layer.

6. The method for fabricating a chip according to claim 1, wherein, Before forming the first insulating layer, the process also includes a step of removing the natural oxide layer on the surface of the first conductor layer.

7. The method for fabricating a chip according to claim 1, wherein, The step of forming a sacrificial layer between the pier structures includes: A sacrificial layer is formed covering the surface of the bridge pier structure and located between the bridge pier structures; Remove the sacrificial layer covering the surface of the pier structure, while retaining the sacrificial layer located between the pier structures, with the top of the remaining sacrificial layer flush with the top of the pier structure.

8. A chip formed using the chip fabrication method according to any one of claims 1-7, wherein, The first conductor layer, the first insulating layer, and the pier structure form the first chip structure, while the pier structure, the third insulating layer, and the bridge structure form the second chip structure.

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