3D structure die test layout design method supporting cross-hierarchy chain test and single-die self-test

Abstract

The application provides a 3D structure core particle test layout design method supporting cross-layer continuous testing and single-core particle self-testing, and the method comprises the following steps: a. designing a test point layout of a 3D stacked core particle, adopting a hexagonal arrangement mode for each layer of core particles, so that one layer-in test PIN is connected with six signal PINs in the same layer; and a vertical test channel is arranged, so that the layer-in test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. The application adapts to 3D stacking test full coverage, solves the pain point of "difficult to test interlayer signals" in the 3D structure through "layer-in hexagonal layout + vertical test channel", and realizes full-scene coverage of layer-in, interlayer and cross-core particle signals.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit testing, and more specifically relates to a 3D structure chip test layout design method that supports cross-layer cascade testing and single-chip self-testing. Background Technology

[0002] As VLSI rapidly develops towards high density, high bandwidth, and low latency, 3D structure chips (3DChiplets) have become a core technology solution to break through the physical limits of 2D planar integration due to their architectural advantages of "vertical stacking of multi-layer chips + through-silicon via interconnects". By stacking chips with different functions (such as computing chips, storage chips, and interface chips) vertically, they can significantly improve chip integration, shorten signal transmission paths, and reduce system power consumption. They have been widely used in high-end server CPUs, artificial intelligence chips, high-performance storage, and other fields.

[0003] However, the stacking characteristics of 3D structured chips make their testing far more challenging than 2D structures, and testing technology has become a key bottleneck restricting the mass production and application of 3D chips. Current core testing requirements for 3D structured chips include: verifying signal connectivity within layers, verifying the transmission integrity of vertical interconnects between layers, achieving accurate fault localization, and controlling test resource usage (avoiding excessive use of TSVs leading to a surge in packaging costs). However, existing technologies have the following significant shortcomings in addressing these requirements: 1. Inter-layer testing consumes excessive resources, leading to a surge in encapsulation costs: Existing 3D chip testing solutions mostly follow the approach of "direct stacking of 2D test layouts": each layer of chips has its own independent test pins and vertical test channels (TSVs), and the intra-layer test layout often uses a rectangular arrangement (one test pin covers four signal pins). This design leads to: The number of vertical test channels (TSVs) has increased dramatically: each layer needs to be configured with TSVs that match the number of test pins. When stacking 3 or more layers, the total number of TSVs can be 2-3 times that of 2D structures. This not only occupies a lot of packaging space (TSV apertures are usually 5-10μm, and dense arrangement can easily lead to the risk of chip cracking), but also increases the cost of 3D packaging by more than 30%. Inefficient intra-layer testing: The rectangular arrangement of intra-layer test pins has low coverage efficiency. To achieve full signal coverage, the number of test pins needs to be increased, which further exacerbates the redundancy of inter-layer test resources.

[0004] 2. Lack of independent layered control leads to poor test accuracy due to signal crosstalk between layers: Current 3D chip testing circuits mostly employ "overall enable" logic: during testing, all layer test pins and vertical channels are activated simultaneously, without designing independent control mechanisms for different layers. This design suffers from severe inter-layer signal crosstalk problems. When testing the signal of a certain layer, the test pins of adjacent layers will receive and feed back interference signals, causing the output signal to be distorted, making it impossible to accurately determine whether the fault is located in the target layer. During cross-layer testing, vertical channels of non-target layers can form "parasitic paths," causing test signals to be diverted and making it difficult to verify the true transmission performance of inter-layer interconnects (such as TSVs), with a false positive rate of over 15%.

[0005] 3. Inability to perform self-testing on a single core chip, resulting in difficulty in fault location and low testing efficiency: Existing 3D core testing solutions rely on a "multi-core stacking followed by overall testing" process: multiple cores must be vertically stacked and bonded before signals can be input through the top / bottom layer test interfaces to verify overall connectivity. This process has two major problems: Single-core faults cannot be detected in advance: If a single core itself has an intralayer signal fault (such as an open circuit at the factory), when the overall test fails after stacking, it is impossible to distinguish whether the fault originates from "inside the single core" or "interlayer damage during the stacking process". It is necessary to disassemble and re-test, which extends the test cycle by more than 50%. Redundancy in multi-layer testing steps: When testing chip paths spanning 3 or more layers, each complete path must be tested individually. There is no efficient segmented testing logic, and the testing time increases linearly with the number of stacked layers.

[0006] 4. Insufficient test coverage, with signal blind spots existing: Some solutions aim to reduce resource consumption by simplifying the intra-layer test layout (e.g., reducing the number of test pins) or omitting some inter-layer test channels. Incomplete signal coverage within the layer: The simplified test layout cannot cover the edge signal pins, causing some signals to remain in an "untested state" for a long time, which can easily lead to "hidden faults" (such as excessive signal delay) during mass production. Interlayer interconnect test blind zone: After omitting some TSV test channels, it is impossible to verify the integrity of all vertical interconnects. After 3D stacking, "local interlayer transmission interruption" may occur, affecting the overall function of the chip.

[0007] In summary, existing 3D chip testing technologies suffer from multiple bottlenecks in terms of resource consumption, test accuracy, efficiency, and coverage, making it difficult to meet the mass production testing requirements of high-density 3D stacked integrated circuits. Therefore, developing a test layout design method that adapts to the characteristics of 3D stacking, balances test efficiency and resource optimization, and supports single-chip self-testing and cross-layer cascade testing has become a key issue that urgently needs to be addressed in the current 3D chip technology field. Summary of the Invention

[0008] This invention aims to solve the problems existing in the prior art and proposes a 3D structure core testing layout design method that supports cross-layer cascade testing and single core self-testing.

[0009] To achieve the above objectives, the present invention employs the following technical solution: a 3D structure core testing layout design method supporting cross-layer cascade testing and single core self-testing, the method comprising the following steps: a. Design the test point layout of 3D stacked cores. Each core layer adopts a hexagonal arrangement so that the test PIN in one layer is connected to the 6 signal PINs in the same layer. At the same time, set up a vertical test channel so that the test PIN in each layer is connected to the corresponding test PIN in the adjacent layer through a vertical interconnection structure. b. Each core layer is equipped with an independent in-layer test circuit, and the in-layer test circuit is connected to the vertical test channel through a layer selection switch; c. Design the test process. Based on the test circuit, first perform single-core self-test, then perform cross-layer cascade test, and judge the signal connectivity within and between layers through the test results.

[0010] Preferably, the vertical interconnect structure in step a is a through-silicon via (TSV), and each in-layer test PIN is connected to the corresponding in-layer test PIN in the upper and lower layers through one TSV, and the connection point between the TSV and the in-layer test PIN is located at the center of the hexagonal layout.

[0011] Preferably, in step a, the in-layer test PINs of each core are equidistant from the six signal PINs of the same layer, and the in-layer test PINs of adjacent layers overlap in the vertical direction.

[0012] Preferably, the hierarchically independently controlled test circuit in step b includes: In-layer control module: Configures an independent control signal for each in-layer test PIN to control the opening or closing of the test PIN during in-layer testing; Layer selection module: Configures a layer selection signal for the vertical test channel to control the conduction or disconnection between adjacent layer test pins, thereby enabling selective activation of cross-layer test paths.

[0013] Preferably, the single-core self-test includes: Single-layer self-test: The layer control module opens one layer test PIN of a certain layer of the target core, closes other test PINs and all vertical test channels in the same layer, inputs test signals and detects the output to determine the signal connectivity in that layer. Single core cross-layer self-test: The vertical test channels of two adjacent layers within the target core are connected through the layer selection module, while the test PINs of other layers are closed. Test signals are input and cross-layer outputs are detected to determine the interlayer connectivity within the core.

[0014] Preferably, the cross-layer cascading test includes: Adjacent layer connectivity test: After completing the single core self-test, the vertical test channels of two adjacent cores are connected through the layer selection module, other test paths are closed, test signals are input and cross-core output is detected to determine the interlayer connectivity of adjacent cores; Cross-multi-layer cascade test: The vertical test channels of multiple stacked cores are sequentially connected through the cascade selection module, the non-path test PIN is closed, the test signal is input and the terminal output is detected to determine the signal connectivity across multiple cores.

[0015] Preferably, the output signal judgment criteria for the single-layer intralayer self-test and single-core cross-layer self-test are as follows: if the consistency between the output signal and the preset test signal meets the threshold requirement, it is determined that the corresponding intralayer or interlayer signal path is normal; if the signal is missing or the deviation exceeds the threshold, it is determined that there is an open circuit or short circuit fault.

[0016] Beneficial effects of this invention: This invention is adapted to full testing coverage of 3D stacking. By using "intra-layer hexagonal layout + vertical test channel", it solves the pain point of "difficulty in testing inter-layer signals" in 3D structures and achieves full-scene coverage of intra-layer, inter-layer, and cross-core signals. The efficiency and accuracy of testing are effectively improved, and the layered independent control circuit avoids cross-layer signal interference; the "segmented testing method" reduces the number of testing steps; the step-by-step execution of single-core self-test and cross-layer cascade test can accurately locate whether the fault is "inside a single core" or "between cores".

[0017] Compared to traditional 3D testing solutions, this method effectively reduces the amount of TSV used by sharing the test pins and vertical channels within the layer, thereby reducing the complexity and cost of 3D packaging. Detailed Implementation

[0018] To facilitate understanding of the present invention, a more comprehensive description will be given below. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0019] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. To facilitate understanding, the invention will now be described in a more complete manner. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] This implementation addresses the testing requirements of 3D stacked cores (i.e., formed by stacking two or more cores through vertical interconnection), and designs a collaborative test point layout of "intra-layer + inter-layer": The test points of each core are arranged in a hexagonal pattern (continuing the high-efficiency coverage advantage of the 2D structure). One in-layer test PIN (denoted as Pn, where n is the layer number) is equidistantly connected to the six signal PINs (S1-S6) in the same layer to ensure full coverage of the signal within a single layer. At the same time, a through-silicon via (TSV) is set at the center of each in-layer test PIN as a vertical test channel, so that Pn is vertically connected to the upper layer test PIN Pn+1 and the lower layer test PIN Pn-1 through the TSV.

[0021] The technical advantages of this layout are: 1. The hexagonal arrangement within the layer maintains the efficiency of "one test pin covering six signal pins" in the 2D structure, reducing the number of test pins within the layer; 2. The vertical test channel and the in-layer test PIN are designed to be in the same center, which minimizes the signal transmission path across layers and reduces signal attenuation; 3. The vertical projections of test pins on adjacent layers overlap to avoid misalignment interference of test channels in 3D stacking.

[0022] This embodiment also includes a test circuit with independent layered control: To achieve compatibility between "intra-layer independent testing" and "cross-layer precise testing" in 3D structures, this implementation design features a test circuit with independent layer control, mainly including: In-layer control module: Configures an independent control signal (e.g., Cntl_Pn_x, where n is the layer number and x is the test PIN number for that layer) for each test PIN within each layer, controlling the on / off state of the test PIN through high / low levels. This module ensures that when testing a signal within a certain layer, the target test PIN can be activated independently, avoiding signal interference from other test PINs in the same layer.

[0023] Layer selection module: Each vertical test channel is configured with an upward selection signal (Up_n, controlling the conduction of the nth layer test PIN with the (n+1)th layer) and a downward selection signal (Dn_n, controlling the conduction of the nth layer test PIN with the (n-1)th layer). Precise control of cross-layer paths is achieved through a "step-by-step enable" logic. For example, when testing the connectivity between the 2nd and 3rd layers, only the Up_2 and Dn_3 signals are activated, while other layer selection signals remain off to prevent signal crosstalk to the 1st or 4th layer.

[0024] The effect of this circuit design is that, through the dual logic of "intra-layer control + layer selection", it not only preserves the test independence within a single core, but also realizes the flexible switching of cross-layer test paths, thus solving the problem of "inter-layer signal interference causing inaccurate testing" in traditional 3D testing.

[0025] Based on the above layout and circuit, the 3D testing process of this embodiment is executed in two steps, balancing test completeness and efficiency: The purpose of single-core self-test is to verify the intra-layer and inter-layer signal connectivity within a single 3D core, including: 1. Single-layer self-test: Taking layer 2 as an example, activate P2_1 through the layer control module, and close other test PINs (P2_2-P2_m) and all Up / Dn signals in this layer (cut off the vertical channel); input test signals to P2_1 and check the outputs of S1-S6. If the outputs are all normal, it is determined that there is no fault in the signal path within layer 2.

[0026] 2. Single Core Cell Cross-Layer Self-Test: To verify the vertical connectivity between the 2nd and 3rd layers within the same core cell, activate the intra-layer control signals of P2_1 and P3_1, and simultaneously activate Up_2 and Dn_3 (to conduct the TSV between the two layers); input a test signal to P2_1 and detect the output of P3_1. If the output is normal, it is determined that the vertical channel between the 2nd and 3rd layers inside the core cell is fault-free.

[0027] Cross-layer cascading testing verifies signal connectivity between multiple stacked cores after the single-core self-test passes, including: 1. Adjacent Layer Cascading Test: When testing the connection between core A (top layer is layer 2) and core B (bottom layer is layer 3), activate P2_1 of A and P3_1 of B, and conduct Up_2 of A and Dn_3 of B (conducted through package interconnection); input a signal to P2_1 of A, detect the output of P3_1 of B, and determine the interlayer connectivity between the two cores.

[0028] 2. Multi-layer cascade test: When testing the three-layer path of core A-core B-core C, the "segmented test method" is adopted: first verify the connectivity between A and B, then verify the connectivity between B and C. If both segments are normal, the ABC path is directly determined to be normal, and there is no need to repeat the test of the complete path.

[0029] Compared to existing technologies, this invention is adapted to full testing coverage of 3D stacking. By using "intra-layer hexagonal layout + vertical test channel", it solves the pain point of "difficulty in testing inter-layer signals" in 3D structures and achieves full-scene coverage of intra-layer, inter-layer, and cross-core signals. The efficiency and accuracy of testing are effectively improved, and the layered independent control circuit avoids cross-layer signal interference; the "segmented testing method" reduces the redundancy of testing steps; the step-by-step execution of single-core self-test and cross-layer cascade test can accurately locate whether the fault is "inside a single core" or "between cores".

[0030] Compared to traditional 3D testing solutions, this method effectively reduces the amount of TSV used by sharing the test pins and vertical channels within the layer, thereby reducing the complexity and cost of 3D packaging.

[0031] In summary, this invention provides a complete testing solution for 3D structure chips, taking into account test coverage, efficiency and cost, and is suitable for mass production testing scenarios of high-density 3D stacked integrated circuits.

[0032] It should be understood that the above detailed description of the technical solutions of the present invention with reference to preferred embodiments is illustrative and not restrictive. Those skilled in the art can modify the technical solutions described in the embodiments or make equivalent substitutions for some of the technical features based on reading this specification; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 3D structure core testing layout design method supporting cross-layer cascade testing and single core self-testing, characterized in that, The method includes the following steps: a. Design the test point layout of 3D stacked cores. Each core layer adopts a hexagonal arrangement so that the test PIN in one layer is connected to the 6 signal PINs in the same layer. At the same time, set up a vertical test channel so that the test PIN in each layer is connected to the corresponding test PIN in the adjacent layer through a vertical interconnection structure. b. Each core layer is equipped with an independent in-layer test circuit, and the in-layer test circuit is connected to the vertical test channel through a layer selection switch; c. Design the test process. Based on the test circuit, first perform single-core self-test, then perform cross-layer cascade test, and judge the signal connectivity within and between layers through the test results.

2. The 3D structure core test layout design method supporting cross-layer cascade testing and single core self-testing according to claim 1, characterized in that, The vertical interconnect structure in step a is a through silicon via (TSV). Each in-layer test pin is connected to the corresponding in-layer test pins in the upper and lower layers through one TSV, and the connection point between the TSV and the in-layer test pin is located at the center of the hexagonal layout.

3. The 3D structure core test layout design method supporting cross-layer cascade testing and single core self-testing according to claim 1, characterized in that, In step a, the in-layer test PINs of each core are arranged equidistantly from the six signal PINs of the same layer, and the in-layer test PINs of adjacent layers overlap in the vertical direction.

4. The 3D structure core test layout design method supporting cross-layer cascade testing and single core self-testing according to claim 1, characterized in that, The independent in-layer test circuit in step b includes: In-layer control module: Configures an independent control signal for each in-layer test PIN to control the opening or closing of the test PIN during in-layer testing; Layer selection module: Configures a layer selection signal for the vertical test channel to control the conduction or disconnection between adjacent layer test pins, thereby enabling selective activation of cross-layer test paths.

5. The 3D structure core test layout design method supporting cross-layer cascade testing and single core self-testing according to claim 1, characterized in that, The single-core self-test includes: Single-layer self-test: The layer control module opens one layer test PIN of a certain layer of the target core, closes other test PINs and all vertical test channels in the same layer, inputs test signals and detects the output to determine the signal connectivity in that layer. Single core cross-layer self-test: The vertical test channels of two adjacent layers within the target core are connected through the layer selection module, while the test PINs of other layers are closed. Test signals are input and cross-layer outputs are detected to determine the interlayer connectivity within the core.

6. The 3D structure core test layout design method supporting cross-layer cascade testing and single core self-testing according to claim 1, characterized in that, The cross-layer cascading test includes: Adjacent layer connectivity test: After completing the single core self-test, the vertical test channels of two adjacent cores are connected through the layer selection module, other test paths are closed, test signals are input and cross-core output is detected to determine the interlayer connectivity of adjacent cores; Cross-multi-layer cascade test: The vertical test channels of multiple stacked cores are sequentially connected through the cascade selection module, the non-path test PIN is closed, the test signal is input and the terminal output is detected to determine the signal connectivity across multiple cores.

7. The 3D structure core test layout design method supporting cross-layer cascade testing and single core self-testing according to claim 5, characterized in that, The output signal judgment criteria for the single-layer internal self-test and single-core cross-layer self-test are as follows: if the consistency between the output signal and the preset test signal meets the threshold requirement, the corresponding signal path within or between layers is determined to be normal; if the signal is missing or the deviation exceeds the threshold, an open circuit or short circuit fault is determined to exist.